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QNX Operating System/Discussion/OSTech/Memory Management/List of Posts
Forum Topic - Memory Management: (6 Items)
   
Update
Vadim Malenboim
01/26/2009 6:30 AM
post20774
Memory Management   
Hello ,
My Hardware is PPC405 implemented in Virtex4 FPGA .
I'm using the procnto400 micro-kernel and the ml410 bsp downloaded from this site.

I have a question about the memory management in the kernel in general and in the relevant implementation in particular 
.

I assume and correct me if i'm wrong that the kernel and the bsp operates in virtual mode (according to ppc reference 
guide when MMU present the operating mode is virtual ).

In the bsp there are couple routines that set and activate the i-cache and the d-cache on the ram .
I assume and again correct me if i'm wrong that this is done for speeding system startup , because when the system is up
 the mmu takes place of memory including caching management.

1.Can anybody direct me to where the qnx memory model is described
anything more detailed than : http://www.qnx.co.jp/developers/docs/6.4.0/neutrino/sys_arch/proc.html#MEMMAN.

2.And can anybody describe the MMU interface and how is the TLB filled and when in kernel or in the bsp ?
3.Can I control the caching attributes in the TLB entries (the four most significant bits in the TLBLO )
Attachment: PDF PowerPc Processor Reference Guide.pdf 7.84 MB
Brian Stecher
01/26/2009 9:26 AM
post20776
Re: Memory Management   
On Mon, Jan 26, 2009 at 06:31:43AM -0500, Vadim Malenboim wrote:
> I assume and correct me if i'm wrong that the kernel and the bsp operates in virtual mode (according to ppc reference 
guide when MMU present the operating mode is virtual ).

The startup program runs in real mode, but once the kernel has initialized
everything else is virtual.

> In the bsp there are couple routines that set and activate the i-cache and the d-cache on the ram .
> I assume and again correct me if i'm wrong that this is done for speeding system startup , because when the system is 
up the mmu takes place of memory including caching management.

Correct.

> 1.Can anybody direct me to where the qnx memory model is described
> anything more detailed than : http://www.qnx.co.jp/developers/docs/6.4.0/neutrino/sys_arch/proc.html#MEMMAN.

There isn't anything more for user facing documentation. There
are:

http://community.qnx.com/sf/wiki/do/viewPage/projects.core_os/wiki/Vmm_data_structures
http://community.qnx.com/sf/wiki/do/viewPage/projects.core_os/wiki/Vmm_algorithms
http://community.qnx.com/integration/viewcvs/viewcvs.cgi/trunk/services/system/doc/mm-cpu-specific?root=coreos_pub&rev=153052&system=exsy1001&view=markup

which talk about the internal data structures.

> 2.
And can anybody describe the MMU interface and how is the TLB filled and when in kernel or in the bsp ?

The TLB is filled only by the kernel. This is done in the TLB miss exception 
handling routines (aside from some corner cases).  That code is in
services/system/ker/ppc/400/vm400.s. Look for the "tlb_miss" macro.


> 3.Can I control the caching attributes in the TLB entries (the four most significant bits in the TLBLO )

If you do a mmap() with PROT_NOCACHE set, you'll turn on the I and G bits
(if PROT_EXEC is on, the G-bit will be left off). If you need more control
than that, you can use the shm_ctl_special() API with the PPC_SPECIAL_*
macros (defined in <ppc/cpu.h>) to control the bits directly at the cost
of making your code not portable to other architectures. 


-- 
Brian Stecher (bstecher@qnx.com)        QNX Software Systems
phone: +1 (613) 591-0931 (voice)        175 Terence Matthews Cr.
       +1 (613) 591-3579 (fax)          Kanata, Ontario, Canada K2M 1W8
Vadim Malenboim
01/27/2009 9:01 AM
post20830
Re: Memory Management   
Thank you very much for the detailed response .

A few more question : 

1.When does the caching (I+D) initialization done ? Is it done before the startup program ?
Can i control it for performance evaluations only (wirte 0 to the iccr and dccr registers should do it ,no?)

2.the cpu_startup calls cpuconfig1 that initializing i+d caches and its happens before the startup program
is this the place where the caches are initialized 

3. what is the first thing that runs when i start the bsp image ?
there is _main() routine in my startup/ppc directory that runs cpu_starup and than the startup program    main,  is this
 the first entry point of the bsp ?
Brian Stecher
01/27/2009 9:36 AM
post20837
Re: Memory Management   
On Tue, Jan 27, 2009 at 09:01:46AM -0500, Vadim Malenboim wrote:
> 1.When does the caching (I+D) initialization done ? Is it done before the startup program ?

The startup program does it during cpuconfig1(), as you've noted, which runs
very early on in the process. Some IPL's/rom monitors also will also enable 
the cache before startup is invoked.

> Can i control it for performance evaluations only (wirte 0 to the iccr and dccr registers should do it ,no?)

You might be able to get startup to run with the caches off, but the OS itself
will not operate properly unless they're enabled and properly initialized.

> 
> 2.the cpu_startup calls cpuconfig1 that initializing i+d caches and its happens before the startup program
> is this the place where the caches are initialized 

This is all part of the startup program - the cpuconfig1() routine does
get invoked before the board specific portion controlled by the main()
routine gets run.

> 3. what is the first thing that runs when i start the bsp image ?
> there is _main() routine in my startup/ppc directory that runs cpu_starup and than the startup program    main,  is 
this the first entry point of the bsp ?

The _start symbol in lib/startup/ppc/cstart.s is where execution begins
in the image, but it does very little before transferring control to
the _main() routine.


-- 
Brian Stecher (bstecher@qnx.com)        QNX Software Systems
phone: +1 (613) 591-0931 (voice)        175 Terence Matthews Cr.
       +1 (613) 591-3579 (fax)          Kanata, Ontario, Canada K2M 1W8
Vadim Malenboim
01/28/2009 9:39 AM
post20919
Re: Memory Management   
Brian Hello ,
Thank you again.
Your answers fill me a lot of blanks that i have .

You said :"You might be able to get startup to run with the caches off, but the OS itself
                 will not operate properly unless they're enabled and properly initialized."

I'm trying to do just that to check the caches influence on the startup program , more than that i inserted simple loop 
in the beginning of the startup main that runs for 10 sec and want to check the time with and without cache.

I modified the ppcv_cpuconfig1_400 routine, once no to do anything and once to write 0 at the iccr and the dccr regs .
Nothing that i do seems to influence the performance of the 10 sec loop, the time remains the same with registers set or
 cleared .

Thank you again for you thorough answers they help me a lot .

Vadim.
Brian Stecher
01/30/2009 1:14 PM
post21117
Re: Memory Management   
I tried the attached code on a real 405 (200MHz). The call to timing_test() 
was inserted just before the print_syspage() in main.c. It reported:

	loop time with caches on/off=42/435

which indicates a 10-fold decrease in performance of the loop with
the caches off.

On Wed, Jan 28, 2009 at 09:39:57AM -0500, Vadim Malenboim wrote:
> Brian Hello ,
> Thank you again.
> Your answers fill me a lot of blanks that i have .
> 
> You said :"You might be able to get startup to run with the caches off, but the OS itself
>                  will not operate properly unless they're enabled and properly initialized."
> 
> I'm trying to do just that to check the caches influence on the startup program , more than that i inserted simple 
loop in the beginning of the startup main that runs for 10 sec and want to check the time with and without cache.
> 
> I modified the ppcv_cpuconfig1_400 routine, once no to do anything and once to write 0 at the iccr and the dccr regs .

> Nothing that i do seems to influence the performance of the 10 sec loop, the time remains the same with registers set 
or cleared .
> 
> Thank you again for you thorough answers they help me a lot .
> 
> Vadim.
> 
> 
> _______________________________________________
> OSTech
> http://community.qnx.com/sf/go/post20919
> 

-- 
Brian Stecher (bstecher@qnx.com)        QNX Software Systems
phone: +1 (613) 591-0931 (voice)        175 Terence Matthews Cr.
       +1 (613) 591-3579 (fax)          Kanata, Ontario, Canada K2M 1W8
Attachment: Text tryme.c 1.68 KB

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