05/29/2012 5:49 AM
post93328
|
we are using QNX 6.5.0.Is it support for PCI Express.If supports we need sample application code for PCI Express data
transfer between applications.
|
|
|
05/30/2012 8:42 AM
post93370
|
Please can you be a bit more specific. What device are you trying to
access and what information do you need about data transfer? Are you
trying to access configuration space or device I/O space?
--
Hugh Brown
QNX Software Systems Limited
1001 Farrar Rd.,
Ottawa. ON. K2K 0B3.
Telephone: 613-591-0931
On 12-05-29 5:49 AM, "sri lakshmi" <community-noreply@qnx.com> wrote:
>we are using QNX 6.5.0.Is it support for PCI Express.If supports we need
>sample application code for PCI Express data transfer between
>applications.
>
>
>
>_______________________________________________
>
>General
>http://community.qnx.com/sf/go/post93328
>To cancel your subscription to this discussion, please e-mail
>general-community-unsubscribe@community.qnx.com
|
|
|
05/30/2012 9:00 AM
post93371
|
Actually in my project I need to transfer data from Intel Advantech board to
FPGA board through PCI Express. from FPGA board it transfers data to
different cards like card c, card D like that. Here I need to access
configuration space.
-----Original Message-----
From: Hugh Brown [mailto:community-noreply@qnx.com]
Sent: Wednesday, May 30, 2012 6:07 PM
To: general-community@community.qnx.com
Subject: Re: PCI Express
Please can you be a bit more specific. What device are you trying to
access and what information do you need about data transfer? Are you
trying to access configuration space or device I/O space?
--
Hugh Brown
QNX Software Systems Limited
1001 Farrar Rd.,
Ottawa. ON. K2K 0B3.
Telephone: 613-591-0931
On 12-05-29 5:49 AM, "sri lakshmi" <community-noreply@qnx.com> wrote:
>we are using QNX 6.5.0.Is it support for PCI Express.If supports we need
>sample application code for PCI Express data transfer between
>applications.
>
>
>
>_______________________________________________
>
>General
>http://community.qnx.com/sf/go/post93328
>To cancel your subscription to this discussion, please e-mail
>general-community-unsubscribe@community.qnx.com
_______________________________________________
General
http://community.qnx.com/sf/go/post93370
To cancel your subscription to this discussion, please e-mail
general-community-unsubscribe@community.qnx.com
-----
No virus found in this message.
Checked by AVG - www.avg.com
Version: 2012.0.2176 / Virus Database: 2425/5033 - Release Date: 05/30/12
|
|
|
05/30/2012 9:14 AM
post93373
|
Take a look at the pci_attach* and pci_read_config() functions in the help
files to see how to read configuration space and attach your application
to a device.
--
Hugh Brown
QNX Software Systems Limited
1001 Farrar Rd.,
Ottawa. ON. K2K 0B3.
Telephone: 613-591-0931
On 12-05-30 8:56 AM, "srilakshmi" <community-noreply@qnx.com> wrote:
>Actually in my project I need to transfer data from Intel Advantech board
>to
>FPGA board through PCI Express. from FPGA board it transfers data to
>different cards like card c, card D like that. Here I need to access
>configuration space.
>
>-----Original Message-----
>From: Hugh Brown [mailto:community-noreply@qnx.com]
>Sent: Wednesday, May 30, 2012 6:07 PM
>To: general-community@community.qnx.com
>Subject: Re: PCI Express
>
>Please can you be a bit more specific. What device are you trying to
>access and what information do you need about data transfer? Are you
>trying to access configuration space or device I/O space?
>
>--
>Hugh Brown
>QNX Software Systems Limited
>1001 Farrar Rd.,
>Ottawa. ON. K2K 0B3.
>Telephone: 613-591-0931
>
>
>
>
>
>
>
>On 12-05-29 5:49 AM, "sri lakshmi" <community-noreply@qnx.com> wrote:
>
>>we are using QNX 6.5.0.Is it support for PCI Express.If supports we need
>>sample application code for PCI Express data transfer between
>>applications.
>>
>>
>>
>>_______________________________________________
>>
>>General
>>http://community.qnx.com/sf/go/post93328
>>To cancel your subscription to this discussion, please e-mail
>>general-community-unsubscribe@community.qnx.com
>
>
>
>
>
>_______________________________________________
>
>General
>http://community.qnx.com/sf/go/post93370
>To cancel your subscription to this discussion, please e-mail
>general-community-unsubscribe@community.qnx.com
>
>
>-----
>No virus found in this message.
>Checked by AVG - www.avg.com
>Version: 2012.0.2176 / Virus Database: 2425/5033 - Release Date: 05/30/12
>
>
>
>
>
>
>_______________________________________________
>
>General
>http://community.qnx.com/sf/go/post93371
>To cancel your subscription to this discussion, please e-mail
>general-community-unsubscribe@community.qnx.com
|
|
|
06/01/2012 2:14 AM
post93441
|
I need sample c code for PCIe data transfer in QNX.
-----Original Message-----
From: Hugh Brown [mailto:community-noreply@qnx.com]
Sent: Wednesday, May 30, 2012 6:38 PM
To: general-community@community.qnx.com
Subject: Re: PCI Express
Take a look at the pci_attach* and pci_read_config() functions in the help
files to see how to read configuration space and attach your application
to a device.
--
Hugh Brown
QNX Software Systems Limited
1001 Farrar Rd.,
Ottawa. ON. K2K 0B3.
Telephone: 613-591-0931
On 12-05-30 8:56 AM, "srilakshmi" <community-noreply@qnx.com> wrote:
>Actually in my project I need to transfer data from Intel Advantech board
>to
>FPGA board through PCI Express. from FPGA board it transfers data to
>different cards like card c, card D like that. Here I need to access
>configuration space.
>
>-----Original Message-----
>From: Hugh Brown [mailto:community-noreply@qnx.com]
>Sent: Wednesday, May 30, 2012 6:07 PM
>To: general-community@community.qnx.com
>Subject: Re: PCI Express
>
>Please can you be a bit more specific. What device are you trying to
>access and what information do you need about data transfer? Are you
>trying to access configuration space or device I/O space?
>
>--
>Hugh Brown
>QNX Software Systems Limited
>1001 Farrar Rd.,
>Ottawa. ON. K2K 0B3.
>Telephone: 613-591-0931
>
>
>
>
>
>
>
>On 12-05-29 5:49 AM, "sri lakshmi" <community-noreply@qnx.com> wrote:
>
>>we are using QNX 6.5.0.Is it support for PCI Express.If supports we need
>>sample application code for PCI Express data transfer between
>>applications.
>>
>>
>>
>>_______________________________________________
>>
>>General
>>http://community.qnx.com/sf/go/post93328
>>To cancel your subscription to this discussion, please e-mail
>>general-community-unsubscribe@community.qnx.com
>
>
>
>
>
>_______________________________________________
>
>General
>http://community.qnx.com/sf/go/post93370
>To cancel your subscription to this discussion, please e-mail
>general-community-unsubscribe@community.qnx.com
>
>
>-----
>No virus found in this message.
>Checked by AVG - www.avg.com
>Version: 2012.0.2176 / Virus Database: 2425/5033 - Release Date: 05/30/12
>
>
>
>
>
>
>_______________________________________________
>
>General
>http://community.qnx.com/sf/go/post93371
>To cancel your subscription to this discussion, please e-mail
>general-community-unsubscribe@community.qnx.com
_______________________________________________
General
http://community.qnx.com/sf/go/post93373
To cancel your subscription to this discussion, please e-mail
general-community-unsubscribe@community.qnx.com
-----
No virus found in this message.
Checked by AVG - www.avg.com
Version: 2012.0.2176 / Virus Database: 2425/5034 - Release Date: 05/30/12
|
|
|
06/01/2012 8:56 AM
post93450
|
Here is some sample code to allow you to attach to a PCI device and read
the configuration space. You run the program as 'pci_att 0xVendor
0xDevice' where Vendor and Device are the vendor and device Ids of the
device you are concerned about.
--
Hugh Brown
QNX Software Systems Limited
1001 Farrar Rd.,
Ottawa. ON. K2K 0B3.
Telephone: 613-591-0931
On 12-06-01 2:07 AM, "srilakshmi" <community-noreply@qnx.com> wrote:
>I need sample c code for PCIe data transfer in QNX.
>
>-----Original Message-----
>From: Hugh Brown [mailto:community-noreply@qnx.com]
>Sent: Wednesday, May 30, 2012 6:38 PM
>To: general-community@community.qnx.com
>Subject: Re: PCI Express
>
>Take a look at the pci_attach* and pci_read_config() functions in the help
>files to see how to read configuration space and attach your application
>to a device.
>
>--
>Hugh Brown
>QNX Software Systems Limited
>1001 Farrar Rd.,
>Ottawa. ON. K2K 0B3.
>Telephone: 613-591-0931
>
>
>
>
>
>
>
>On 12-05-30 8:56 AM, "srilakshmi" <community-noreply@qnx.com> wrote:
>
>>Actually in my project I need to transfer data from Intel Advantech board
>>to
>>FPGA board through PCI Express. from FPGA board it transfers data to
>>different cards like card c, card D like that. Here I need to access
>>configuration space.
>>
>>-----Original Message-----
>>From: Hugh Brown [mailto:community-noreply@qnx.com]
>>Sent: Wednesday, May 30, 2012 6:07 PM
>>To: general-community@community.qnx.com
>>Subject: Re: PCI Express
>>
>>Please can you be a bit more specific. What device are you trying to
>>access and what information do you need about data transfer? Are you
>>trying to access configuration space or device I/O space?
>>
>>--
>>Hugh Brown
>>QNX Software Systems Limited
>>1001 Farrar Rd.,
>>Ottawa. ON. K2K 0B3.
>>Telephone: 613-591-0931
>>
>>
>>
>>
>>
>>
>>
>>On 12-05-29 5:49 AM, "sri lakshmi" <community-noreply@qnx.com> wrote:
>>
>>>we are using QNX 6.5.0.Is it support for PCI Express.If supports we need
>>>sample application code for PCI Express data transfer between
>>>applications.
>>>
>>>
>>>
>>>_______________________________________________
>>>
>>>General
>>>http://community.qnx.com/sf/go/post93328
>>>To cancel your subscription to this discussion, please e-mail
>>>general-community-unsubscribe@community.qnx.com
>>
>>
>>
>>
>>
>>_______________________________________________
>>
>>General
>>http://community.qnx.com/sf/go/post93370
>>To cancel your subscription to this discussion, please e-mail
>>general-community-unsubscribe@community.qnx.com
>>
>>
>>-----
>>No virus found in this message.
>>Checked by AVG - www.avg.com
>>Version: 2012.0.2176 / Virus Database: 2425/5033 - Release Date: 05/30/12
>>
>>
>>
>>
>>
>>
>>_______________________________________________
>>
>>General
>>http://community.qnx.com/sf/go/post93371
>>To cancel your subscription to this discussion, please e-mail
>>general-community-unsubscribe@community.qnx.com
>
>
>
>
>
>_______________________________________________
>
>General
>http://community.qnx.com/sf/go/post93373
>To cancel your subscription to this discussion, please e-mail
>general-community-unsubscribe@community.qnx.com
>
>-----
>No virus found in this message.
>Checked by AVG - www.avg.com
>Version: 2012.0.2176 / Virus...
|
|
|
06/01/2012 12:03 PM
post93460
|
Hugh,
the flags PCI_USE_MSI and PCI_USE_MSIX are not documented.
What are their semantic? Does it work with the current version of
pci-bois-v2 ?
Best Regards
--Armin
Hugh Brown wrote:
> Here is some sample code to allow you to attach to a PCI device and read
> the configuration space. You run the program as 'pci_att 0xVendor
> 0xDevice' where Vendor and Device are the vendor and device Ids of the
> device you are concerned about.
>
|
|
|
06/01/2012 12:55 PM
post93463
|
These flags are to inform the pci-bios-v2 server to either use MSI or MSI-X interrupts rather than the default irqs. If
a device can use both MSI and MSI-X interrupts and the MSI flag is specified, then only MSI interrupts will be allocated
.
Sent from Blackberry
From: Armin Steinhoff [mailto:community-noreply@qnx.com]
Sent: Friday, June 01, 2012 12:00 PM
To: general-community@community.qnx.com <general-community@community.qnx.com>
Cc: Info System - IS Notifications; Info System - IS Notifications
Subject: Re: PCI Express
Hugh,
the flags PCI_USE_MSI and PCI_USE_MSIX are not documented.
What are their semantic? Does it work with the current version of pci-bois-v2 ?
Best Regards
--Armin
Hugh Brown wrote:
Here is some sample code to allow you to attach to a PCI device and read
the configuration space. You run the program as 'pci_att 0xVendor
0xDevice' where Vendor and Device are the vendor and device Ids of the
device you are concerned about.
|
|
|
06/02/2012 6:37 PM
post93471
|
Hugh,
many thanks for the info. is there a way to use this flags for e.g.
pci_find_device?
Regards
Armin
Hugh Brown wrote:
> These flags are to inform the pci-bios-v2 server to either use MSI or
> MSI-X interrupts rather than the default irqs. If a device can use
> both MSI and MSI-X interrupts and the MSI flag is specified, then only
> MSI interrupts will be allocated.
>
> Sent from Blackberry
>
> *From*: Armin Steinhoff [mailto:community-noreply@qnx.com]
> *Sent*: Friday, June 01, 2012 12:00 PM
> *To*: general-community@community.qnx.com
> <general-community@community.qnx.com>
> *Cc*: Info System - IS Notifications; Info System - IS Notifications
> *Subject*: Re: PCI Express
>
> Hugh,
>
> the flags PCI_USE_MSI and PCI_USE_MSIX are not documented.
>
> What are their semantic? Does it work with the current version of
> pci-bois-v2 ?
>
> Best Regards
>
> --Armin
>
>
>
> Hugh Brown wrote:
>> Here is some sample code to allow you to attach to a PCI device and read
>> the configuration space. You run the program as 'pci_att 0xVendor
>> 0xDevice' where Vendor and Device are the vendor and device Ids of the
>> device you are concerned about.
>>
|
|
|
06/03/2012 7:53 AM
post93472
|
Armin,
No, the flags are only used in the pci_attach_device() function.
Hugh.
--
Hugh Brown
QNX Software Systems Limited
1001 Farrar Rd.,
Ottawa. ON. K2K 0B3.
Telephone: 613-591-0931
From: Armin Steinhoff <community-noreply@qnx.com<mailto:community-noreply@qnx.com>>
Reply-To: "general-community@community.qnx.com<mailto:general-community@community.qnx.com>" <general-community@
community.qnx.com<mailto:general-community@community.qnx.com>>
Date: Saturday, 2 June, 2012 6:33 PM
To: "general-community@community.qnx.com<mailto:general-community@community.qnx.com>" <general-community@community.
qnx.com<mailto:general-community@community.qnx.com>>
Cc: Info System - IS Notifications <is-notifications@qnx.com<mailto:is-notifications@qnx.com>>, Info System - IS
Notifications <is-notifications@qnx.com<mailto:is-notifications@qnx.com>>
Subject: Re: PCI Express
Hugh,
many thanks for the info. is there a way to use this flags for e.g. pci_find_device?
Regards
Armin
Hugh Brown wrote:
These flags are to inform the pci-bios-v2 server to either use MSI or MSI-X interrupts rather than the default irqs. If
a device can use both MSI and MSI-X interrupts and the MSI flag is specified, then only MSI interrupts will be allocated
.
Sent from Blackberry
From: Armin Steinhoff [mailto:community-noreply@qnx.com]
Sent: Friday, June 01, 2012 12:00 PM
To: general-community@community.qnx.com<mailto:general-community@community.qnx.com> <general-community@community.qnx.
com><mailto:general-community@community.qnx.com>
Cc: Info System - IS Notifications; Info System - IS Notifications
Subject: Re: PCI Express
Hugh,
the flags PCI_USE_MSI and PCI_USE_MSIX are not documented.
What are their semantic? Does it work with the current version of pci-bois-v2 ?
Best Regards
--Armin
Hugh Brown wrote:
Here is some sample code to allow you to attach to a PCI device and read
the configuration space. You run the program as 'pci_att 0xVendor
0xDevice' where Vendor and Device are the vendor and device Ids of the
device you are concerned about.
|
|
|
06/02/2012 1:37 AM
post93467
|
We are able to detect the device and read configuration space. when we are
sending data from Intel to FPGA board it is able to read 1 byte of data only
that means sending only one request. But in my project I need to transfer
some bytes of data from Intel board to FPGA board and able to receive data
from FPGA board to Intel board.
-----Original Message-----
From: Hugh Brown [mailto:community-noreply@qnx.com]
Sent: Friday, June 01, 2012 6:22 PM
To: general-community@community.qnx.com
Subject: Re: PCI Express
Here is some sample code to allow you to attach to a PCI device and read the
configuration space. You run the program as 'pci_att 0xVendor 0xDevice'
where Vendor and Device are the vendor and device Ids of the device you are
concerned about.
--
Hugh Brown
QNX Software Systems Limited
1001 Farrar Rd.,
Ottawa. ON. K2K 0B3.
Telephone: 613-591-0931
On 12-06-01 2:07 AM, "srilakshmi" <community-noreply@qnx.com> wrote:
>I need sample c code for PCIe data transfer in QNX.
>
>-----Original Message-----
>From: Hugh Brown [mailto:community-noreply@qnx.com]
>Sent: Wednesday, May 30, 2012 6:38 PM
>To: general-community@community.qnx.com
>Subject: Re: PCI Express
>
>Take a look at the pci_attach* and pci_read_config() functions in the help
>files to see how to read configuration space and attach your application
>to a device.
>
>--
>Hugh Brown
>QNX Software Systems Limited
>1001 Farrar Rd.,
>Ottawa. ON. K2K 0B3.
>Telephone: 613-591-0931
>
>
>
>
>
>
>
>On 12-05-30 8:56 AM, "srilakshmi" <community-noreply@qnx.com> wrote:
>
>>Actually in my project I need to transfer data from Intel Advantech board
>>to
>>FPGA board through PCI Express. from FPGA board it transfers data to
>>different cards like card c, card D like that. Here I need to access
>>configuration space.
>>
>>-----Original Message-----
>>From: Hugh Brown [mailto:community-noreply@qnx.com]
>>Sent: Wednesday, May 30, 2012 6:07 PM
>>To: general-community@community.qnx.com
>>Subject: Re: PCI Express
>>
>>Please can you be a bit more specific. What device are you trying to
>>access and what information do you need about data transfer? Are you
>>trying to access configuration space or device I/O space?
>>
>>--
>>Hugh Brown
>>QNX Software Systems Limited
>>1001 Farrar Rd.,
>>Ottawa. ON. K2K 0B3.
>>Telephone: 613-591-0931
>>
>>
>>
>>
>>
>>
>>
>>On 12-05-29 5:49 AM, "sri lakshmi" <community-noreply@qnx.com> wrote:
>>
>>>we are using QNX 6.5.0.Is it support for PCI Express.If supports we need
>>>sample application code for PCI Express data transfer between
>>>applications.
>>>
>>>
>>>
>>>_______________________________________________
>>>
>>>General
>>>http://community.qnx.com/sf/go/post93328
>>>To cancel your subscription to this discussion, please e-mail
>>>general-community-unsubscribe@community.qnx.com
>>
>>
>>
>>
>>
>>_______________________________________________
>>
>>General
>>http://community.qnx.com/sf/go/post93370
>>To cancel your subscription to this discussion, please e-mail
>>general-community-unsubscribe@community.qnx.com
>>
>>
>>-----
>>No virus found in this message.
>>Checked by AVG - www.avg.com
>>Version: 2012.0.2176 / Virus Database: 2425/5033 - Release Date:...
View Full Message
|
|
|
06/03/2012 7:55 AM
post93473
|
I have no idea how your FPGA works, so am unable to help you with data
transfer.
--
Hugh Brown
QNX Software Systems Limited
1001 Farrar Rd.,
Ottawa. ON. K2K 0B3.
Telephone: 613-591-0931
On 12-06-02 1:19 AM, "srilakshmi" <community-noreply@qnx.com> wrote:
>We are able to detect the device and read configuration space. when we are
>sending data from Intel to FPGA board it is able to read 1 byte of data
>only
>that means sending only one request. But in my project I need to transfer
>some bytes of data from Intel board to FPGA board and able to receive data
>from FPGA board to Intel board.
>
>-----Original Message-----
>From: Hugh Brown [mailto:community-noreply@qnx.com]
>Sent: Friday, June 01, 2012 6:22 PM
>To: general-community@community.qnx.com
>Subject: Re: PCI Express
>
>Here is some sample code to allow you to attach to a PCI device and read
>the
>configuration space. You run the program as 'pci_att 0xVendor 0xDevice'
>where Vendor and Device are the vendor and device Ids of the device you
>are
>concerned about.
>
>--
>Hugh Brown
>QNX Software Systems Limited
>1001 Farrar Rd.,
>Ottawa. ON. K2K 0B3.
>Telephone: 613-591-0931
>
>
>
>
>
>
>
>On 12-06-01 2:07 AM, "srilakshmi" <community-noreply@qnx.com> wrote:
>
>>I need sample c code for PCIe data transfer in QNX.
>>
>>-----Original Message-----
>>From: Hugh Brown [mailto:community-noreply@qnx.com]
>>Sent: Wednesday, May 30, 2012 6:38 PM
>>To: general-community@community.qnx.com
>>Subject: Re: PCI Express
>>
>>Take a look at the pci_attach* and pci_read_config() functions in the
>>help
>>files to see how to read configuration space and attach your application
>>to a device.
>>
>>--
>>Hugh Brown
>>QNX Software Systems Limited
>>1001 Farrar Rd.,
>>Ottawa. ON. K2K 0B3.
>>Telephone: 613-591-0931
>>
>>
>>
>>
>>
>>
>>
>>On 12-05-30 8:56 AM, "srilakshmi" <community-noreply@qnx.com> wrote:
>>
>>>Actually in my project I need to transfer data from Intel Advantech
>>>board
>>>to
>>>FPGA board through PCI Express. from FPGA board it transfers data to
>>>different cards like card c, card D like that. Here I need to access
>>>configuration space.
>>>
>>>-----Original Message-----
>>>From: Hugh Brown [mailto:community-noreply@qnx.com]
>>>Sent: Wednesday, May 30, 2012 6:07 PM
>>>To: general-community@community.qnx.com
>>>Subject: Re: PCI Express
>>>
>>>Please can you be a bit more specific. What device are you trying to
>>>access and what information do you need about data transfer? Are you
>>>trying to access configuration space or device I/O space?
>>>
>>>--
>>>Hugh Brown
>>>QNX Software Systems Limited
>>>1001 Farrar Rd.,
>>>Ottawa. ON. K2K 0B3.
>>>Telephone: 613-591-0931
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>On 12-05-29 5:49 AM, "sri lakshmi" <community-noreply@qnx.com> wrote:
>>>
>>>>we are using QNX 6.5.0.Is it support for PCI Express.If supports we
>>>>need
>>>>sample application code for PCI Express data transfer between
>>>>applications.
>>>>
>>>>
>>>>
>>>>_______________________________________________
>>>>
>>>>General
>>>>http://community.qnx.com/sf/go/post93328
>>>>To cancel your subscription to this discussion, please...
View Full Message
|
|
|
06/04/2012 12:33 AM
post93478
|
Hugh Brown,
I need help regarding when request is sending from FPGA to INTEL board how
INTEL Board recognize that Request? Is their any functions and commands in
QNX?
Srilakshmi
-----Original Message-----
From: Hugh Brown [mailto:community-noreply@qnx.com]
Sent: Sunday, June 03, 2012 5:21 PM
To: general-community@community.qnx.com
Subject: Re: PCI Express
I have no idea how your FPGA works, so am unable to help you with data
transfer.
--
Hugh Brown
QNX Software Systems Limited
1001 Farrar Rd.,
Ottawa. ON. K2K 0B3.
Telephone: 613-591-0931
On 12-06-02 1:19 AM, "srilakshmi" <community-noreply@qnx.com> wrote:
>We are able to detect the device and read configuration space. when we are
>sending data from Intel to FPGA board it is able to read 1 byte of data
>only
>that means sending only one request. But in my project I need to transfer
>some bytes of data from Intel board to FPGA board and able to receive data
>from FPGA board to Intel board.
>
>-----Original Message-----
>From: Hugh Brown [mailto:community-noreply@qnx.com]
>Sent: Friday, June 01, 2012 6:22 PM
>To: general-community@community.qnx.com
>Subject: Re: PCI Express
>
>Here is some sample code to allow you to attach to a PCI device and read
>the
>configuration space. You run the program as 'pci_att 0xVendor 0xDevice'
>where Vendor and Device are the vendor and device Ids of the device you
>are
>concerned about.
>
>--
>Hugh Brown
>QNX Software Systems Limited
>1001 Farrar Rd.,
>Ottawa. ON. K2K 0B3.
>Telephone: 613-591-0931
>
>
>
>
>
>
>
>On 12-06-01 2:07 AM, "srilakshmi" <community-noreply@qnx.com> wrote:
>
>>I need sample c code for PCIe data transfer in QNX.
>>
>>-----Original Message-----
>>From: Hugh Brown [mailto:community-noreply@qnx.com]
>>Sent: Wednesday, May 30, 2012 6:38 PM
>>To: general-community@community.qnx.com
>>Subject: Re: PCI Express
>>
>>Take a look at the pci_attach* and pci_read_config() functions in the
>>help
>>files to see how to read configuration space and attach your application
>>to a device.
>>
>>--
>>Hugh Brown
>>QNX Software Systems Limited
>>1001 Farrar Rd.,
>>Ottawa. ON. K2K 0B3.
>>Telephone: 613-591-0931
>>
>>
>>
>>
>>
>>
>>
>>On 12-05-30 8:56 AM, "srilakshmi" <community-noreply@qnx.com> wrote:
>>
>>>Actually in my project I need to transfer data from Intel Advantech
>>>board
>>>to
>>>FPGA board through PCI Express. from FPGA board it transfers data to
>>>different cards like card c, card D like that. Here I need to access
>>>configuration space.
>>>
>>>-----Original Message-----
>>>From: Hugh Brown [mailto:community-noreply@qnx.com]
>>>Sent: Wednesday, May 30, 2012 6:07 PM
>>>To: general-community@community.qnx.com
>>>Subject: Re: PCI Express
>>>
>>>Please can you be a bit more specific. What device are you trying to
>>>access and what information do you need about data transfer? Are you
>>>trying to access configuration space or device I/O space?
>>>
>>>--
>>>Hugh Brown
>>>QNX Software Systems Limited
>>>1001 Farrar Rd.,
>>>Ottawa. ON. K2K 0B3.
>>>Telephone: 613-591-0931
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>On 12-05-29 5:49 AM, "sri lakshmi" <community-noreply@qnx.com> wrote:
>>>
>>>>we are using QNX 6.5.0.Is it support for PCI Express.If supports we
>>>>need
>>>>sample application code...
View Full Message
|
|
|
06/04/2012 7:47 AM
post93489
|
If your FPGA supports bus mastering, then all you need to do is setup the
physical address of the memory buffer in the FPGA and the FPGA will bus
master to/from this address.
--
Hugh Brown
QNX Software Systems Limited
1001 Farrar Rd.,
Ottawa. ON. K2K 0B3.
Telephone: 613-591-0931
On 12-06-04 12:17 AM, "srilakshmi" <community-noreply@qnx.com> wrote:
>Hugh Brown,
> I need help regarding when request is sending from FPGA to INTEL board
>how
>INTEL Board recognize that Request? Is their any functions and commands in
>QNX?
>
>
>Srilakshmi
>
>-----Original Message-----
>From: Hugh Brown [mailto:community-noreply@qnx.com]
>Sent: Sunday, June 03, 2012 5:21 PM
>To: general-community@community.qnx.com
>Subject: Re: PCI Express
>
>I have no idea how your FPGA works, so am unable to help you with data
>transfer.
>
>--
>Hugh Brown
>QNX Software Systems Limited
>1001 Farrar Rd.,
>Ottawa. ON. K2K 0B3.
>Telephone: 613-591-0931
>
>
>
>
>
>
>
>On 12-06-02 1:19 AM, "srilakshmi" <community-noreply@qnx.com> wrote:
>
>>We are able to detect the device and read configuration space. when we
>>are
>>sending data from Intel to FPGA board it is able to read 1 byte of data
>>only
>>that means sending only one request. But in my project I need to transfer
>>some bytes of data from Intel board to FPGA board and able to receive
>>data
>>from FPGA board to Intel board.
>>
>>-----Original Message-----
>>From: Hugh Brown [mailto:community-noreply@qnx.com]
>>Sent: Friday, June 01, 2012 6:22 PM
>>To: general-community@community.qnx.com
>>Subject: Re: PCI Express
>>
>>Here is some sample code to allow you to attach to a PCI device and read
>>the
>>configuration space. You run the program as 'pci_att 0xVendor 0xDevice'
>>where Vendor and Device are the vendor and device Ids of the device you
>>are
>>concerned about.
>>
>>--
>>Hugh Brown
>>QNX Software Systems Limited
>>1001 Farrar Rd.,
>>Ottawa. ON. K2K 0B3.
>>Telephone: 613-591-0931
>>
>>
>>
>>
>>
>>
>>
>>On 12-06-01 2:07 AM, "srilakshmi" <community-noreply@qnx.com> wrote:
>>
>>>I need sample c code for PCIe data transfer in QNX.
>>>
>>>-----Original Message-----
>>>From: Hugh Brown [mailto:community-noreply@qnx.com]
>>>Sent: Wednesday, May 30, 2012 6:38 PM
>>>To: general-community@community.qnx.com
>>>Subject: Re: PCI Express
>>>
>>>Take a look at the pci_attach* and pci_read_config() functions in the
>>>help
>>>files to see how to read configuration space and attach your application
>>>to a device.
>>>
>>>--
>>>Hugh Brown
>>>QNX Software Systems Limited
>>>1001 Farrar Rd.,
>>>Ottawa. ON. K2K 0B3.
>>>Telephone: 613-591-0931
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>On 12-05-30 8:56 AM, "srilakshmi" <community-noreply@qnx.com> wrote:
>>>
>>>>Actually in my project I need to transfer data from Intel Advantech
>>>>board
>>>>to
>>>>FPGA board through PCI Express. from FPGA board it transfers data to
>>>>different cards like card c, card D like that. Here I need to access
>>>>configuration space.
>>>>
>>>>-----Original Message-----
>>>>From: Hugh Brown [mailto:community-noreply@qnx.com]
>>>>Sent: Wednesday, May 30, 2012 6:07 PM
>>>>To:...
View Full Message
|
|
|
06/05/2012 6:56 AM
post93507
|
Hi Hugh Brown,
we are able to read 1byte of data at FPGA side. now We need to transfer
bulk of data from INTEL board to FPGA through PCI Express.
Thanks & Regards
Srilakshmi
-----Original Message-----
From: Hugh Brown [mailto:community-noreply@qnx.com]
Sent: Sunday, June 03, 2012 5:21 PM
To: general-community@community.qnx.com
Subject: Re: PCI Express
I have no idea how your FPGA works, so am unable to help you with data
transfer.
--
Hugh Brown
QNX Software Systems Limited
1001 Farrar Rd.,
Ottawa. ON. K2K 0B3.
Telephone: 613-591-0931
On 12-06-02 1:19 AM, "srilakshmi" <community-noreply@qnx.com> wrote:
>We are able to detect the device and read configuration space. when we are
>sending data from Intel to FPGA board it is able to read 1 byte of data
>only
>that means sending only one request. But in my project I need to transfer
>some bytes of data from Intel board to FPGA board and able to receive data
>from FPGA board to Intel board.
>
>-----Original Message-----
>From: Hugh Brown [mailto:community-noreply@qnx.com]
>Sent: Friday, June 01, 2012 6:22 PM
>To: general-community@community.qnx.com
>Subject: Re: PCI Express
>
>Here is some sample code to allow you to attach to a PCI device and read
>the
>configuration space. You run the program as 'pci_att 0xVendor 0xDevice'
>where Vendor and Device are the vendor and device Ids of the device you
>are
>concerned about.
>
>--
>Hugh Brown
>QNX Software Systems Limited
>1001 Farrar Rd.,
>Ottawa. ON. K2K 0B3.
>Telephone: 613-591-0931
>
>
>
>
>
>
>
>On 12-06-01 2:07 AM, "srilakshmi" <community-noreply@qnx.com> wrote:
>
>>I need sample c code for PCIe data transfer in QNX.
>>
>>-----Original Message-----
>>From: Hugh Brown [mailto:community-noreply@qnx.com]
>>Sent: Wednesday, May 30, 2012 6:38 PM
>>To: general-community@community.qnx.com
>>Subject: Re: PCI Express
>>
>>Take a look at the pci_attach* and pci_read_config() functions in the
>>help
>>files to see how to read configuration space and attach your application
>>to a device.
>>
>>--
>>Hugh Brown
>>QNX Software Systems Limited
>>1001 Farrar Rd.,
>>Ottawa. ON. K2K 0B3.
>>Telephone: 613-591-0931
>>
>>
>>
>>
>>
>>
>>
>>On 12-05-30 8:56 AM, "srilakshmi" <community-noreply@qnx.com> wrote:
>>
>>>Actually in my project I need to transfer data from Intel Advantech
>>>board
>>>to
>>>FPGA board through PCI Express. from FPGA board it transfers data to
>>>different cards like card c, card D like that. Here I need to access
>>>configuration space.
>>>
>>>-----Original Message-----
>>>From: Hugh Brown [mailto:community-noreply@qnx.com]
>>>Sent: Wednesday, May 30, 2012 6:07 PM
>>>To: general-community@community.qnx.com
>>>Subject: Re: PCI Express
>>>
>>>Please can you be a bit more specific. What device are you trying to
>>>access and what information do you need about data transfer? Are you
>>>trying to access configuration space or device I/O space?
>>>
>>>--
>>>Hugh Brown
>>>QNX Software Systems Limited
>>>1001 Farrar Rd.,
>>>Ottawa. ON. K2K 0B3.
>>>Telephone: 613-591-0931
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>On 12-05-29 5:49 AM, "sri lakshmi" <community-noreply@qnx.com> wrote:
>>>
>>>>we are using QNX 6.5.0.Is it support for PCI Express.If supports we
>>>>need
>>>>sample application code for...
View Full Message
|
|
|
06/05/2012 7:40 AM
post93512
|
As I have said before, I don't know how your FPGA works, so you will have
to contact whoever designed your FPGA.
--
Hugh Brown
QNX Software Systems Limited
1001 Farrar Rd.,
Ottawa. ON. K2K 0B3.
Telephone: 613-591-0931
On 12-06-05 6:44 AM, "srilakshmi" <community-noreply@qnx.com> wrote:
>Hi Hugh Brown,
> we are able to read 1byte of data at FPGA side. now We need to transfer
>bulk of data from INTEL board to FPGA through PCI Express.
>
>Thanks & Regards
> Srilakshmi
>
>-----Original Message-----
>From: Hugh Brown [mailto:community-noreply@qnx.com]
>Sent: Sunday, June 03, 2012 5:21 PM
>To: general-community@community.qnx.com
>Subject: Re: PCI Express
>
>I have no idea how your FPGA works, so am unable to help you with data
>transfer.
>
>--
>Hugh Brown
>QNX Software Systems Limited
>1001 Farrar Rd.,
>Ottawa. ON. K2K 0B3.
>Telephone: 613-591-0931
>
>
>
>
>
>
>
>On 12-06-02 1:19 AM, "srilakshmi" <community-noreply@qnx.com> wrote:
>
>>We are able to detect the device and read configuration space. when we
>>are
>>sending data from Intel to FPGA board it is able to read 1 byte of data
>>only
>>that means sending only one request. But in my project I need to transfer
>>some bytes of data from Intel board to FPGA board and able to receive
>>data
>>from FPGA board to Intel board.
>>
>>-----Original Message-----
>>From: Hugh Brown [mailto:community-noreply@qnx.com]
>>Sent: Friday, June 01, 2012 6:22 PM
>>To: general-community@community.qnx.com
>>Subject: Re: PCI Express
>>
>>Here is some sample code to allow you to attach to a PCI device and read
>>the
>>configuration space. You run the program as 'pci_att 0xVendor 0xDevice'
>>where Vendor and Device are the vendor and device Ids of the device you
>>are
>>concerned about.
>>
>>--
>>Hugh Brown
>>QNX Software Systems Limited
>>1001 Farrar Rd.,
>>Ottawa. ON. K2K 0B3.
>>Telephone: 613-591-0931
>>
>>
>>
>>
>>
>>
>>
>>On 12-06-01 2:07 AM, "srilakshmi" <community-noreply@qnx.com> wrote:
>>
>>>I need sample c code for PCIe data transfer in QNX.
>>>
>>>-----Original Message-----
>>>From: Hugh Brown [mailto:community-noreply@qnx.com]
>>>Sent: Wednesday, May 30, 2012 6:38 PM
>>>To: general-community@community.qnx.com
>>>Subject: Re: PCI Express
>>>
>>>Take a look at the pci_attach* and pci_read_config() functions in the
>>>help
>>>files to see how to read configuration space and attach your application
>>>to a device.
>>>
>>>--
>>>Hugh Brown
>>>QNX Software Systems Limited
>>>1001 Farrar Rd.,
>>>Ottawa. ON. K2K 0B3.
>>>Telephone: 613-591-0931
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>On 12-05-30 8:56 AM, "srilakshmi" <community-noreply@qnx.com> wrote:
>>>
>>>>Actually in my project I need to transfer data from Intel Advantech
>>>>board
>>>>to
>>>>FPGA board through PCI Express. from FPGA board it transfers data to
>>>>different cards like card c, card D like that. Here I need to access
>>>>configuration space.
>>>>
>>>>-----Original Message-----
>>>>From: Hugh Brown [mailto:community-noreply@qnx.com]
>>>>Sent: Wednesday, May 30, 2012 6:07 PM
>>>>To: general-community@community.qnx.com
>>>>Subject: Re: PCI...
View Full Message
|
|
|
06/14/2012 2:25 AM
post93651
|
We are able to transfer TLP with 1byte of data for Memory write transaction.
You please help me to send more bytes of data through PCI express from Intel
to FPGA.
Thanks & Regards
Srilakshmi
-----Original Message-----
From: Hugh Brown [mailto:community-noreply@qnx.com]
Sent: Tuesday, June 05, 2012 5:06 PM
To: general-community@community.qnx.com
Subject: Re: PCI Express
As I have said before, I don't know how your FPGA works, so you will have
to contact whoever designed your FPGA.
--
Hugh Brown
QNX Software Systems Limited
1001 Farrar Rd.,
Ottawa. ON. K2K 0B3.
Telephone: 613-591-0931
On 12-06-05 6:44 AM, "srilakshmi" <community-noreply@qnx.com> wrote:
>Hi Hugh Brown,
> we are able to read 1byte of data at FPGA side. now We need to transfer
>bulk of data from INTEL board to FPGA through PCI Express.
>
>Thanks & Regards
> Srilakshmi
>
>-----Original Message-----
>From: Hugh Brown [mailto:community-noreply@qnx.com]
>Sent: Sunday, June 03, 2012 5:21 PM
>To: general-community@community.qnx.com
>Subject: Re: PCI Express
>
>I have no idea how your FPGA works, so am unable to help you with data
>transfer.
>
>--
>Hugh Brown
>QNX Software Systems Limited
>1001 Farrar Rd.,
>Ottawa. ON. K2K 0B3.
>Telephone: 613-591-0931
>
>
>
>
>
>
>
>On 12-06-02 1:19 AM, "srilakshmi" <community-noreply@qnx.com> wrote:
>
>>We are able to detect the device and read configuration space. when we
>>are
>>sending data from Intel to FPGA board it is able to read 1 byte of data
>>only
>>that means sending only one request. But in my project I need to transfer
>>some bytes of data from Intel board to FPGA board and able to receive
>>data
>>from FPGA board to Intel board.
>>
>>-----Original Message-----
>>From: Hugh Brown [mailto:community-noreply@qnx.com]
>>Sent: Friday, June 01, 2012 6:22 PM
>>To: general-community@community.qnx.com
>>Subject: Re: PCI Express
>>
>>Here is some sample code to allow you to attach to a PCI device and read
>>the
>>configuration space. You run the program as 'pci_att 0xVendor 0xDevice'
>>where Vendor and Device are the vendor and device Ids of the device you
>>are
>>concerned about.
>>
>>--
>>Hugh Brown
>>QNX Software Systems Limited
>>1001 Farrar Rd.,
>>Ottawa. ON. K2K 0B3.
>>Telephone: 613-591-0931
>>
>>
>>
>>
>>
>>
>>
>>On 12-06-01 2:07 AM, "srilakshmi" <community-noreply@qnx.com> wrote:
>>
>>>I need sample c code for PCIe data transfer in QNX.
>>>
>>>-----Original Message-----
>>>From: Hugh Brown [mailto:community-noreply@qnx.com]
>>>Sent: Wednesday, May 30, 2012 6:38 PM
>>>To: general-community@community.qnx.com
>>>Subject: Re: PCI Express
>>>
>>>Take a look at the pci_attach* and pci_read_config() functions in the
>>>help
>>>files to see how to read configuration space and attach your application
>>>to a device.
>>>
>>>--
>>>Hugh Brown
>>>QNX Software Systems Limited
>>>1001 Farrar Rd.,
>>>Ottawa. ON. K2K 0B3.
>>>Telephone: 613-591-0931
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>On 12-05-30 8:56 AM, "srilakshmi" <community-noreply@qnx.com> wrote:
>>>
>>>>Actually in my project I need to transfer data from Intel Advantech
>>>>board
>>>>to
>>>>FPGA board through PCI Express. from FPGA board it transfers data to
>>>>different cards like card c, card D like...
View Full Message
|
|
|
06/14/2012 9:28 AM
post93662
|
How can we help you when we don't even know how your FPGA works?
--
Hugh Brown
QNX Software Systems Limited
1001 Farrar Rd.,
Ottawa. ON. K2K 0B3.
Telephone: 613-591-0931
On 12-06-14 2:13 AM, "srilakshmi" <community-noreply@qnx.com> wrote:
>We are able to transfer TLP with 1byte of data for Memory write
>transaction.
>You please help me to send more bytes of data through PCI express from
>Intel
>to FPGA.
>
>Thanks & Regards
> Srilakshmi
>
>-----Original Message-----
>From: Hugh Brown [mailto:community-noreply@qnx.com]
>Sent: Tuesday, June 05, 2012 5:06 PM
>To: general-community@community.qnx.com
>Subject: Re: PCI Express
>
>As I have said before, I don't know how your FPGA works, so you will have
>to contact whoever designed your FPGA.
>
>--
>Hugh Brown
>QNX Software Systems Limited
>1001 Farrar Rd.,
>Ottawa. ON. K2K 0B3.
>Telephone: 613-591-0931
>
>
>
>
>
>
>
>On 12-06-05 6:44 AM, "srilakshmi" <community-noreply@qnx.com> wrote:
>
>>Hi Hugh Brown,
>> we are able to read 1byte of data at FPGA side. now We need to transfer
>>bulk of data from INTEL board to FPGA through PCI Express.
>>
>>Thanks & Regards
>> Srilakshmi
>>
>>-----Original Message-----
>>From: Hugh Brown [mailto:community-noreply@qnx.com]
>>Sent: Sunday, June 03, 2012 5:21 PM
>>To: general-community@community.qnx.com
>>Subject: Re: PCI Express
>>
>>I have no idea how your FPGA works, so am unable to help you with data
>>transfer.
>>
>>--
>>Hugh Brown
>>QNX Software Systems Limited
>>1001 Farrar Rd.,
>>Ottawa. ON. K2K 0B3.
>>Telephone: 613-591-0931
>>
>>
>>
>>
>>
>>
>>
>>On 12-06-02 1:19 AM, "srilakshmi" <community-noreply@qnx.com> wrote:
>>
>>>We are able to detect the device and read configuration space. when we
>>>are
>>>sending data from Intel to FPGA board it is able to read 1 byte of data
>>>only
>>>that means sending only one request. But in my project I need to
>>>transfer
>>>some bytes of data from Intel board to FPGA board and able to receive
>>>data
>>>from FPGA board to Intel board.
>>>
>>>-----Original Message-----
>>>From: Hugh Brown [mailto:community-noreply@qnx.com]
>>>Sent: Friday, June 01, 2012 6:22 PM
>>>To: general-community@community.qnx.com
>>>Subject: Re: PCI Express
>>>
>>>Here is some sample code to allow you to attach to a PCI device and read
>>>the
>>>configuration space. You run the program as 'pci_att 0xVendor 0xDevice'
>>>where Vendor and Device are the vendor and device Ids of the device you
>>>are
>>>concerned about.
>>>
>>>--
>>>Hugh Brown
>>>QNX Software Systems Limited
>>>1001 Farrar Rd.,
>>>Ottawa. ON. K2K 0B3.
>>>Telephone: 613-591-0931
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>On 12-06-01 2:07 AM, "srilakshmi" <community-noreply@qnx.com> wrote:
>>>
>>>>I need sample c code for PCIe data transfer in QNX.
>>>>
>>>>-----Original Message-----
>>>>From: Hugh Brown [mailto:community-noreply@qnx.com]
>>>>Sent: Wednesday, May 30, 2012 6:38 PM
>>>>To: general-community@community.qnx.com
>>>>Subject: Re: PCI Express
>>>>
>>>>Take a look at the pci_attach* and pci_read_config() functions in the
>>>>help
>>>>files to see how to read...
View Full Message
|
|
|
06/18/2012 6:53 AM
post93718
|
Hi,
I need to send 4kbytes of data with single packet. On FPGA side we checking
packets and data length through Chip scope. Now we are able to send 1byte of
data with each packet.
To send 4k bytes of data with one packet I need to know DMA transaction for
pci in QNX.
Please provide me any document regarding this.
Thanks & Regards
Srilakshmi
-----Original Message-----
From: Hugh Brown [mailto:community-noreply@qnx.com]
Sent: Thursday, June 14, 2012 6:45 PM
To: general-community@community.qnx.com
Subject: Re: PCI Express
How can we help you when we don't even know how your FPGA works?
--
Hugh Brown
QNX Software Systems Limited
1001 Farrar Rd.,
Ottawa. ON. K2K 0B3.
Telephone: 613-591-0931
On 12-06-14 2:13 AM, "srilakshmi" <community-noreply@qnx.com> wrote:
>We are able to transfer TLP with 1byte of data for Memory write
>transaction.
>You please help me to send more bytes of data through PCI express from
>Intel
>to FPGA.
>
>Thanks & Regards
> Srilakshmi
>
>-----Original Message-----
>From: Hugh Brown [mailto:community-noreply@qnx.com]
>Sent: Tuesday, June 05, 2012 5:06 PM
>To: general-community@community.qnx.com
>Subject: Re: PCI Express
>
>As I have said before, I don't know how your FPGA works, so you will have
>to contact whoever designed your FPGA.
>
>--
>Hugh Brown
>QNX Software Systems Limited
>1001 Farrar Rd.,
>Ottawa. ON. K2K 0B3.
>Telephone: 613-591-0931
>
>
>
>
>
>
>
>On 12-06-05 6:44 AM, "srilakshmi" <community-noreply@qnx.com> wrote:
>
>>Hi Hugh Brown,
>> we are able to read 1byte of data at FPGA side. now We need to transfer
>>bulk of data from INTEL board to FPGA through PCI Express.
>>
>>Thanks & Regards
>> Srilakshmi
>>
>>-----Original Message-----
>>From: Hugh Brown [mailto:community-noreply@qnx.com]
>>Sent: Sunday, June 03, 2012 5:21 PM
>>To: general-community@community.qnx.com
>>Subject: Re: PCI Express
>>
>>I have no idea how your FPGA works, so am unable to help you with data
>>transfer.
>>
>>--
>>Hugh Brown
>>QNX Software Systems Limited
>>1001 Farrar Rd.,
>>Ottawa. ON. K2K 0B3.
>>Telephone: 613-591-0931
>>
>>
>>
>>
>>
>>
>>
>>On 12-06-02 1:19 AM, "srilakshmi" <community-noreply@qnx.com> wrote:
>>
>>>We are able to detect the device and read configuration space. when we
>>>are
>>>sending data from Intel to FPGA board it is able to read 1 byte of data
>>>only
>>>that means sending only one request. But in my project I need to
>>>transfer
>>>some bytes of data from Intel board to FPGA board and able to receive
>>>data
>>>from FPGA board to Intel board.
>>>
>>>-----Original Message-----
>>>From: Hugh Brown [mailto:community-noreply@qnx.com]
>>>Sent: Friday, June 01, 2012 6:22 PM
>>>To: general-community@community.qnx.com
>>>Subject: Re: PCI Express
>>>
>>>Here is some sample code to allow you to attach to a PCI device and read
>>>the
>>>configuration space. You run the program as 'pci_att 0xVendor 0xDevice'
>>>where Vendor and Device are the vendor and device Ids of the device you
>>>are
>>>concerned about.
>>>
>>>--
>>>Hugh Brown
>>>QNX Software Systems Limited
>>>1001 Farrar Rd.,
>>>Ottawa. ON. K2K 0B3.
>>>Telephone: 613-591-0931
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>On 12-06-01 2:07 AM, "srilakshmi" <community-noreply@qnx.com>...
View Full Message
|
|
|
06/18/2012 7:51 AM
post93722
|
Srilakshmi,
is the PCIexpress interface realized as a core of the FPGA ?
If yes, do you have the VHDL code of that core?
Or is the PCI interface based on one of these standard chips ? (PLX xxx
a.s.o)
Could you post the output of "pci -vvv" ?
What is the functionalty of your board ?
--Armin
http://www.steinhoff-automation.com
srilakshmi wrote:
> Hi,
> I need to send 4kbytes of data with single packet. On FPGA side we checking
> packets and data length through Chip scope. Now we are able to send 1byte of
> data with each packet.
> To send 4k bytes of data with one packet I need to know DMA transaction for
> pci in QNX.
> Please provide me any document regarding this.
>
> Thanks& Regards
> Srilakshmi
>
> -----Original Message-----
> From: Hugh Brown [mailto:community-noreply@qnx.com]
> Sent: Thursday, June 14, 2012 6:45 PM
> To: general-community@community.qnx.com
> Subject: Re: PCI Express
>
> How can we help you when we don't even know how your FPGA works?
>
|
|
|
06/19/2012 4:48 AM
post93750
|
Hi Hugh Brown,
I don't know FPGA side work. Another person is doing that part.
When I am executing PCI code on QNX RTOS they checking at FPGA chip scope
how many packets they are getting and each packet carrying how much of data
all those things they are checking. Is their any document regarding this
please send me.
Thanks & Regards
Srilakshmi
-----Original Message-----
From: Hugh Brown [mailto:community-noreply@qnx.com]
Sent: Thursday, June 14, 2012 6:45 PM
To: general-community@community.qnx.com
Subject: Re: PCI Express
How can we help you when we don't even know how your FPGA works?
--
Hugh Brown
QNX Software Systems Limited
1001 Farrar Rd.,
Ottawa. ON. K2K 0B3.
Telephone: 613-591-0931
On 12-06-14 2:13 AM, "srilakshmi" <community-noreply@qnx.com> wrote:
>We are able to transfer TLP with 1byte of data for Memory write
>transaction.
>You please help me to send more bytes of data through PCI express from
>Intel
>to FPGA.
>
>Thanks & Regards
> Srilakshmi
>
>-----Original Message-----
>From: Hugh Brown [mailto:community-noreply@qnx.com]
>Sent: Tuesday, June 05, 2012 5:06 PM
>To: general-community@community.qnx.com
>Subject: Re: PCI Express
>
>As I have said before, I don't know how your FPGA works, so you will have
>to contact whoever designed your FPGA.
>
>--
>Hugh Brown
>QNX Software Systems Limited
>1001 Farrar Rd.,
>Ottawa. ON. K2K 0B3.
>Telephone: 613-591-0931
>
>
>
>
>
>
>
>On 12-06-05 6:44 AM, "srilakshmi" <community-noreply@qnx.com> wrote:
>
>>Hi Hugh Brown,
>> we are able to read 1byte of data at FPGA side. now We need to transfer
>>bulk of data from INTEL board to FPGA through PCI Express.
>>
>>Thanks & Regards
>> Srilakshmi
>>
>>-----Original Message-----
>>From: Hugh Brown [mailto:community-noreply@qnx.com]
>>Sent: Sunday, June 03, 2012 5:21 PM
>>To: general-community@community.qnx.com
>>Subject: Re: PCI Express
>>
>>I have no idea how your FPGA works, so am unable to help you with data
>>transfer.
>>
>>--
>>Hugh Brown
>>QNX Software Systems Limited
>>1001 Farrar Rd.,
>>Ottawa. ON. K2K 0B3.
>>Telephone: 613-591-0931
>>
>>
>>
>>
>>
>>
>>
>>On 12-06-02 1:19 AM, "srilakshmi" <community-noreply@qnx.com> wrote:
>>
>>>We are able to detect the device and read configuration space. when we
>>>are
>>>sending data from Intel to FPGA board it is able to read 1 byte of data
>>>only
>>>that means sending only one request. But in my project I need to
>>>transfer
>>>some bytes of data from Intel board to FPGA board and able to receive
>>>data
>>>from FPGA board to Intel board.
>>>
>>>-----Original Message-----
>>>From: Hugh Brown [mailto:community-noreply@qnx.com]
>>>Sent: Friday, June 01, 2012 6:22 PM
>>>To: general-community@community.qnx.com
>>>Subject: Re: PCI Express
>>>
>>>Here is some sample code to allow you to attach to a PCI device and read
>>>the
>>>configuration space. You run the program as 'pci_att 0xVendor 0xDevice'
>>>where Vendor and Device are the vendor and device Ids of the device you
>>>are
>>>concerned about.
>>>
>>>--
>>>Hugh Brown
>>>QNX Software Systems Limited
>>>1001 Farrar Rd.,
>>>Ottawa. ON. K2K 0B3.
>>>Telephone: 613-591-0931
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>On 12-06-01 2:07 AM, "srilakshmi" <community-noreply@qnx.com>...
View Full Message
|
|
|
06/19/2012 5:41 AM
post93751
|
srilakshmi wrote:
> Hi Hugh Brown,
> I don't know FPGA side work. Another person is doing that part.
> When I am executing PCI code on QNX RTOS they checking at FPGA chip scope
> how many packets they are getting and each packet carrying how much of data
> all those things they are checking.
These data are related to the bus traffic of the PCI-E bus. It has
nothing to do with QNX.
The PCI-E core of the FPGA seems not working correctly ...
> Is their any document regarding this
> please send me.
Please read the PCI-E standard
--Armin
|
|
|
06/19/2012 7:54 AM
post93757
|
No, there is no document explaining this. The only QNX documentation is
for the pci* functions. You will have to contact the FPGA designer to
rectify this problem.
--
Hugh Brown
QNX Software Systems Limited
1001 Farrar Rd.,
Ottawa. ON. K2K 0B3.
Telephone: 613-591-0931
On 12-06-19 4:47 AM, "srilakshmi" <community-noreply@qnx.com> wrote:
>Hi Hugh Brown,
> I don't know FPGA side work. Another person is doing that part.
>When I am executing PCI code on QNX RTOS they checking at FPGA chip scope
>how many packets they are getting and each packet carrying how much of
>data
>all those things they are checking. Is their any document regarding this
>please send me.
>
>Thanks & Regards
> Srilakshmi
>-----Original Message-----
>From: Hugh Brown [mailto:community-noreply@qnx.com]
>Sent: Thursday, June 14, 2012 6:45 PM
>To: general-community@community.qnx.com
>Subject: Re: PCI Express
>
>How can we help you when we don't even know how your FPGA works?
>
>--
>Hugh Brown
>QNX Software Systems Limited
>1001 Farrar Rd.,
>Ottawa. ON. K2K 0B3.
>Telephone: 613-591-0931
>
>
>
>
>
>
>
>On 12-06-14 2:13 AM, "srilakshmi" <community-noreply@qnx.com> wrote:
>
>>We are able to transfer TLP with 1byte of data for Memory write
>>transaction.
>>You please help me to send more bytes of data through PCI express from
>>Intel
>>to FPGA.
>>
>>Thanks & Regards
>> Srilakshmi
>>
>>-----Original Message-----
>>From: Hugh Brown [mailto:community-noreply@qnx.com]
>>Sent: Tuesday, June 05, 2012 5:06 PM
>>To: general-community@community.qnx.com
>>Subject: Re: PCI Express
>>
>>As I have said before, I don't know how your FPGA works, so you will have
>>to contact whoever designed your FPGA.
>>
>>--
>>Hugh Brown
>>QNX Software Systems Limited
>>1001 Farrar Rd.,
>>Ottawa. ON. K2K 0B3.
>>Telephone: 613-591-0931
>>
>>
>>
>>
>>
>>
>>
>>On 12-06-05 6:44 AM, "srilakshmi" <community-noreply@qnx.com> wrote:
>>
>>>Hi Hugh Brown,
>>> we are able to read 1byte of data at FPGA side. now We need to
>>>transfer
>>>bulk of data from INTEL board to FPGA through PCI Express.
>>>
>>>Thanks & Regards
>>> Srilakshmi
>>>
>>>-----Original Message-----
>>>From: Hugh Brown [mailto:community-noreply@qnx.com]
>>>Sent: Sunday, June 03, 2012 5:21 PM
>>>To: general-community@community.qnx.com
>>>Subject: Re: PCI Express
>>>
>>>I have no idea how your FPGA works, so am unable to help you with data
>>>transfer.
>>>
>>>--
>>>Hugh Brown
>>>QNX Software Systems Limited
>>>1001 Farrar Rd.,
>>>Ottawa. ON. K2K 0B3.
>>>Telephone: 613-591-0931
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>On 12-06-02 1:19 AM, "srilakshmi" <community-noreply@qnx.com> wrote:
>>>
>>>>We are able to detect the device and read configuration space. when we
>>>>are
>>>>sending data from Intel to FPGA board it is able to read 1 byte of data
>>>>only
>>>>that means sending only one request. But in my project I need to
>>>>transfer
>>>>some bytes of data from Intel board to FPGA board and able to receive
>>>>data
>>>>from FPGA board to Intel board.
>>>>
>>>>-----Original Message-----
>>>>From: Hugh Brown [mailto:community-noreply@qnx.com]
>>>>Sent: Friday,...
View Full Message
|
|
|
06/20/2012 8:04 AM
post93782
|
How to recognize interrupts coming from FPGA through PCI? Please provide me
document or code regarding this.
--
Srilakshmi
-----Original Message-----
From: Hugh Brown [mailto:community-noreply@qnx.com]
Sent: Tuesday, June 19, 2012 5:23 PM
To: general-community@community.qnx.com
Subject: Re: PCI Express
No, there is no document explaining this. The only QNX documentation is
for the pci* functions. You will have to contact the FPGA designer to
rectify this problem.
--
Hugh Brown
QNX Software Systems Limited
1001 Farrar Rd.,
Ottawa. ON. K2K 0B3.
Telephone: 613-591-0931
On 12-06-19 4:47 AM, "srilakshmi" <community-noreply@qnx.com> wrote:
>Hi Hugh Brown,
> I don't know FPGA side work. Another person is doing that part.
>When I am executing PCI code on QNX RTOS they checking at FPGA chip scope
>how many packets they are getting and each packet carrying how much of
>data
>all those things they are checking. Is their any document regarding this
>please send me.
>
>Thanks & Regards
> Srilakshmi
>-----Original Message-----
>From: Hugh Brown [mailto:community-noreply@qnx.com]
>Sent: Thursday, June 14, 2012 6:45 PM
>To: general-community@community.qnx.com
>Subject: Re: PCI Express
>
>How can we help you when we don't even know how your FPGA works?
>
>--
>Hugh Brown
>QNX Software Systems Limited
>1001 Farrar Rd.,
>Ottawa. ON. K2K 0B3.
>Telephone: 613-591-0931
>
>
>
>
>
>
>
>On 12-06-14 2:13 AM, "srilakshmi" <community-noreply@qnx.com> wrote:
>
>>We are able to transfer TLP with 1byte of data for Memory write
>>transaction.
>>You please help me to send more bytes of data through PCI express from
>>Intel
>>to FPGA.
>>
>>Thanks & Regards
>> Srilakshmi
>>
>>-----Original Message-----
>>From: Hugh Brown [mailto:community-noreply@qnx.com]
>>Sent: Tuesday, June 05, 2012 5:06 PM
>>To: general-community@community.qnx.com
>>Subject: Re: PCI Express
>>
>>As I have said before, I don't know how your FPGA works, so you will have
>>to contact whoever designed your FPGA.
>>
>>--
>>Hugh Brown
>>QNX Software Systems Limited
>>1001 Farrar Rd.,
>>Ottawa. ON. K2K 0B3.
>>Telephone: 613-591-0931
>>
>>
>>
>>
>>
>>
>>
>>On 12-06-05 6:44 AM, "srilakshmi" <community-noreply@qnx.com> wrote:
>>
>>>Hi Hugh Brown,
>>> we are able to read 1byte of data at FPGA side. now We need to
>>>transfer
>>>bulk of data from INTEL board to FPGA through PCI Express.
>>>
>>>Thanks & Regards
>>> Srilakshmi
>>>
>>>-----Original Message-----
>>>From: Hugh Brown [mailto:community-noreply@qnx.com]
>>>Sent: Sunday, June 03, 2012 5:21 PM
>>>To: general-community@community.qnx.com
>>>Subject: Re: PCI Express
>>>
>>>I have no idea how your FPGA works, so am unable to help you with data
>>>transfer.
>>>
>>>--
>>>Hugh Brown
>>>QNX Software Systems Limited
>>>1001 Farrar Rd.,
>>>Ottawa. ON. K2K 0B3.
>>>Telephone: 613-591-0931
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>On 12-06-02 1:19 AM, "srilakshmi" <community-noreply@qnx.com> wrote:
>>>
>>>>We are able to detect the device and read configuration space. when we
>>>>are
>>>>sending data from Intel to FPGA board it is able to read 1 byte of data
>>>>only
>>>>that means sending only one request. But in my project I need...
View Full Message
|
|
|
06/20/2012 1:35 PM
post93787
|
Has allready been done by Hugh ... see the attachment !!
--Armin
srilakshmi wrote:
> How to recognize interrupts coming from FPGA through PCI? Please provide me
> document or code regarding this.
>
|
|
|
06/20/2012 2:47 PM
post93788
|
srilakshmi wrote:
> How to recognize interrupts coming from FPGA through PCI?
is this a board with a PCI interface together with separate FPGA chip??
Or is the PCI interface realized as a core of the FPGA?
Could you post the output of "pci -vvv" ?
> Please provide me
> document or code regarding this.
>
|
|
|
06/21/2012 1:34 AM
post93792
|
Through the attached file I am sending the output of pci -vvv.
My project board contains both Intel chip and FPGA chip on same board.
through PCI express slot we are connecting Xilinx board. Through PCIe we are
communicating with each other. And the result is checking at FPGA side by
Chipscope software.
And the previous which you have sent to me is not working because
pci_dev_info predefined structure doesn't contain members like HeaderType,
CpuBmstrTranslation, CpuIsaTranslation, CpuMemTranslation, NumIrq,
info.MsiDefs[i].count
Srilakshmi
-----Original Message-----
From: Armin Steinhoff [mailto:community-noreply@qnx.com]
Sent: Wednesday, June 20, 2012 11:59 PM
To: general-community@community.qnx.com
Cc: srilakshmi; srilakshmi
Subject: Re: PCI Express
srilakshmi wrote:
> How to recognize interrupts coming from FPGA through PCI?
is this a board with a PCI interface together with separate FPGA chip??
Or is the PCI interface realized as a core of the FPGA?
Could you post the output of "pci -vvv" ?
> Please provide me
> document or code regarding this.
>
_______________________________________________
General
http://community.qnx.com/sf/go/post93788
To cancel your subscription to this discussion, please e-mail
general-community-unsubscribe@community.qnx.com
-----
No virus found in this message.
Checked by AVG - www.avg.com
Version: 2012.0.2177 / Virus Database: 2437/5081 - Release Date: 06/20/12
|
|
|
06/21/2012 4:37 AM
post93794
|
srilakshmi wrote:
> Through the attached file I am sending the output of pci -vvv.
> My project board contains both Intel chip and FPGA chip on same board.
> through PCI express slot we are connecting Xilinx board. Through PCIe we are
> communicating with each other. And the result is checking at FPGA side by
> Chipscope software.
Ok ... and this is a board from Xilinx with the vendor ID 10EEh ??
This board seems to be completely disabled ...
No I/O memory, no memory, no connection to an interrupt line.
Also the memory of 128 bytes referenced by BAR[0] is disabled !
Please see the marks at the printouts of the "pci" command:
Vendor ID = 10eeh, Xilinx Corporation
Device ID = 7h, Unknown Unknown
PCI index = 0h
Class Codes = 050000h
Revision ID = 0h
Bus number = 2
Device number = 0
Function num = 0
Status Reg = 10h
Command Reg = 0h
I/O space access *disabled* <<<============ !!!
Memory space access *disabled* <<<============ !!!
Bus Master disabled
Special Cycle operations ignored
Memory Write and Invalidate *disabled* <<<============ !!!
Palette Snooping disabled
Parity Error Response disabled
Data/Address stepping disabled
SERR# driver disabled
Fast back-to-back transactions to different agents disabled
PCI INTx enabled
Header type = 0h Single-function
BIST = 0h Build-in-self-test not supported
Latency Timer = 0h
Cache Line Size= 0h
BAR - 0 [Mem] = 0h 32bit length 128 *disabled* <<<========= !!!
Subsystem Vendor ID = 10eeh
Subsystem ID = 7h
Max Lat = 0ns
Min Gnt = 0ns
PCI Int Pin = INT A
Interrupt line = *no connection* <<<========== !!!
> And the previous which you have sent to me is not working because
> pci_dev_info predefined structure doesn't contain members like HeaderType,
> CpuBmstrTranslation, CpuIsaTranslation, CpuMemTranslation, NumIrq,
> info.MsiDefs[i].count
The example code previously posted by Hugh Brown is for QNX 6.5.
Are you working with QNX 6.4.x ??
Best Regards
--Armin
http://www.steinhoff-automation.com
>
>
>
> Srilakshmi
>
>
> -----Original Message-----
> From: Armin Steinhoff [mailto:community-noreply@qnx.com]
> Sent: Wednesday, June 20, 2012 11:59 PM
> To: general-community@community.qnx.com
> Cc: srilakshmi; srilakshmi
> Subject: Re: PCI Express
>
> srilakshmi wrote:
>> How to recognize interrupts coming from FPGA through PCI?
> is this a board with a PCI interface together with separate FPGA chip??
> Or is the PCI interface realized as a core of the FPGA?
>
> Could you post the output of "pci -vvv" ?
>
>
>> Please provide me
>> document or code regarding this.
>>
>
>
>
>
> _______________________________________________
>
> General
> http://community.qnx.com/sf/go/post93788
> To cancel your subscription to this discussion, please e-mail
> general-community-unsubscribe@community.qnx.com
>
> -----
> No virus found in this message.
> Checked by AVG - www.avg.com
> Version: 2012.0.2177 / Virus Database: 2437/5081 - Release Date: 06/20/12
>
>
>
>
> _______________________________________________
>
> General
> http://community.qnx.com/sf/go/post93792
> To cancel your subscription to this discussion, please e-mail general-community-unsubscribe@community.qnx.com
|
|
|
06/21/2012 5:55 AM
post93798
|
I am working with QNX 6.5.0.But in Regarding APIs for pci_dev_info
predefined structure doesn't contains members like HeaderType,
CpuBmstrTranslation, CpuIsaTranslation, CpuMemTranslation, NumIrq,
info.MsiDefs[i].count.
That code is not working for interrupts.
Please provide me document or code.
I need to activate interrupts (recognize interrupts coming from FPGA )
Srilakshmi
From: Armin Steinhoff [mailto:community-noreply@qnx.com]
Sent: Thursday, June 21, 2012 2:08 PM
To: general-community@community.qnx.com
Cc: srilakshmi; srilakshmi
Subject: Re: PCI Express
srilakshmi wrote:
Through the attached file I am sending the output of pci -vvv.
My project board contains both Intel chip and FPGA chip on same board.
through PCI express slot we are connecting Xilinx board. Through PCIe we are
communicating with each other. And the result is checking at FPGA side by
Chipscope software.
Ok ... and this is a board from Xilinx with the vendor ID 10EEh ??
This board seems to be completely disabled ...
No I/O memory, no memory, no connection to an interrupt line.
Also the memory of 128 bytes referenced by BAR[0] is disabled !
Please see the marks at the printouts of the "pci" command:
Vendor ID = 10eeh, Xilinx Corporation
Device ID = 7h, Unknown Unknown
PCI index = 0h
Class Codes = 050000h
Revision ID = 0h
Bus number = 2
Device number = 0
Function num = 0
Status Reg = 10h
Command Reg = 0h
I/O space access disabled <<<============ !!!
Memory space access disabled <<<============ !!!
Bus Master disabled
Special Cycle operations ignored
Memory Write and Invalidate disabled <<<============ !!!
Palette Snooping disabled
Parity Error Response disabled
Data/Address stepping disabled
SERR# driver disabled
Fast back-to-back transactions to different agents disabled
PCI INTx enabled
Header type = 0h Single-function
BIST = 0h Build-in-self-test not supported
Latency Timer = 0h
Cache Line Size= 0h
BAR - 0 [Mem] = 0h 32bit length 128 disabled <<<========= !!!
Subsystem Vendor ID = 10eeh
Subsystem ID = 7h
Max Lat = 0ns
Min Gnt = 0ns
PCI Int Pin = INT A
Interrupt line = no connection <<<========== !!!
And the previous which you have sent to me is not working because
pci_dev_info predefined structure doesn't contain members like HeaderType,
CpuBmstrTranslation, CpuIsaTranslation, CpuMemTranslation, NumIrq,
info.MsiDefs[i].count
The example code previously posted by Hugh Brown is for QNX 6.5.
Are you working with QNX 6.4.x ??
Best Regards
--Armin
http://www.steinhoff-automation.com
Srilakshmi
-----Original Message-----
From: Armin Steinhoff [mailto:community-noreply@qnx.com]
Sent: Wednesday, June 20, 2012 11:59 PM
To: general-community@community.qnx.com
Cc: srilakshmi; srilakshmi
Subject: Re: PCI Express
srilakshmi wrote:
How to recognize interrupts coming from FPGA through PCI?
is this a board with a PCI interface together with separate FPGA chip??
Or is the PCI interface realized as a core of the FPGA?
Could you post the output of "pci -vvv" ?
Please provide me
document or code regarding this.
_______________________________________________
General
http://community.qnx.com/sf/go/post93788
To cancel your subscription to this discussion, please e-mail
general-community-unsubscribe@community.qnx.com
-----
No virus found in this message.
Checked by AVG - www.avg.com
Version: 2012.0.2177 / Virus Database: 2437/5081 - Release Date: 06/20/12
_______________________________________________
General
http://community.qnx.com/sf/go/post93792
To cancel your subscription to this discussion, please...
View Full Message
|
|
|
06/21/2012 7:06 AM
post93802
|
srilakshmi wrote:
>
> I am working with QNX 6.5.0.But in Regarding APIs for pci_dev_info
> predefined structure doesn't contains members like HeaderType,
>
remove the code refrencing HeaderType ... it seems not to be a member
of the "released" version of pci_dev_info!
Also remove USE_MSI and USE_MSIX from pci_attach_device ...
> CpuBmstrTranslation, CpuIsaTranslation, CpuMemTranslation,
>
pci_dev_info contains these members
> NumIrq,
>
NumIrq is Irq ...
> info.MsiDefs[i].count...
>
remove any references to MsiDefs ... ... seems not to be a member of the
"released" version of pci_dev_info.
> That code is not working for interrupts.
>
That code does absolutely nothing with the interrupt.
Have a look to the call InterrupAttach a.s.o
--Armin
> Please provide me document or code.
>
> I need to activate interrupts (recognize interrupts coming from FPGA )
>
> Srilakshmi
>
> *From:*Armin Steinhoff [mailto:community-noreply@qnx.com]
> *Sent:* Thursday, June 21, 2012 2:08 PM
> *To:* general-community@community.qnx.com
> *Cc:* srilakshmi; srilakshmi
> *Subject:* Re: PCI Express
>
> srilakshmi wrote:
>
> Through the attached file I am sending the output of pci -vvv.
> My project board contains both Intel chip and FPGA chip on same board.
> through PCI express slot we are connecting Xilinx board. Through PCIe we are
> communicating with each other. And the result is checking at FPGA side by
> Chipscope software.
>
>
> Ok ... and this is a board from Xilinx with the vendor ID 10EEh ??
>
> This board seems to be completely disabled ...
> No I/O memory, no memory, no connection to an interrupt line.
> Also the memory of 128 bytes referenced by BAR[0] is disabled !
>
> Please see the marks at the printouts of the "pci" command:
>
> Vendor ID = 10eeh, Xilinx Corporation
> Device ID = 7h, Unknown Unknown
> PCI index = 0h
> Class Codes = 050000h
> Revision ID = 0h
> Bus number = 2
> Device number = 0
> Function num = 0
> Status Reg = 10h
> Command Reg = 0h
> I/O space access *disabled* <<<============ !!!
> Memory space access *disabled* <<<============ !!!
> Bus Master disabled
> Special Cycle operations ignored
> Memory Write and Invalidate *disabled* <<<============ !!!
> Palette Snooping disabled
> Parity Error Response disabled
> Data/Address stepping disabled
> SERR# driver disabled
> Fast back-to-back transactions to different agents disabled
> PCI INTx enabled
> Header type = 0h Single-function
> BIST = 0h Build-in-self-test not supported
> Latency Timer = 0h
> Cache Line Size= 0h
> BAR - 0 [Mem] = 0h 32bit length 128 *disabled* <<<========= !!!
> Subsystem Vendor ID = 10eeh
> Subsystem ID = 7h
> Max Lat = 0ns
> Min Gnt = 0ns
> PCI Int Pin = INT A
> Interrupt line = *no connection* <<<========== !!!
>
>
>
>
> And the previous which you have sent to me is not working because
> pci_dev_info predefined structure doesn't contain members like HeaderType,
> CpuBmstrTranslation, CpuIsaTranslation, CpuMemTranslation, NumIrq,
> info.MsiDefs[i].count
>
>
> The example code previously posted by Hugh Brown is for QNX 6.5.
> Are you working with QNX 6.4.x ??
>
> Best Regards
>
> --Armin
>
> http://www.steinhoff-automation.com
>
>
>
>
>
> Srilakshmi
>
>
> -----Original Message-----
> From: Armin Steinhoff [mailto:community-noreply@qnx.com]
> Sent: Wednesday, June 20, 2012 11:59 PM
> To:general-community@community.qnx.com ...
View Full Message
|
|
|
06/21/2012 6:43 AM
post93799
|
How to enable the interrupt line?
Please provide me sample code or document or explanaion
From: Armin Steinhoff [mailto:community-noreply@qnx.com]
Sent: Thursday, June 21, 2012 2:08 PM
To: general-community@community.qnx.com
Cc: srilakshmi; srilakshmi
Subject: Re: PCI Express
srilakshmi wrote:
Through the attached file I am sending the output of pci -vvv.
My project board contains both Intel chip and FPGA chip on same board.
through PCI express slot we are connecting Xilinx board. Through PCIe we are
communicating with each other. And the result is checking at FPGA side by
Chipscope software.
Ok ... and this is a board from Xilinx with the vendor ID 10EEh ??
This board seems to be completely disabled ...
No I/O memory, no memory, no connection to an interrupt line.
Also the memory of 128 bytes referenced by BAR[0] is disabled !
Please see the marks at the printouts of the "pci" command:
Vendor ID = 10eeh, Xilinx Corporation
Device ID = 7h, Unknown Unknown
PCI index = 0h
Class Codes = 050000h
Revision ID = 0h
Bus number = 2
Device number = 0
Function num = 0
Status Reg = 10h
Command Reg = 0h
I/O space access disabled <<<============ !!!
Memory space access disabled <<<============ !!!
Bus Master disabled
Special Cycle operations ignored
Memory Write and Invalidate disabled <<<============ !!!
Palette Snooping disabled
Parity Error Response disabled
Data/Address stepping disabled
SERR# driver disabled
Fast back-to-back transactions to different agents disabled
PCI INTx enabled
Header type = 0h Single-function
BIST = 0h Build-in-self-test not supported
Latency Timer = 0h
Cache Line Size= 0h
BAR - 0 [Mem] = 0h 32bit length 128 disabled <<<========= !!!
Subsystem Vendor ID = 10eeh
Subsystem ID = 7h
Max Lat = 0ns
Min Gnt = 0ns
PCI Int Pin = INT A
Interrupt line = no connection <<<========== !!!
And the previous which you have sent to me is not working because
pci_dev_info predefined structure doesn't contain members like HeaderType,
CpuBmstrTranslation, CpuIsaTranslation, CpuMemTranslation, NumIrq,
info.MsiDefs[i].count
The example code previously posted by Hugh Brown is for QNX 6.5.
Are you working with QNX 6.4.x ??
Best Regards
--Armin
http://www.steinhoff-automation.com
Srilakshmi
-----Original Message-----
From: Armin Steinhoff [mailto:community-noreply@qnx.com]
Sent: Wednesday, June 20, 2012 11:59 PM
To: general-community@community.qnx.com
Cc: srilakshmi; srilakshmi
Subject: Re: PCI Express
srilakshmi wrote:
How to recognize interrupts coming from FPGA through PCI?
is this a board with a PCI interface together with separate FPGA chip??
Or is the PCI interface realized as a core of the FPGA?
Could you post the output of "pci -vvv" ?
Please provide me
document or code regarding this.
_______________________________________________
General
http://community.qnx.com/sf/go/post93788
To cancel your subscription to this discussion, please e-mail
general-community-unsubscribe@community.qnx.com
-----
No virus found in this message.
Checked by AVG - www.avg.com
Version: 2012.0.2177 / Virus Database: 2437/5081 - Release Date: 06/20/12
_______________________________________________
General
http://community.qnx.com/sf/go/post93792
To cancel your subscription to this discussion, please e-mail
general-community-unsubscribe@community.qnx.com
_____
No virus found in this message.
Checked by AVG - www.avg.com
Version: 2012.0.2177 / Virus Database: 2437/5082 - Release Date: 06/20/12
|
|
|
06/21/2012 6:47 AM
post93800
|
srilakshmi wrote:
>
> How to enable the interrupt line?
>
Your basically problem is that the board (FPGA core?) doesn't initialize
at hardware level the PCI interface.
The configuration data of the PCI interfaces are normaly provided by a
serial ROM.
Please checkout why the PCI interface isn't initialized!
Nothing can be done with an uninitialized PCI interface ...
--Armin
> Please provide me sample code or document or explanaion
>
> *From:*Armin Steinhoff [mailto:community-noreply@qnx.com]
> *Sent:* Thursday, June 21, 2012 2:08 PM
> *To:* general-community@community.qnx.com
> *Cc:* srilakshmi; srilakshmi
> *Subject:* Re: PCI Express
>
> srilakshmi wrote:
>
> Through the attached file I am sending the output of pci -vvv.
> My project board contains both Intel chip and FPGA chip on same board.
> through PCI express slot we are connecting Xilinx board. Through PCIe we are
> communicating with each other. And the result is checking at FPGA side by
> Chipscope software.
>
>
> Ok ... and this is a board from Xilinx with the vendor ID 10EEh ??
>
> This board seems to be completely disabled ...
> No I/O memory, no memory, no connection to an interrupt line.
> Also the memory of 128 bytes referenced by BAR[0] is disabled !
>
> Please see the marks at the printouts of the "pci" command:
>
> Vendor ID = 10eeh, Xilinx Corporation
> Device ID = 7h, Unknown Unknown
> PCI index = 0h
> Class Codes = 050000h
> Revision ID = 0h
> Bus number = 2
> Device number = 0
> Function num = 0
> Status Reg = 10h
> Command Reg = 0h
> I/O space access *disabled* <<<============ !!!
> Memory space access *disabled* <<<============ !!!
> Bus Master disabled
> Special Cycle operations ignored
> Memory Write and Invalidate *disabled* <<<============ !!!
> Palette Snooping disabled
> Parity Error Response disabled
> Data/Address stepping disabled
> SERR# driver disabled
> Fast back-to-back transactions to different agents disabled
> PCI INTx enabled
> Header type = 0h Single-function
> BIST = 0h Build-in-self-test not supported
> Latency Timer = 0h
> Cache Line Size= 0h
> BAR - 0 [Mem] = 0h 32bit length 128 *disabled* <<<========= !!!
> Subsystem Vendor ID = 10eeh
> Subsystem ID = 7h
> Max Lat = 0ns
> Min Gnt = 0ns
> PCI Int Pin = INT A
> Interrupt line = *no connection* <<<========== !!!
>
>
>
>
> And the previous which you have sent to me is not working because
> pci_dev_info predefined structure doesn't contain members like HeaderType,
> CpuBmstrTranslation, CpuIsaTranslation, CpuMemTranslation, NumIrq,
> info.MsiDefs[i].count
>
>
> The example code previously posted by Hugh Brown is for QNX 6.5.
> Are you working with QNX 6.4.x ??
>
> Best Regards
>
> --Armin
>
> http://www.steinhoff-automation.com
>
>
>
>
>
> Srilakshmi
>
>
> -----Original Message-----
> From: Armin Steinhoff [mailto:community-noreply@qnx.com]
> Sent: Wednesday, June 20, 2012 11:59 PM
> To:general-community@community.qnx.com <mailto:general-community@community.qnx.com>
> Cc: srilakshmi; srilakshmi
> Subject: Re: PCI Express
>
> srilakshmi wrote:
>
> How to recognize interrupts coming from FPGA through PCI?
>
>
> is this a board with a PCI interface together with separate FPGA chip??
> Or is the PCI interface realized as a core of the FPGA?
>
> Could you post the output of "pci -vvv" ?
>
>
>
> Please provide me
>
> document or code...
View Full Message
|
|
|
06/21/2012 7:00 AM
post93801
|
How to rectify this problem?
From: Armin Steinhoff [mailto:community-noreply@qnx.com]
Sent: Thursday, June 21, 2012 4:20 PM
To: general-community@community.qnx.com
Cc: srilakshmi; srilakshmi
Subject: Re: PCI Express
srilakshmi wrote:
How to enable the interrupt line?
Your basically problem is that the board (FPGA core?) doesn't initialize at
hardware level the PCI interface.
The configuration data of the PCI interfaces are normaly provided by a
serial ROM.
Please checkout why the PCI interface isn't initialized!
Nothing can be done with an uninitialized PCI interface ...
--Armin
Please provide me sample code or document or explanaion
From: Armin Steinhoff [mailto:community-noreply@qnx.com]
Sent: Thursday, June 21, 2012 2:08 PM
To: general-community@community.qnx.com
Cc: srilakshmi; srilakshmi
Subject: Re: PCI Express
srilakshmi wrote:
Through the attached file I am sending the output of pci -vvv.
My project board contains both Intel chip and FPGA chip on same board.
through PCI express slot we are connecting Xilinx board. Through PCIe we are
communicating with each other. And the result is checking at FPGA side by
Chipscope software.
Ok ... and this is a board from Xilinx with the vendor ID 10EEh ??
This board seems to be completely disabled ...
No I/O memory, no memory, no connection to an interrupt line.
Also the memory of 128 bytes referenced by BAR[0] is disabled !
Please see the marks at the printouts of the "pci" command:
Vendor ID = 10eeh, Xilinx Corporation
Device ID = 7h, Unknown Unknown
PCI index = 0h
Class Codes = 050000h
Revision ID = 0h
Bus number = 2
Device number = 0
Function num = 0
Status Reg = 10h
Command Reg = 0h
I/O space access disabled <<<============ !!!
Memory space access disabled <<<============ !!!
Bus Master disabled
Special Cycle operations ignored
Memory Write and Invalidate disabled <<<============ !!!
Palette Snooping disabled
Parity Error Response disabled
Data/Address stepping disabled
SERR# driver disabled
Fast back-to-back transactions to different agents disabled
PCI INTx enabled
Header type = 0h Single-function
BIST = 0h Build-in-self-test not supported
Latency Timer = 0h
Cache Line Size= 0h
BAR - 0 [Mem] = 0h 32bit length 128 disabled <<<========= !!!
Subsystem Vendor ID = 10eeh
Subsystem ID = 7h
Max Lat = 0ns
Min Gnt = 0ns
PCI Int Pin = INT A
Interrupt line = no connection <<<========== !!!
And the previous which you have sent to me is not working because
pci_dev_info predefined structure doesn't contain members like HeaderType,
CpuBmstrTranslation, CpuIsaTranslation, CpuMemTranslation, NumIrq,
info.MsiDefs[i].count
The example code previously posted by Hugh Brown is for QNX 6.5.
Are you working with QNX 6.4.x ??
Best Regards
--Armin
http://www.steinhoff-automation.com
Srilakshmi
-----Original Message-----
From: Armin Steinhoff [mailto:community-noreply@qnx.com]
Sent: Wednesday, June 20, 2012 11:59 PM
To: general-community@community.qnx.com
Cc: srilakshmi; srilakshmi
Subject: Re: PCI Express
srilakshmi wrote:
How to recognize interrupts coming from FPGA through PCI?
is this a board with a PCI interface together with separate FPGA chip??
Or is the PCI interface realized as a core of the FPGA?
Could you post the output of "pci -vvv" ?
Please provide me
document or code regarding this.
_______________________________________________
General
http://community.qnx.com/sf/go/post93788
To cancel your subscription to this discussion, please e-mail
general-community-unsubscribe@community.qnx.com
-----
No virus found in this message.
Checked by AVG -...
View Full Message
|
|
|
06/21/2012 7:16 AM
post93805
|
srilakshmi wrote:
>
> How to rectify this problem?
>
Please ask the guy behind the ChipScope :) He should know it ...
--Armin
> *From:*Armin Steinhoff [mailto:community-noreply@qnx.com]
> *Sent:* Thursday, June 21, 2012 4:20 PM
> *To:* general-community@community.qnx.com
> *Cc:* srilakshmi; srilakshmi
> *Subject:* Re: PCI Express
>
> srilakshmi wrote:
>
> How to enable the interrupt line?
>
>
> Your basically problem is that the board (FPGA core?) doesn't
> initialize at hardware level the PCI interface.
> The configuration data of the PCI interfaces are normaly provided by a
> serial ROM.
> Please checkout why the PCI interface isn't initialized!
>
> Nothing can be done with an uninitialized PCI interface ...
>
> --Armin
>
>
>
>
> Please provide me sample code or document or explanaion
>
> *From:*Armin Steinhoff [mailto:community-noreply@qnx.com]
> *Sent:* Thursday, June 21, 2012 2:08 PM
> *To:* general-community@community.qnx.com
> <mailto:general-community@community.qnx.com>
> *Cc:* srilakshmi; srilakshmi
> *Subject:* Re: PCI Express
>
> srilakshmi wrote:
>
> Through the attached file I am sending the output of pci -vvv.
> My project board contains both Intel chip and FPGA chip on same board.
> through PCI express slot we are connecting Xilinx board. Through PCIe we are
> communicating with each other. And the result is checking at FPGA side by
> Chipscope software.
>
>
> Ok ... and this is a board from Xilinx with the vendor ID 10EEh ??
>
> This board seems to be completely disabled ...
> No I/O memory, no memory, no connection to an interrupt line.
> Also the memory of 128 bytes referenced by BAR[0] is disabled !
>
> Please see the marks at the printouts of the "pci" command:
>
> Vendor ID = 10eeh, Xilinx Corporation
> Device ID = 7h, Unknown Unknown
> PCI index = 0h
> Class Codes = 050000h
> Revision ID = 0h
> Bus number = 2
> Device number = 0
> Function num = 0
> Status Reg = 10h
> Command Reg = 0h
> I/O space access *disabled* <<<============ !!!
> Memory space access *disabled* <<<============ !!!
> Bus Master disabled
> Special Cycle operations ignored
> Memory Write and Invalidate *disabled* <<<============ !!!
> Palette Snooping disabled
> Parity Error Response disabled
> Data/Address stepping disabled
> SERR# driver disabled
> Fast back-to-back transactions to different agents disabled
> PCI INTx enabled
> Header type = 0h Single-function
> BIST = 0h Build-in-self-test not supported
> Latency Timer = 0h
> Cache Line Size= 0h
> BAR - 0 [Mem] = 0h 32bit length 128 *disabled* <<<========= !!!
> Subsystem Vendor ID = 10eeh
> Subsystem ID = 7h
> Max Lat = 0ns
> Min Gnt = 0ns
> PCI Int Pin = INT A
> Interrupt line = *no connection* <<<========== !!!
>
>
>
>
>
> And the previous which you have sent to me is not working because
> pci_dev_info predefined structure doesn't contain members like HeaderType,
> CpuBmstrTranslation, CpuIsaTranslation, CpuMemTranslation, NumIrq,
> info.MsiDefs[i].count
>
>
> The example code previously posted by Hugh Brown is for QNX 6.5.
> Are you working with QNX 6.4.x ??
>
> Best Regards
>
> --Armin
>
> http://www.steinhoff-automation.com
>
>
>
>
>
>
> Srilakshmi
>
>
> -----Original Message-----
> From: Armin Steinhoff [mailto:community-noreply@qnx.com]
> Sent: Wednesday, June 20, 2012 11:59 PM
> To:general-community@community.qnx.com ...
View Full Message
|
|
|
06/21/2012 7:48 AM
post93807
|
When we are executing the code BAR 0 is mapping &128 bytes of data is
transmitting to FPGA board through PCIe slot. Now the problem is enabling
and recognizing the interrupts.
For this I need help
From: Armin Steinhoff [mailto:community-noreply@qnx.com]
Sent: Thursday, June 21, 2012 4:42 PM
To: general-community@community.qnx.com
Cc: srilakshmi; srilakshmi
Subject: Re: PCI Express
srilakshmi wrote:
How to rectify this problem?
Please ask the guy behind the ChipScope :) He should know it ...
--Armin
From: Armin Steinhoff [mailto:community-noreply@qnx.com]
Sent: Thursday, June 21, 2012 4:20 PM
To: general-community@community.qnx.com
Cc: srilakshmi; srilakshmi
Subject: Re: PCI Express
srilakshmi wrote:
How to enable the interrupt line?
Your basically problem is that the board (FPGA core?) doesn't initialize at
hardware level the PCI interface.
The configuration data of the PCI interfaces are normaly provided by a
serial ROM.
Please checkout why the PCI interface isn't initialized!
Nothing can be done with an uninitialized PCI interface ...
--Armin
Please provide me sample code or document or explanaion
From: Armin Steinhoff [mailto:community-noreply@qnx.com]
Sent: Thursday, June 21, 2012 2:08 PM
To: general-community@community.qnx.com
Cc: srilakshmi; srilakshmi
Subject: Re: PCI Express
srilakshmi wrote:
Through the attached file I am sending the output of pci -vvv.
My project board contains both Intel chip and FPGA chip on same board.
through PCI express slot we are connecting Xilinx board. Through PCIe we are
communicating with each other. And the result is checking at FPGA side by
Chipscope software.
Ok ... and this is a board from Xilinx with the vendor ID 10EEh ??
This board seems to be completely disabled ...
No I/O memory, no memory, no connection to an interrupt line.
Also the memory of 128 bytes referenced by BAR[0] is disabled !
Please see the marks at the printouts of the "pci" command:
Vendor ID = 10eeh, Xilinx Corporation
Device ID = 7h, Unknown Unknown
PCI index = 0h
Class Codes = 050000h
Revision ID = 0h
Bus number = 2
Device number = 0
Function num = 0
Status Reg = 10h
Command Reg = 0h
I/O space access disabled <<<============ !!!
Memory space access disabled <<<============ !!!
Bus Master disabled
Special Cycle operations ignored
Memory Write and Invalidate disabled <<<============ !!!
Palette Snooping disabled
Parity Error Response disabled
Data/Address stepping disabled
SERR# driver disabled
Fast back-to-back transactions to different agents disabled
PCI INTx enabled
Header type = 0h Single-function
BIST = 0h Build-in-self-test not supported
Latency Timer = 0h
Cache Line Size= 0h
BAR - 0 [Mem] = 0h 32bit length 128 disabled <<<========= !!!
Subsystem Vendor ID = 10eeh
Subsystem ID = 7h
Max Lat = 0ns
Min Gnt = 0ns
PCI Int Pin = INT A
Interrupt line = no connection <<<========== !!!
And the previous which you have sent to me is not working because
pci_dev_info predefined structure doesn't contain members like HeaderType,
CpuBmstrTranslation, CpuIsaTranslation, CpuMemTranslation, NumIrq,
info.MsiDefs[i].count
The example code previously posted by Hugh Brown is for QNX 6.5.
Are you working with QNX 6.4.x ??
Best Regards
--Armin
http://www.steinhoff-automation.com
Srilakshmi
-----Original Message-----
From: Armin Steinhoff [mailto:community-noreply@qnx.com]
Sent: Wednesday, June 20, 2012 11:59 PM
To: general-community@community.qnx.com
Cc: srilakshmi; srilakshmi
Subject: Re: PCI Express
srilakshmi wrote:
How to recognize interrupts coming from FPGA through PCI?
is...
View Full Message
|
|
|
06/21/2012 7:09 AM
post93803
|
When I am executing above attached code I am getting configuration data..
From: Armin Steinhoff [mailto:community-noreply@qnx.com]
Sent: Thursday, June 21, 2012 4:20 PM
To: general-community@community.qnx.com
Cc: srilakshmi; srilakshmi
Subject: Re: PCI Express
srilakshmi wrote:
How to enable the interrupt line?
Your basically problem is that the board (FPGA core?) doesn't initialize at
hardware level the PCI interface.
The configuration data of the PCI interfaces are normaly provided by a
serial ROM.
Please checkout why the PCI interface isn't initialized!
Nothing can be done with an uninitialized PCI interface ...
--Armin
Please provide me sample code or document or explanaion
From: Armin Steinhoff [mailto:community-noreply@qnx.com]
Sent: Thursday, June 21, 2012 2:08 PM
To: general-community@community.qnx.com
Cc: srilakshmi; srilakshmi
Subject: Re: PCI Express
srilakshmi wrote:
Through the attached file I am sending the output of pci -vvv.
My project board contains both Intel chip and FPGA chip on same board.
through PCI express slot we are connecting Xilinx board. Through PCIe we are
communicating with each other. And the result is checking at FPGA side by
Chipscope software.
Ok ... and this is a board from Xilinx with the vendor ID 10EEh ??
This board seems to be completely disabled ...
No I/O memory, no memory, no connection to an interrupt line.
Also the memory of 128 bytes referenced by BAR[0] is disabled !
Please see the marks at the printouts of the "pci" command:
Vendor ID = 10eeh, Xilinx Corporation
Device ID = 7h, Unknown Unknown
PCI index = 0h
Class Codes = 050000h
Revision ID = 0h
Bus number = 2
Device number = 0
Function num = 0
Status Reg = 10h
Command Reg = 0h
I/O space access disabled <<<============ !!!
Memory space access disabled <<<============ !!!
Bus Master disabled
Special Cycle operations ignored
Memory Write and Invalidate disabled <<<============ !!!
Palette Snooping disabled
Parity Error Response disabled
Data/Address stepping disabled
SERR# driver disabled
Fast back-to-back transactions to different agents disabled
PCI INTx enabled
Header type = 0h Single-function
BIST = 0h Build-in-self-test not supported
Latency Timer = 0h
Cache Line Size= 0h
BAR - 0 [Mem] = 0h 32bit length 128 disabled <<<========= !!!
Subsystem Vendor ID = 10eeh
Subsystem ID = 7h
Max Lat = 0ns
Min Gnt = 0ns
PCI Int Pin = INT A
Interrupt line = no connection <<<========== !!!
And the previous which you have sent to me is not working because
pci_dev_info predefined structure doesn't contain members like HeaderType,
CpuBmstrTranslation, CpuIsaTranslation, CpuMemTranslation, NumIrq,
info.MsiDefs[i].count
The example code previously posted by Hugh Brown is for QNX 6.5.
Are you working with QNX 6.4.x ??
Best Regards
--Armin
http://www.steinhoff-automation.com
Srilakshmi
-----Original Message-----
From: Armin Steinhoff [mailto:community-noreply@qnx.com]
Sent: Wednesday, June 20, 2012 11:59 PM
To: general-community@community.qnx.com
Cc: srilakshmi; srilakshmi
Subject: Re: PCI Express
srilakshmi wrote:
How to recognize interrupts coming from FPGA through PCI?
is this a board with a PCI interface together with separate FPGA chip??
Or is the PCI interface realized as a core of the FPGA?
Could you post the output of "pci -vvv" ?
Please provide me
document or code regarding this.
_______________________________________________
General
http://community.qnx.com/sf/go/post93788
To cancel your subscription to this discussion, please e-mail
general-community-unsubscribe@community.qnx.com
-----
No...
View Full Message
|
|
|
06/21/2012 7:36 AM
post93806
|
srilakshmi wrote:
>
> When I am executing above attached code I am getting configuration data..
>
Yes ... but you are reading configuration data from an uninitialzed
device which provides invalid data.
Just some comments about your code:
pci_read_config32(2,0,0x04,10,&buf); --> why not are
inf.BusNumber and inf. DevFunc not used ?
You have to check the memory type by PCI_IS_MEM() before you use
PCI_MEM_ADDR( )
It's not a good idea to map an IO address into normal memory.
If you have a support contract ... go back to QNX 6.4.1.
--Armin
> *From:*Armin Steinhoff [mailto:community-noreply@qnx.com]
> *Sent:* Thursday, June 21, 2012 4:20 PM
> *To:* general-community@community.qnx.com
> *Cc:* srilakshmi; srilakshmi
> *Subject:* Re: PCI Express
>
> srilakshmi wrote:
>
> How to enable the interrupt line?
>
>
> Your basically problem is that the board (FPGA core?) doesn't
> initialize at hardware level the PCI interface.
> The configuration data of the PCI interfaces are normaly provided by a
> serial ROM.
> Please checkout why the PCI interface isn't initialized!
>
> Nothing can be done with an uninitialized PCI interface ...
>
> --Armin
>
>
>
>
> Please provide me sample code or document or explanaion
>
> *From:*Armin Steinhoff [mailto:community-noreply@qnx.com]
> *Sent:* Thursday, June 21, 2012 2:08 PM
> *To:* general-community@community.qnx.com
> <mailto:general-community@community.qnx.com>
> *Cc:* srilakshmi; srilakshmi
> *Subject:* Re: PCI Express
>
> srilakshmi wrote:
>
> Through the attached file I am sending the output of pci -vvv.
> My project board contains both Intel chip and FPGA chip on same board.
> through PCI express slot we are connecting Xilinx board. Through PCIe we are
> communicating with each other. And the result is checking at FPGA side by
> Chipscope software.
>
>
> Ok ... and this is a board from Xilinx with the vendor ID 10EEh ??
>
> This board seems to be completely disabled ...
> No I/O memory, no memory, no connection to an interrupt line.
> Also the memory of 128 bytes referenced by BAR[0] is disabled !
>
> Please see the marks at the printouts of the "pci" command:
>
> Vendor ID = 10eeh, Xilinx Corporation
> Device ID = 7h, Unknown Unknown
> PCI index = 0h
> Class Codes = 050000h
> Revision ID = 0h
> Bus number = 2
> Device number = 0
> Function num = 0
> Status Reg = 10h
> Command Reg = 0h
> I/O space access *disabled* <<<============ !!!
> Memory space access *disabled* <<<============ !!!
> Bus Master disabled
> Special Cycle operations ignored
> Memory Write and Invalidate *disabled* <<<============ !!!
> Palette Snooping disabled
> Parity Error Response disabled
> Data/Address stepping disabled
> SERR# driver disabled
> Fast back-to-back transactions to different agents disabled
> PCI INTx enabled
> Header type = 0h Single-function
> BIST = 0h Build-in-self-test not supported
> Latency Timer = 0h
> Cache Line Size= 0h
> BAR - 0 [Mem] = 0h 32bit length 128 *disabled* <<<========= !!!
> Subsystem Vendor ID = 10eeh
> Subsystem ID = 7h
> Max Lat = 0ns
> Min Gnt = 0ns
> PCI Int Pin = INT A
> Interrupt line = *no connection* <<<========== !!!
>
>
>
>
>
> And the previous which you have sent to me is not working because
> pci_dev_info predefined structure doesn't contain members like HeaderType,
> CpuBmstrTranslation, CpuIsaTranslation, CpuMemTranslation, NumIrq,
> info.MsiDefs[i].count
>
>
> The example code...
View Full Message
|
|
|
06/21/2012 7:55 AM
post93808
|
But at FPGA side they receiving data through this code
From: Armin Steinhoff [mailto:community-noreply@qnx.com]
Sent: Thursday, June 21, 2012 5:08 PM
To: general-community@community.qnx.com
Cc: srilakshmi; srilakshmi
Subject: Re: PCI Express
srilakshmi wrote:
When I am executing above attached code I am getting configuration data..
Yes ... but you are reading configuration data from an uninitialzed device
which provides invalid data.
Just some comments about your code:
pci_read_config32(2,0,0x04,10,&buf); --> why not are inf.BusNumber and
inf. DevFunc not used ?
You have to check the memory type by PCI_IS_MEM() before you use
PCI_MEM_ADDR( )
It's not a good idea to map an IO address into normal memory.
If you have a support contract ... go back to QNX 6.4.1.
--Armin
From: Armin Steinhoff [mailto:community-noreply@qnx.com]
Sent: Thursday, June 21, 2012 4:20 PM
To: general-community@community.qnx.com
Cc: srilakshmi; srilakshmi
Subject: Re: PCI Express
srilakshmi wrote:
How to enable the interrupt line?
Your basically problem is that the board (FPGA core?) doesn't initialize at
hardware level the PCI interface.
The configuration data of the PCI interfaces are normaly provided by a
serial ROM.
Please checkout why the PCI interface isn't initialized!
Nothing can be done with an uninitialized PCI interface ...
--Armin
Please provide me sample code or document or explanaion
From: Armin Steinhoff [mailto:community-noreply@qnx.com]
Sent: Thursday, June 21, 2012 2:08 PM
To: general-community@community.qnx.com
Cc: srilakshmi; srilakshmi
Subject: Re: PCI Express
srilakshmi wrote:
Through the attached file I am sending the output of pci -vvv.
My project board contains both Intel chip and FPGA chip on same board.
through PCI express slot we are connecting Xilinx board. Through PCIe we are
communicating with each other. And the result is checking at FPGA side by
Chipscope software.
Ok ... and this is a board from Xilinx with the vendor ID 10EEh ??
This board seems to be completely disabled ...
No I/O memory, no memory, no connection to an interrupt line.
Also the memory of 128 bytes referenced by BAR[0] is disabled !
Please see the marks at the printouts of the "pci" command:
Vendor ID = 10eeh, Xilinx Corporation
Device ID = 7h, Unknown Unknown
PCI index = 0h
Class Codes = 050000h
Revision ID = 0h
Bus number = 2
Device number = 0
Function num = 0
Status Reg = 10h
Command Reg = 0h
I/O space access disabled <<<============ !!!
Memory space access disabled <<<============ !!!
Bus Master disabled
Special Cycle operations ignored
Memory Write and Invalidate disabled <<<============ !!!
Palette Snooping disabled
Parity Error Response disabled
Data/Address stepping disabled
SERR# driver disabled
Fast back-to-back transactions to different agents disabled
PCI INTx enabled
Header type = 0h Single-function
BIST = 0h Build-in-self-test not supported
Latency Timer = 0h
Cache Line Size= 0h
BAR - 0 [Mem] = 0h 32bit length 128 disabled <<<========= !!!
Subsystem Vendor ID = 10eeh
Subsystem ID = 7h
Max Lat = 0ns
Min Gnt = 0ns
PCI Int Pin = INT A
Interrupt line = no connection <<<========== !!!
And the previous which you have sent to me is not working because
pci_dev_info predefined structure doesn't contain members like HeaderType,
CpuBmstrTranslation, CpuIsaTranslation, CpuMemTranslation, NumIrq,
info.MsiDefs[i].count
The example code previously posted by Hugh Brown is for QNX 6.5.
Are you working with QNX 6.4.x ??
Best Regards
--Armin
http://www.steinhoff-automation.com
Srilakshmi
-----Original...
View Full Message
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06/21/2012 7:59 AM
post93809
|
We used pci_read_config32(2,0,0x04,10,&buf); for enabling DMA master to
transfer data to FPGA
From: Armin Steinhoff [mailto:community-noreply@qnx.com]
Sent: Thursday, June 21, 2012 5:08 PM
To: general-community@community.qnx.com
Cc: srilakshmi; srilakshmi
Subject: Re: PCI Express
srilakshmi wrote:
When I am executing above attached code I am getting configuration data..
Yes ... but you are reading configuration data from an uninitialzed device
which provides invalid data.
Just some comments about your code:
pci_read_config32(2,0,0x04,10,&buf); --> why not are inf.BusNumber and
inf. DevFunc not used ?
You have to check the memory type by PCI_IS_MEM() before you use
PCI_MEM_ADDR( )
It's not a good idea to map an IO address into normal memory.
If you have a support contract ... go back to QNX 6.4.1.
--Armin
From: Armin Steinhoff [mailto:community-noreply@qnx.com]
Sent: Thursday, June 21, 2012 4:20 PM
To: general-community@community.qnx.com
Cc: srilakshmi; srilakshmi
Subject: Re: PCI Express
srilakshmi wrote:
How to enable the interrupt line?
Your basically problem is that the board (FPGA core?) doesn't initialize at
hardware level the PCI interface.
The configuration data of the PCI interfaces are normaly provided by a
serial ROM.
Please checkout why the PCI interface isn't initialized!
Nothing can be done with an uninitialized PCI interface ...
--Armin
Please provide me sample code or document or explanaion
From: Armin Steinhoff [mailto:community-noreply@qnx.com]
Sent: Thursday, June 21, 2012 2:08 PM
To: general-community@community.qnx.com
Cc: srilakshmi; srilakshmi
Subject: Re: PCI Express
srilakshmi wrote:
Through the attached file I am sending the output of pci -vvv.
My project board contains both Intel chip and FPGA chip on same board.
through PCI express slot we are connecting Xilinx board. Through PCIe we are
communicating with each other. And the result is checking at FPGA side by
Chipscope software.
Ok ... and this is a board from Xilinx with the vendor ID 10EEh ??
This board seems to be completely disabled ...
No I/O memory, no memory, no connection to an interrupt line.
Also the memory of 128 bytes referenced by BAR[0] is disabled !
Please see the marks at the printouts of the "pci" command:
Vendor ID = 10eeh, Xilinx Corporation
Device ID = 7h, Unknown Unknown
PCI index = 0h
Class Codes = 050000h
Revision ID = 0h
Bus number = 2
Device number = 0
Function num = 0
Status Reg = 10h
Command Reg = 0h
I/O space access disabled <<<============ !!!
Memory space access disabled <<<============ !!!
Bus Master disabled
Special Cycle operations ignored
Memory Write and Invalidate disabled <<<============ !!!
Palette Snooping disabled
Parity Error Response disabled
Data/Address stepping disabled
SERR# driver disabled
Fast back-to-back transactions to different agents disabled
PCI INTx enabled
Header type = 0h Single-function
BIST = 0h Build-in-self-test not supported
Latency Timer = 0h
Cache Line Size= 0h
BAR - 0 [Mem] = 0h 32bit length 128 disabled <<<========= !!!
Subsystem Vendor ID = 10eeh
Subsystem ID = 7h
Max Lat = 0ns
Min Gnt = 0ns
PCI Int Pin = INT A
Interrupt line = no connection <<<========== !!!
And the previous which you have sent to me is not working because
pci_dev_info predefined structure doesn't contain members like HeaderType,
CpuBmstrTranslation, CpuIsaTranslation, CpuMemTranslation, NumIrq,
info.MsiDefs[i].count
The example code previously posted by Hugh Brown is for QNX 6.5.
Are you working with QNX 6.4.x ??
Best Regards
--Armin
http://www.steinhoff-automation.com
...
View Full Message
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06/21/2012 9:02 AM
post93810
|
srilakshmi wrote:
>
> We used pci_read_config32(2,0,0x04,10,&buf); for enabling DMA master
> to transfer data to FPGA
>
pci_read_config32(2,0,0x04,10,&buf); reads the following members of the
config space:
uint16_t Command; /* 0x04 */
uint16_t Status; /* 0x06 */
uint8_t Revision_ID; /* 0x08 */
uint8_t Class_Code[3]; /* 0x09 */
uint8_t Cache_Line_Size; /* 0x0C */
uint8_t Latency_Timer; /* 0x0D */
uint8_t Header_Type; /* 0x0E */
uint8_t BIST; /* 0x0F */
uint32_t Base_Address_Regs[6]; /* 0x10 */
uint32_t CardBus_CIS; /* 0x28 */
uint16_t Sub_Vendor_ID; /* 0x2C */
I don't know why reading the config space beginning at offset 0x04
should enable DMA processing ??
That's plain nonsens. Does your PCI interface really support DMA to an
asigned piece of memory ??
if you want to do DMA you have to run the PCI adapter at least as bus
master
hdl = pci_attach_device( NULL, PCI_INIT_ALL, pidx, &inf ); -->
hdl = pci_attach_device (NULL, PCI_INIT_ALL | PCI_INIT_ROM | PCI_PERSIST
| PCI_MASTER_ENABLE ,pidx, &inf);
--Armin
> *From:*Armin Steinhoff [mailto:community-noreply@qnx.com]
> *Sent:* Thursday, June 21, 2012 5:08 PM
> *To:* general-community@community.qnx.com
> *Cc:* srilakshmi; srilakshmi
> *Subject:* Re: PCI Express
>
> srilakshmi wrote:
>
> When I am executing above attached code I am getting configuration data..
>
>
> Yes ... but you are reading configuration data from an uninitialzed
> device which provides invalid data.
> Just some comments about your code:
>
> pci_read_config32(2,0,0x04,10,&buf); --> why not are
> inf.BusNumber and inf. DevFunc not used ?
>
> You have to check the memory type by PCI_IS_MEM() before you use
> PCI_MEM_ADDR( )
> It's not a good idea to map an IO address into normal memory.
>
> If you have a support contract ... go back to QNX 6.4.1.
>
> --Armin
>
>
>
> *From:*Armin Steinhoff [mailto:community-noreply@qnx.com]
> *Sent:* Thursday, June 21, 2012 4:20 PM
> *To:* general-community@community.qnx.com
> <mailto:general-community@community.qnx.com>
> *Cc:* srilakshmi; srilakshmi
> *Subject:* Re: PCI Express
>
> srilakshmi wrote:
>
> How to enable the interrupt line?
>
>
> Your basically problem is that the board (FPGA core?) doesn't
> initialize at hardware level the PCI interface.
> The configuration data of the PCI interfaces are normaly provided by a
> serial ROM.
> Please checkout why the PCI interface isn't initialized!
>
> Nothing can be done with an uninitialized PCI interface ...
>
> --Armin
>
>
>
>
>
> Please provide me sample code or document or explanaion
>
> *From:*Armin Steinhoff [mailto:community-noreply@qnx.com]
> *Sent:* Thursday, June 21, 2012 2:08 PM
> *To:* general-community@community.qnx.com
> <mailto:general-community@community.qnx.com>
> *Cc:* srilakshmi; srilakshmi
> *Subject:* Re: PCI Express
>
> srilakshmi wrote:
>
> Through the attached file I am sending the output of pci -vvv.
> My project board contains both Intel chip and FPGA chip on same board.
> through PCI express slot we are connecting Xilinx board. Through PCIe we are
> communicating with each other. And the result is checking at FPGA side by
> Chipscope software.
>
>
> Ok ... and this is a board from Xilinx with the vendor ID 10EEh...
View Full Message
|
|
|
06/28/2012 5:47 AM
post93917
|
Through the attachment I am sending output of pci -vvv command.
Now I need to enable interrupt.
You please provide me sample code for interrupts(functions for interrupts
are like InterruptAttach(),InterruptAttachEvent(),Interruptdetach,).
I am using QNX 6.5.0
From: Armin Steinhoff [mailto:community-noreply@qnx.com]
Sent: Thursday, June 21, 2012 6:35 PM
To: general-community@community.qnx.com
Cc: srilakshmi; srilakshmi
Subject: Re: PCI Express
srilakshmi wrote:
We used pci_read_config32(2,0,0x04,10,&buf); for enabling DMA master to
transfer data to FPGA
pci_read_config32(2,0,0x04,10,&buf); reads the following members of the
config space:
uint16_t Command; /* 0x04 */
uint16_t Status; /* 0x06 */
uint8_t Revision_ID; /* 0x08 */
uint8_t Class_Code[3]; /* 0x09 */
uint8_t Cache_Line_Size; /* 0x0C */
uint8_t Latency_Timer; /* 0x0D */
uint8_t Header_Type; /* 0x0E */
uint8_t BIST; /* 0x0F */
uint32_t Base_Address_Regs[6]; /* 0x10 */
uint32_t CardBus_CIS; /* 0x28 */
uint16_t Sub_Vendor_ID; /* 0x2C */
I don't know why reading the config space beginning at offset 0x04 should
enable DMA processing ??
That's plain nonsens. Does your PCI interface really support DMA to an
asigned piece of memory ??
if you want to do DMA you have to run the PCI adapter at least as bus master
hdl = pci_attach_device( NULL, PCI_INIT_ALL, pidx, &inf ); --> hdl =
pci_attach_device (NULL, PCI_INIT_ALL | PCI_INIT_ROM | PCI_PERSIST |
PCI_MASTER_ENABLE ,pidx, &inf);
--Armin
From: Armin Steinhoff [mailto:community-noreply@qnx.com]
Sent: Thursday, June 21, 2012 5:08 PM
To: general-community@community.qnx.com
Cc: srilakshmi; srilakshmi
Subject: Re: PCI Express
srilakshmi wrote:
When I am executing above attached code I am getting configuration data..
Yes ... but you are reading configuration data from an uninitialzed device
which provides invalid data.
Just some comments about your code:
pci_read_config32(2,0,0x04,10,&buf); --> why not are inf.BusNumber and
inf. DevFunc not used ?
You have to check the memory type by PCI_IS_MEM() before you use
PCI_MEM_ADDR( )
It's not a good idea to map an IO address into normal memory.
If you have a support contract ... go back to QNX 6.4.1.
--Armin
From: Armin Steinhoff [mailto:community-noreply@qnx.com]
Sent: Thursday, June 21, 2012 4:20 PM
To: general-community@community.qnx.com
Cc: srilakshmi; srilakshmi
Subject: Re: PCI Express
srilakshmi wrote:
How to enable the interrupt line?
Your basically problem is that the board (FPGA core?) doesn't initialize at
hardware level the PCI interface.
The configuration data of the PCI interfaces are normaly provided by a
serial ROM.
Please checkout why the PCI interface isn't initialized!
Nothing can be done with an uninitialized PCI interface ...
--Armin
Please provide me sample code or document or explanaion
From: Armin Steinhoff [mailto:community-noreply@qnx.com]
Sent: Thursday, June 21, 2012 2:08 PM
To: general-community@community.qnx.com
Cc: srilakshmi; srilakshmi
Subject: Re: PCI Express
srilakshmi wrote:
Through the attached file I am sending the output of pci -vvv.
My project board contains both Intel chip and FPGA chip on same board.
through PCI express slot we are connecting Xilinx board. Through PCIe we are
communicating with each other. And the result is checking at FPGA side by
Chipscope software.
Ok ... and this is a board from Xilinx with the...
View Full Message
|
|
|
06/28/2012 8:59 AM
post93919
|
Congratulation ! The PCI device is now in a good state !!
http://www.qnx.com/developers/docs/6.5.0/topic/com.qnx.doc.neutrino_prog/inthandler.html
--Armin
srilakshmi wrote:
>
> Through the attachment I am sending output of pci --vvv command.
>
> Now I need to enable interrupt.
>
> You please provide me sample code for interrupts(functions for
> interrupts are like
> InterruptAttach(),InterruptAttachEvent(),Interruptdetach,).
>
> I am using QNX 6.5.0
>
> *From:*Armin Steinhoff [mailto:community-noreply@qnx.com]
> *Sent:* Thursday, June 21, 2012 6:35 PM
> *To:* general-community@community.qnx.com
> *Cc:* srilakshmi; srilakshmi
> *Subject:* Re: PCI Express
>
> srilakshmi wrote:
>
> We used pci_read_config32(2,0,0x04,10,&buf); for enabling DMA master
> to transfer data to FPGA
>
>
> pci_read_config32(2,0,0x04,10,&buf); reads the following members of
> the config space:
>
> uint16_t Command; /* 0x04 */
> uint16_t Status; /* 0x06 */
> uint8_t Revision_ID; /* 0x08 */
> uint8_t Class_Code[3]; /* 0x09 */
> uint8_t Cache_Line_Size; /* 0x0C */
> uint8_t Latency_Timer; /* 0x0D */
> uint8_t Header_Type; /* 0x0E */
> uint8_t BIST; /* 0x0F */
> uint32_t Base_Address_Regs[6]; /* 0x10 */
> uint32_t CardBus_CIS; /* 0x28 */
> uint16_t Sub_Vendor_ID; /* 0x2C */
>
> I don't know why reading the config space beginning at offset 0x04
> should enable DMA processing ??
> That's plain nonsens. Does your PCI interface really support DMA to an
> asigned piece of memory ??
>
> if you want to do DMA you have to run the PCI adapter at least as bus
> master
> hdl = pci_attach_device( NULL, PCI_INIT_ALL, pidx, &inf ); -->
> hdl = pci_attach_device (NULL, PCI_INIT_ALL | PCI_INIT_ROM |
> PCI_PERSIST | PCI_MASTER_ENABLE ,pidx, &inf);
>
>
> --Armin
>
>
>
>
> *From:*Armin Steinhoff [mailto:community-noreply@qnx.com]
> *Sent:* Thursday, June 21, 2012 5:08 PM
> *To:* general-community@community.qnx.com
> <mailto:general-community@community.qnx.com>
> *Cc:* srilakshmi; srilakshmi
> *Subject:* Re: PCI Express
>
> srilakshmi wrote:
>
> When I am executing above attached code I am getting configuration data..
>
>
> Yes ... but you are reading configuration data from an uninitialzed
> device which provides invalid data.
> Just some comments about your code:
>
> pci_read_config32(2,0,0x04,10,&buf); --> why not are
> inf.BusNumber and inf. DevFunc not used ?
>
> You have to check the memory type by PCI_IS_MEM() before you use
> PCI_MEM_ADDR( )
> It's not a good idea to map an IO address into normal memory.
>
> If you have a support contract ... go back to QNX 6.4.1.
>
> --Armin
>
>
>
>
> *From:*Armin Steinhoff [mailto:community-noreply@qnx.com]
> *Sent:* Thursday, June 21, 2012 4:20 PM
> *To:* general-community@community.qnx.com
> <mailto:general-community@community.qnx.com>
> *Cc:* srilakshmi; srilakshmi
> *Subject:* Re: PCI Express
>
> srilakshmi wrote:
>
> How to enable the interrupt line?
>
>
> Your basically problem is that the board (FPGA core?) doesn't
> initialize at hardware level the PCI interface.
> The configuration data of the PCI interfaces are normaly provided by a
> serial ROM.
> Please checkout why the PCI interface isn't initialized!
>
> Nothing can be done with an uninitialized PCI interface ...
>
> --Armin
>
>
>
>
>
>
> Please provide me sample code or document or explanaion
>
> *From:*Armin Steinhoff...
View Full Message
|
|
|
06/29/2012 5:20 AM
post93949
|
Through the attachment I am sending new output of pci -vvv command.
FPGA developer has changed some values like Device ID, Irq..
Now my target is interrupts to master FPGA through PCIe.
Will you please provide me guidance / suggestions?
Send me any sample code regarding interrupts.
Thanks & Regards
Srilakshmi
From: Armin Steinhoff [mailto:community-noreply@qnx.com]
Sent: Thursday, June 21, 2012 6:35 PM
To: general-community@community.qnx.com
Cc: srilakshmi; srilakshmi
Subject: Re: PCI Express
srilakshmi wrote:
We used pci_read_config32(2,0,0x04,10,&buf); for enabling DMA master to
transfer data to FPGA
pci_read_config32(2,0,0x04,10,&buf); reads the following members of the
config space:
uint16_t Command; /* 0x04 */
uint16_t Status; /* 0x06 */
uint8_t Revision_ID; /* 0x08 */
uint8_t Class_Code[3]; /* 0x09 */
uint8_t Cache_Line_Size; /* 0x0C */
uint8_t Latency_Timer; /* 0x0D */
uint8_t Header_Type; /* 0x0E */
uint8_t BIST; /* 0x0F */
uint32_t Base_Address_Regs[6]; /* 0x10 */
uint32_t CardBus_CIS; /* 0x28 */
uint16_t Sub_Vendor_ID; /* 0x2C */
I don't know why reading the config space beginning at offset 0x04 should
enable DMA processing ??
That's plain nonsens. Does your PCI interface really support DMA to an
asigned piece of memory ??
if you want to do DMA you have to run the PCI adapter at least as bus master
hdl = pci_attach_device( NULL, PCI_INIT_ALL, pidx, &inf ); --> hdl =
pci_attach_device (NULL, PCI_INIT_ALL | PCI_INIT_ROM | PCI_PERSIST |
PCI_MASTER_ENABLE ,pidx, &inf);
--Armin
From: Armin Steinhoff [mailto:community-noreply@qnx.com]
Sent: Thursday, June 21, 2012 5:08 PM
To: general-community@community.qnx.com
Cc: srilakshmi; srilakshmi
Subject: Re: PCI Express
srilakshmi wrote:
When I am executing above attached code I am getting configuration data..
Yes ... but you are reading configuration data from an uninitialzed device
which provides invalid data.
Just some comments about your code:
pci_read_config32(2,0,0x04,10,&buf); --> why not are inf.BusNumber and
inf. DevFunc not used ?
You have to check the memory type by PCI_IS_MEM() before you use
PCI_MEM_ADDR( )
It's not a good idea to map an IO address into normal memory.
If you have a support contract ... go back to QNX 6.4.1.
--Armin
From: Armin Steinhoff [mailto:community-noreply@qnx.com]
Sent: Thursday, June 21, 2012 4:20 PM
To: general-community@community.qnx.com
Cc: srilakshmi; srilakshmi
Subject: Re: PCI Express
srilakshmi wrote:
How to enable the interrupt line?
Your basically problem is that the board (FPGA core?) doesn't initialize at
hardware level the PCI interface.
The configuration data of the PCI interfaces are normaly provided by a
serial ROM.
Please checkout why the PCI interface isn't initialized!
Nothing can be done with an uninitialized PCI interface ...
--Armin
Please provide me sample code or document or explanaion
From: Armin Steinhoff [mailto:community-noreply@qnx.com]
Sent: Thursday, June 21, 2012 2:08 PM
To: general-community@community.qnx.com
Cc: srilakshmi; srilakshmi
Subject: Re: PCI Express
srilakshmi wrote:
Through the attached file I am sending the output of pci -vvv.
My project board contains both Intel chip and FPGA chip on same board.
through PCI express slot we are connecting Xilinx board. Through PCIe we are
communicating with each other. And the result is checking at FPGA side...
View Full Message
|
|
|
06/29/2012 10:38 AM
post93951
|
srilakshmi wrote:
>
> Through the attachment I am sending new output of pci --vvv command.
>
> FPGA developer has changed some values like Device ID, Irq....
>
> Now my target is interrupts to master FPGA through PCIe.
>
> Will you please provide me guidance / suggestions?
>
Yes ... but I have no intention to do your job :)
However ... load the example code from:
http://www.qnx.com/download/download/23638/cookbook_code.zip
--Armin
> Send me any sample code regarding interrupts.
>
> Thanks & Regards
>
> Srilakshmi
>
> *From:*Armin Steinhoff [mailto:community-noreply@qnx.com]
> *Sent:* Thursday, June 21, 2012 6:35 PM
> *To:* general-community@community.qnx.com
> *Cc:* srilakshmi; srilakshmi
> *Subject:* Re: PCI Express
>
> srilakshmi wrote:
>
> We used pci_read_config32(2,0,0x04,10,&buf); for enabling DMA master
> to transfer data to FPGA
>
>
> pci_read_config32(2,0,0x04,10,&buf); reads the following members of
> the config space:
>
> uint16_t Command; /* 0x04 */
> uint16_t Status; /* 0x06 */
> uint8_t Revision_ID; /* 0x08 */
> uint8_t Class_Code[3]; /* 0x09 */
> uint8_t Cache_Line_Size; /* 0x0C */
> uint8_t Latency_Timer; /* 0x0D */
> uint8_t Header_Type; /* 0x0E */
> uint8_t BIST; /* 0x0F */
> uint32_t Base_Address_Regs[6]; /* 0x10 */
> uint32_t CardBus_CIS; /* 0x28 */
> uint16_t Sub_Vendor_ID; /* 0x2C */
>
> I don't know why reading the config space beginning at offset 0x04
> should enable DMA processing ??
> That's plain nonsens. Does your PCI interface really support DMA to an
> asigned piece of memory ??
>
> if you want to do DMA you have to run the PCI adapter at least as bus
> master
> hdl = pci_attach_device( NULL, PCI_INIT_ALL, pidx, &inf ); -->
> hdl = pci_attach_device (NULL, PCI_INIT_ALL | PCI_INIT_ROM |
> PCI_PERSIST | PCI_MASTER_ENABLE ,pidx, &inf);
>
>
> --Armin
>
>
>
>
> *From:*Armin Steinhoff [mailto:community-noreply@qnx.com]
> *Sent:* Thursday, June 21, 2012 5:08 PM
> *To:* general-community@community.qnx.com
> <mailto:general-community@community.qnx.com>
> *Cc:* srilakshmi; srilakshmi
> *Subject:* Re: PCI Express
>
> srilakshmi wrote:
>
> When I am executing above attached code I am getting configuration data..
>
>
> Yes ... but you are reading configuration data from an uninitialzed
> device which provides invalid data.
> Just some comments about your code:
>
> pci_read_config32(2,0,0x04,10,&buf); --> why not are
> inf.BusNumber and inf. DevFunc not used ?
>
> You have to check the memory type by PCI_IS_MEM() before you use
> PCI_MEM_ADDR( )
> It's not a good idea to map an IO address into normal memory.
>
> If you have a support contract ... go back to QNX 6.4.1.
>
> --Armin
>
>
>
>
> *From:*Armin Steinhoff [mailto:community-noreply@qnx.com]
> *Sent:* Thursday, June 21, 2012 4:20 PM
> *To:* general-community@community.qnx.com
> <mailto:general-community@community.qnx.com>
> *Cc:* srilakshmi; srilakshmi
> *Subject:* Re: PCI Express
>
> srilakshmi wrote:
>
> How to enable the interrupt line?
>
>
> Your basically problem is that the board (FPGA core?) doesn't
> initialize at hardware level the PCI interface.
> The configuration data of the PCI interfaces are normaly provided by a
> serial ROM.
> Please checkout why the PCI interface isn't initialized!
>
> Nothing can be done with an uninitialized PCI interface ...
>
> --Armin
>
>
>
>
>
>
> Please provide me sample code or document...
View Full Message
|
|
|
06/16/2012 10:09 AM
post93714
|
Srilakshmi,
is the PCI interface realized as a core of the FPGA ?
If yes, do you have the VHDL code of that core?
Or is the PCI interface based on one of these standard chips ? (PLX xxx a.s.o)
Could you post the output of "pci -vvv" ?
What is the functionalty of your board ?
--Armin
http://www.steinhoff-automation.com
srilakshmi wrote:
> We are able to transfer TLP with 1byte of data for Memory write transaction.
> You please help me to send more bytes of data through PCI express from Intel
> to FPGA.
>
> Thanks& Regards
> Srilakshmi
>
> -----Original Message-----
> From: Hugh Brown [mailto:community-noreply@qnx.com]
> Sent: Tuesday, June 05, 2012 5:06 PM
> To: general-community@community.qnx.com
> Subject: Re: PCI Express
>
> As I have said before, I don't know how your FPGA works, so you will have
> to contact whoever designed your FPGA.
>
|
|
|
06/22/2012 2:57 PM
post93840
|
Are there any plans to implement PCIe support for ARM based platforms?
|
|
|
06/22/2012 4:46 PM
post93846
|
There is no standard PCIe interface for ARM, so you will have to be more
specific as to what platform you are targeting.
--
Hugh Brown
QNX Software Systems Limited
1001 Farrar Rd.,
Ottawa. ON. K2K 0B3.
Telephone: 613-591-0931
On 12-06-22 2:57 PM, "Bratislav Matic" <community-noreply@qnx.com> wrote:
>Are there any plans to implement PCIe support for ARM based platforms?
>
>
>
>_______________________________________________
>
>General
>http://community.qnx.com/sf/go/post93840
>To cancel your subscription to this discussion, please e-mail
>general-community-unsubscribe@community.qnx.com
|
|
|
06/30/2012 6:41 AM
post93959
|
Through attachment I am sending output of pci -vvv command.
Would you please help me how to generate interrupts from Intel to master
FPGA through PCI.
Thanks & Regards
Srilakshmi
-----Original Message-----
From: Hugh Brown [mailto:community-noreply@qnx.com]
Sent: Saturday, June 23, 2012 2:10 AM
To: general-community@community.qnx.com
Subject: Re: PCI Express
There is no standard PCIe interface for ARM, so you will have to be more
specific as to what platform you are targeting.
--
Hugh Brown
QNX Software Systems Limited
1001 Farrar Rd.,
Ottawa. ON. K2K 0B3.
Telephone: 613-591-0931
On 12-06-22 2:57 PM, "Bratislav Matic" <community-noreply@qnx.com> wrote:
>Are there any plans to implement PCIe support for ARM based platforms?
>
>
>
>_______________________________________________
>
>General
>http://community.qnx.com/sf/go/post93840
>To cancel your subscription to this discussion, please e-mail
>general-community-unsubscribe@community.qnx.com
_______________________________________________
General
http://community.qnx.com/sf/go/post93846
To cancel your subscription to this discussion, please e-mail
general-community-unsubscribe@community.qnx.com
-----
No virus found in this message.
Checked by AVG - www.avg.com
Version: 2012.0.2177 / Virus Database: 2437/5097 - Release Date: 06/27/12
|
|
|
07/01/2012 9:38 AM
post93960
|
Wow,
is this a restart of the whole thread ??
Please send me the output of the attached utility lspci created by "lspci -vvvxx" and "lcpci -tv".
It's a port from Linux to QNX 6 ... it doesn't use any QNX specific code :)
Did you download and study the code examples provided be QSS(L) ??
--Armin
> Through attachment I am sending output of pci -vvv command.
> Would you please help me how to generate interrupts from Intel to master
> FPGA through PCI.
>
> Thanks & Regards
> Srilakshmi
>
> -----Original Message-----
> From: Hugh Brown [mailto:community-noreply@qnx.com]
> Sent: Saturday, June 23, 2012 2:10 AM
> To: general-community@community.qnx.com
> Subject: Re: PCI Express
>
> There is no standard PCIe interface for ARM, so you will have to be more
> specific as to what platform you are targeting.
>
> --
> Hugh Brown
> QNX Software Systems Limited
> 1001 Farrar Rd.,
> Ottawa. ON. K2K 0B3.
> Telephone: 613-591-0931
>
>
>
>
>
>
>
> On 12-06-22 2:57 PM, "Bratislav Matic" <community-noreply@qnx.com> wrote:
>
> >Are there any plans to implement PCIe support for ARM based platforms?
> >
> >
> >
> >_______________________________________________
> >
> >General
> >http://community.qnx.com/sf/go/post93840
> >To cancel your subscription to this discussion, please e-mail
> >general-community-unsubscribe@community.qnx.com
>
>
>
>
>
> _______________________________________________
>
> General
> http://community.qnx.com/sf/go/post93846
> To cancel your subscription to this discussion, please e-mail
> general-community-unsubscribe@community.qnx.com
>
> -----
> No virus found in this message.
> Checked by AVG - www.avg.com
> Version: 2012.0.2177 / Virus Database: 2437/5097 - Release Date: 06/27/12
>
|
|
|
07/01/2012 1:14 PM
post93961
|
> Through attachment I am sending output of pci -vvv command.
> Would you please help me how to generate interrupts from Intel to
> master FPGA through PCI.
>
Are you understanding what is being said over and over. This is a QNX6 forum, most of the questions you asked have
NOTHING do to with QNX. Your questions show a total lack of understanding of the PCI bus and of the device you are
working with. You need to do some reading or asks on different forum.
To contradict what I just said: the Intel cannot send an interrupt signal, there is no interrupt line GOING to the PCI.
If you want to trigger an interrupt internal to the card you would have to write into a register or IO on the card.
Again THIS HAS NOTHING TO DO WITH PCI OR QNX.
> Thanks & Regards
> Srilakshmi
>
> -----Original Message-----
> From: Hugh Brown [mailto:community-noreply@qnx.com]
> Sent: Saturday, June 23, 2012 2:10 AM
> To: general-community@community.qnx.com
> Subject: Re: PCI Express
>
> There is no standard PCIe interface for ARM, so you will have to be
> more specific as to what platform you are targeting.
>
> --
> Hugh Brown
> QNX Software Systems Limited
> 1001 Farrar Rd.,
> Ottawa. ON. K2K 0B3.
> Telephone: 613-591-0931
>
>
>
>
>
>
>
> On 12-06-22 2:57 PM, "Bratislav Matic" <community-noreply@qnx.com> wrote:
>
> >Are there any plans to implement PCIe support for ARM based platforms?
> >
> >
> >
> >_______________________________________________
> >
> >General
> >http://community.qnx.com/sf/go/post93840
> >To cancel your subscription to this discussion, please e-mail
> >general-community-unsubscribe@community.qnx.com
>
>
>
>
>
> _______________________________________________
>
> General
> http://community.qnx.com/sf/go/post93846
> To cancel your subscription to this discussion, please e-mail
> general-community-unsubscribe@community.qnx.com
>
> -----
> No virus found in this message.
> Checked by AVG - www.avg.com
> Version: 2012.0.2177 / Virus Database: 2437/5097 - Release Date:
> 06/27/12
>
_______________________________________________
General
http://community.qnx.com/sf/go/post93960
To cancel your subscription to this discussion, please e-mail general-community-unsubscribe@community.qnx.com
|
|
|
07/01/2012 6:28 PM
post93962
|
Hi,
I have to add that the PCIe bus interface also doesn't have an interrupt
line to signal an interrupt to the CPU.
It sends a message (MSI) to the chip set and at the end to the CPU to
"signal" an interrupt.
There is no way that the CPU could send an interrupt to a PCI device :)
--Armin
Mario Charest wrote:
>> Through attachment I am sending output of pci -vvv command.
>> Would you please help me how to generate interrupts from Intel to
>> master FPGA through PCI.
>>
> Are you understanding what is being said over and over. This is a QNX6 forum, most of the questions you asked have
NOTHING do to with QNX. Your questions show a total lack of understanding of the PCI bus and of the device you are
working with. You need to do some reading or asks on different forum.
>
> To contradict what I just said: the Intel cannot send an interrupt signal, there is no interrupt line GOING to the
PCI. If you want to trigger an interrupt internal to the card you would have to write into a register or IO on the
card. Again THIS HAS NOTHING TO DO WITH PCI OR QNX.
>
>> Thanks & Regards
>> Srilakshmi
>>
>> -----Original Message-----
>> From: Hugh Brown [mailto:community-noreply@qnx.com]
>> Sent: Saturday, June 23, 2012 2:10 AM
>> To: general-community@community.qnx.com
>> Subject: Re: PCI Express
>>
>> There is no standard PCIe interface for ARM, so you will have to be
>> more specific as to what platform you are targeting.
>>
>> --
>> Hugh Brown
>> QNX Software Systems Limited
>> 1001 Farrar Rd.,
>> Ottawa. ON. K2K 0B3.
>> Telephone: 613-591-0931
>>
>>
>>
>>
>>
>>
>>
>> On 12-06-22 2:57 PM, "Bratislav Matic" <community-noreply@qnx.com> wrote:
>>
>>> Are there any plans to implement PCIe support for ARM based platforms?
>>>
>>>
>>>
>>> _______________________________________________
>>>
>>> General
>>> http://community.qnx.com/sf/go/post93840
>>> To cancel your subscription to this discussion, please e-mail
>>> general-community-unsubscribe@community.qnx.com
>>
>>
>>
>>
>> _______________________________________________
>>
>> General
>> http://community.qnx.com/sf/go/post93846
>> To cancel your subscription to this discussion, please e-mail
>> general-community-unsubscribe@community.qnx.com
>>
>> -----
>> No virus found in this message.
>> Checked by AVG - www.avg.com
>> Version: 2012.0.2177 / Virus Database: 2437/5097 - Release Date:
>> 06/27/12
>>
>
>
>
>
>
> _______________________________________________
>
> General
> http://community.qnx.com/sf/go/post93960
> To cancel your subscription to this discussion, please e-mail general-community-unsubscribe@community.qnx.com
>
>
>
>
> _______________________________________________
>
> General
> http://community.qnx.com/sf/go/post93961
> To cancel your subscription to this discussion, please e-mail general-community-unsubscribe@community.qnx.com
>
|
|
|
07/02/2012 12:37 AM
post93963
|
Thank you for your reply with useful information.
Do you have any documents regarding pci express in QNX?
How to generate message signaled interrupts?
If you had please send to me the respective documents.
I want to improve my knowledge regarding PCIe, QNX to do project
Thanks & Regards
Srilakshmi
-----Original Message-----
From: Mario Charest [mailto:community-noreply@qnx.com]
Sent: Sunday, July 01, 2012 10:38 PM
To: general-community@community.qnx.com
Subject: RE: RE: PCI Express
> Through attachment I am sending output of pci -vvv command.
> Would you please help me how to generate interrupts from Intel to
> master FPGA through PCI.
>
Are you understanding what is being said over and over. This is a QNX6
forum, most of the questions you asked have NOTHING do to with QNX. Your
questions show a total lack of understanding of the PCI bus and of the
device you are working with. You need to do some reading or asks on
different forum.
To contradict what I just said: the Intel cannot send an interrupt signal,
there is no interrupt line GOING to the PCI. If you want to trigger an
interrupt internal to the card you would have to write into a register or
IO on the card. Again THIS HAS NOTHING TO DO WITH PCI OR QNX.
> Thanks & Regards
> Srilakshmi
>
> -----Original Message-----
> From: Hugh Brown [mailto:community-noreply@qnx.com]
> Sent: Saturday, June 23, 2012 2:10 AM
> To: general-community@community.qnx.com
> Subject: Re: PCI Express
>
> There is no standard PCIe interface for ARM, so you will have to be
> more specific as to what platform you are targeting.
>
> --
> Hugh Brown
> QNX Software Systems Limited
> 1001 Farrar Rd.,
> Ottawa. ON. K2K 0B3.
> Telephone: 613-591-0931
>
>
>
>
>
>
>
> On 12-06-22 2:57 PM, "Bratislav Matic" <community-noreply@qnx.com> wrote:
>
> >Are there any plans to implement PCIe support for ARM based platforms?
> >
> >
> >
> >_______________________________________________
> >
> >General
> >http://community.qnx.com/sf/go/post93840
> >To cancel your subscription to this discussion, please e-mail
> >general-community-unsubscribe@community.qnx.com
>
>
>
>
>
> _______________________________________________
>
> General
> http://community.qnx.com/sf/go/post93846
> To cancel your subscription to this discussion, please e-mail
> general-community-unsubscribe@community.qnx.com
>
> -----
> No virus found in this message.
> Checked by AVG - www.avg.com
> Version: 2012.0.2177 / Virus Database: 2437/5097 - Release Date:
> 06/27/12
>
_______________________________________________
General
http://community.qnx.com/sf/go/post93960
To cancel your subscription to this discussion, please e-mail
general-community-unsubscribe@community.qnx.com
_______________________________________________
General
http://community.qnx.com/sf/go/post93961
To cancel your subscription to this discussion, please e-mail
general-community-unsubscribe@community.qnx.com
-----
No virus found in this message.
Checked by AVG - www.avg.com
Version: 2012.0.2177 / Virus Database: 2437/5102 - Release Date: 06/30/12
|
|
|
07/02/2012 3:53 AM
post93964
|
srilakshmi wrote:
> Thank you for your reply with useful information.
> Do you have any documents regarding pci express in QNX?
In general, PCI Express has nothing to do with QNX.
It is just a hardware standard ... hopfully cleanly supported by QNX
6.5 SP1.
> How to generate message signaled interrupts?
Only PCIe devices can send message signaled interrupts ... and this
happens ONLY at HARDWARE level!!
QNX is not involved at that low level functions.
>
> If you had please send to me the respective documents.
> I want to improve my knowledge regarding PCIe,
See the attachment ... and forget QNX in that context.
--Armin
|
|
|
07/02/2012 5:22 AM
post93965
|
It's a QNX software problem.
After we open and compiled single program.
If we want to try again to open or compile same program or any other code
we are getting
" too many session files in /tmp"
due to this system getting hanged. Every time we need to restart the system
to do something.
Its happening frequently.
Would you give me the solution for this?
Thanks & Regards
Srilakshmi
-----Original Message-----
From: Armin Steinhoff [mailto:community-noreply@qnx.com]
Sent: Monday, July 02, 2012 1:23 PM
To: general-community@community.qnx.com
Cc: srilakshmi; srilakshmi
Subject: Re: PCI Express
srilakshmi wrote:
> Thank you for your reply with useful information.
> Do you have any documents regarding pci express in QNX?
In general, PCI Express has nothing to do with QNX.
It is just a hardware standard ... hopfully cleanly supported by QNX
6.5 SP1.
> How to generate message signaled interrupts?
Only PCIe devices can send message signaled interrupts ... and this
happens ONLY at HARDWARE level!!
QNX is not involved at that low level functions.
>
> If you had please send to me the respective documents.
> I want to improve my knowledge regarding PCIe,
See the attachment ... and forget QNX in that context.
--Armin
_______________________________________________
General
http://community.qnx.com/sf/go/post93964
To cancel your subscription to this discussion, please e-mail
general-community-unsubscribe@community.qnx.com
-----
No virus found in this message.
Checked by AVG - www.avg.com
Version: 2012.0.2177 / Virus Database: 2437/5105 - Release Date: 07/01/12
|
|
|
07/02/2012 5:38 AM
post93966
|
srilakshmi wrote:
> It's a QNX software problem.
IMHO ... it's not a problem with QNX software.
It's a problem of YOUR software which seems to kill the whole system :)
> After we open and compiled single program.
What means "open" your "compiled single program" ??
Could you post a screen dump of your terminal session and the sources of
your program ??
> If we want to try again to open or compile same program or any other code
> we are getting
> " too many session files in /tmp"
> due to this system getting hanged. Every time we need to restart the system
> to do something.
> Its happening frequently.
>
> Would you give me the solution for this?
Yes, change your code ...
--Armin
>
> Thanks & Regards
> Srilakshmi
>
>
>
>
> -----Original Message-----
> From: Armin Steinhoff [mailto:community-noreply@qnx.com]
> Sent: Monday, July 02, 2012 1:23 PM
> To: general-community@community.qnx.com
> Cc: srilakshmi; srilakshmi
> Subject: Re: PCI Express
>
> srilakshmi wrote:
>> Thank you for your reply with useful information.
>> Do you have any documents regarding pci express in QNX?
> In general, PCI Express has nothing to do with QNX.
> It is just a hardware standard ... hopfully cleanly supported by QNX
> 6.5 SP1.
>
>
>> How to generate message signaled interrupts?
> Only PCIe devices can send message signaled interrupts ... and this
> happens ONLY at HARDWARE level!!
> QNX is not involved at that low level functions.
>
>> If you had please send to me the respective documents.
>> I want to improve my knowledge regarding PCIe,
> See the attachment ... and forget QNX in that context.
>
> --Armin
>
>
>
>
>
>
> _______________________________________________
>
> General
> http://community.qnx.com/sf/go/post93964
> To cancel your subscription to this discussion, please e-mail
> general-community-unsubscribe@community.qnx.com
>
> -----
> No virus found in this message.
> Checked by AVG - www.avg.com
> Version: 2012.0.2177 / Virus Database: 2437/5105 - Release Date: 07/01/12
>
>
>
>
>
> _______________________________________________
>
> General
> http://community.qnx.com/sf/go/post93965
> To cancel your subscription to this discussion, please e-mail general-community-unsubscribe@community.qnx.com
>
|
|
|
07/02/2012 6:50 AM
post93967
|
Armin,
I got the say, I never expected you to show that much patience, lol! Maybe he is using google translate and some stuff
is getting lost in the translation?
Cheers,
-----Message d'origine-----
De : Armin Steinhoff [mailto:community-noreply@qnx.com]
Envoyé : Monday, July 02, 2012 5:39 AM
À : general-community@community.qnx.com
Cc : srilakshmi; srilakshmi
Objet : Re: PCI Express
srilakshmi wrote:
> It's a QNX software problem.
IMHO ... it's not a problem with QNX software.
It's a problem of YOUR software which seems to kill the whole system :)
> After we open and compiled single program.
What means "open" your "compiled single program" ??
Could you post a screen dump of your terminal session and the sources of your program ??
> If we want to try again to open or compile same program or any other
> code we are getting
> " too many session files in /tmp"
> due to this system getting hanged. Every time we need to restart the
> system to do something.
> Its happening frequently.
>
> Would you give me the solution for this?
Yes, change your code ...
--Armin
>
> Thanks & Regards
> Srilakshmi
>
>
>
>
> -----Original Message-----
> From: Armin Steinhoff [mailto:community-noreply@qnx.com]
> Sent: Monday, July 02, 2012 1:23 PM
> To: general-community@community.qnx.com
> Cc: srilakshmi; srilakshmi
> Subject: Re: PCI Express
>
> srilakshmi wrote:
>> Thank you for your reply with useful information.
>> Do you have any documents regarding pci express in QNX?
> In general, PCI Express has nothing to do with QNX.
> It is just a hardware standard ... hopfully cleanly supported by QNX
> 6.5 SP1.
>
>
>> How to generate message signaled interrupts?
> Only PCIe devices can send message signaled interrupts ... and this
> happens ONLY at HARDWARE level!!
> QNX is not involved at that low level functions.
>
>> If you had please send to me the respective documents.
>> I want to improve my knowledge regarding PCIe,
> See the attachment ... and forget QNX in that context.
>
> --Armin
>
>
>
>
>
>
> _______________________________________________
>
> General
> http://community.qnx.com/sf/go/post93964
> To cancel your subscription to this discussion, please e-mail
> general-community-unsubscribe@community.qnx.com
>
> -----
> No virus found in this message.
> Checked by AVG - www.avg.com
> Version: 2012.0.2177 / Virus Database: 2437/5105 - Release Date:
> 07/01/12
>
>
>
>
>
> _______________________________________________
>
> General
> http://community.qnx.com/sf/go/post93965
> To cancel your subscription to this discussion, please e-mail
> general-community-unsubscribe@community.qnx.com
>
_______________________________________________
General
http://community.qnx.com/sf/go/post93966
To cancel your subscription to this discussion, please e-mail general-community-unsubscribe@community.qnx.com
|
|
|
07/02/2012 8:14 AM
post93969
|
Mario Charest wrote:
> Armin,
>
> I got the say, I never expected you to show that much patience, lol!
I have a lot of "PCI customers" for QNX 6.5, so I'm well trained :)
But I hope to get rid of this special fun with QNX 6.5 SPI or SP2 ?? Or
QNX 8 ???
> Maybe he is using google translate and some stuff is getting lost in the translation?
Good idea!
At next I will respond by a translation from German to Hindi ...
creative chaos makes fun :)
--Armin
>
> Cheers,
>
> -----Message d'origine-----
> De : Armin Steinhoff [mailto:community-noreply@qnx.com]
> Envoyé : Monday, July 02, 2012 5:39 AM
> À : general-community@community.qnx.com
> Cc : srilakshmi; srilakshmi
> Objet : Re: PCI Express
>
> srilakshmi wrote:
>> It's a QNX software problem.
> IMHO ... it's not a problem with QNX software.
> It's a problem of YOUR software which seems to kill the whole system :)
>
>> After we open and compiled single program.
> What means "open" your "compiled single program" ??
> Could you post a screen dump of your terminal session and the sources of your program ??
>
>> If we want to try again to open or compile same program or any other
>> code we are getting
>> " too many session files in /tmp"
>> due to this system getting hanged. Every time we need to restart the
>> system to do something.
>> Its happening frequently.
>>
>> Would you give me the solution for this?
> Yes, change your code ...
>
> --Armin
>
>> Thanks & Regards
>> Srilakshmi
>>
>>
>>
>>
>> -----Original Message-----
>> From: Armin Steinhoff [mailto:community-noreply@qnx.com]
>> Sent: Monday, July 02, 2012 1:23 PM
>> To: general-community@community.qnx.com
>> Cc: srilakshmi; srilakshmi
>> Subject: Re: PCI Express
>>
>> srilakshmi wrote:
>>> Thank you for your reply with useful information.
>>> Do you have any documents regarding pci express in QNX?
>> In general, PCI Express has nothing to do with QNX.
>> It is just a hardware standard ... hopfully cleanly supported by QNX
>> 6.5 SP1.
>>
>>
>>> How to generate message signaled interrupts?
>> Only PCIe devices can send message signaled interrupts ... and this
>> happens ONLY at HARDWARE level!!
>> QNX is not involved at that low level functions.
>>
>>> If you had please send to me the respective documents.
>>> I want to improve my knowledge regarding PCIe,
>> See the attachment ... and forget QNX in that context.
>>
>> --Armin
>>
>>
>>
>>
>>
>>
>> _______________________________________________
>>
>> General
>> http://community.qnx.com/sf/go/post93964
>> To cancel your subscription to this discussion, please e-mail
>> general-community-unsubscribe@community.qnx.com
>>
>> -----
>> No virus found in this message.
>> Checked by AVG - www.avg.com
>> Version: 2012.0.2177 / Virus Database: 2437/5105 - Release Date:
>> 07/01/12
>>
>>
>>
>>
>>
>> _______________________________________________
>>
>> General
>> http://community.qnx.com/sf/go/post93965
>> To cancel your subscription to this discussion, please e-mail
>> general-community-unsubscribe@community.qnx.com
>>
>
>
>
>
>
> _______________________________________________
>
> General
> http://community.qnx.com/sf/go/post93966
> To cancel your subscription to this discussion, please e-mail...
|
|
|
07/02/2012 8:35 AM
post93971
|
Mario Charest wrote:
>> Armin,
>>
>> I got the say, I never expected you to show that much patience, lol!
>I have a lot of "PCI customers" for QNX 6.5, so I'm well trained :) But I hope to get rid of this special fun with QNX
6.5 SPI or SP2 ?? Or QNX 8 ???
With BB10 most probably doom maybe QSS will have more time/resources to dedicated to speeding up the release cycle,
maybe not!
PS this is my personal opinion based on information publicly available, I have no inside information. Sometimes readers
take me too seriously ;-)
|
|
|
|
printing of PCI bus informations / lspci port
|
07/02/2012 11:45 AM
post93975
|
printing of PCI bus informations / lspci port
Hi,
here is a corrected version of the port of "lcpci" and an "example"
program based on the ported "pciutils" of Linux.
The first version had a byte ordering bug ...
Here some outputs.
dump of the bus structure:
lspci -tv
-[0000:00]-+-00.0 Intel Corporation 82945G/GZ/P/PL Memory Controller Hub
+-02.0 Intel Corporation 82945G/GZ Integrated Graphics
Controller
+-1b.0 Intel Corporation N10/ICH 7 Family High Definition
Audio Controller
+-1c.0-[01]--
+-1c.1-[02]----00.0 Realtek Semiconductor Co., Ltd.
RTL8111/8168B PCI Express Gigabit Ethernet controller
+-1d.0 Intel Corporation N10/ICH 7 Family USB UHCI
Controller #1
+-1d.1 Intel Corporation N10/ICH 7 Family USB UHCI
Controller #2
+-1d.2 Intel Corporation N10/ICH 7 Family USB UHCI
Controller #3
+-1d.3 Intel Corporation N10/ICH 7 Family USB UHCI
Controller #4
+-1d.7 Intel Corporation N10/ICH 7 Family USB2 EHCI Controller
+-1e.0-[03]--+-00.0 SHF Communication Technologies AG
Ethernet Powerlink Managing Node 01
| \-01.0 Siemens Nixdorf AG Eicon Diva 2.02
compatible passive ISDN card
+-1f.0 Intel Corporation 82801GB/GR (ICH7 Family) LPC
Interface Bridge
+-1f.1 Intel Corporation 82801G (ICH7 Family) IDE Controller
+-1f.2 Intel Corporation N10/ICH7 Family SATA Controller
[IDE mode]
\-1f.3 Intel Corporation N10/ICH 7 Family SMBus Controller
# output of the example program
0000:00:1f.3 vendor=8086 device=27da class=0c05 irq=11 (pin 2) base0=0
(N10/ICH 7 Family SMBus Controller)
0000:00:1f.2 vendor=8086 device=27c0 class=0101 irq=11 (pin 2)
base0=d401 (N10/ICH7 Family SATA Controller [IDE mode])
0000:00:1f.1 vendor=8086 device=27df class=0101 irq=0 (pin 1) base0=1
(82801G (ICH7 Family) IDE Controller)
0000:00:1f.0 vendor=8086 device=27b8 class=0601 irq=0 (pin 0) base0=0
(82801GB/GR (ICH7 Family) LPC Interface Bridge)
0000:03:01.0 vendor=110a device=2104 class=0280 irq=11 (pin 1)
base0=d1200000 (Eicon Diva 2.02 compatible passive ISDN card)
0000:03:00.0 vendor=0eac device=0008 class=0280 irq=5 (pin 1) base0=a001
(Ethernet Powerlink Managing Node 01)
0000:00:1e.0 vendor=8086 device=244e class=0604 irq=255 (pin 0) base0=0
(82801 PCI Bridge)
0000:00:1d.7 vendor=8086 device=27cc class=0c03 irq=9 (pin 1)
base0=d14c4000 (N10/ICH 7 Family USB2 EHCI Controller)
0000:00:1d.3 vendor=8086 device=27cb class=0c03 irq=3 (pin 4) base0=0
(N10/ICH 7 Family USB UHCI Controller #4)
0000:00:1d.2 vendor=8086 device=27ca class=0c03 irq=6 (pin 3) base0=0
(N10/ICH 7 Family USB UHCI Controller #3)
0000:00:1d.1 vendor=8086 device=27c9 class=0c03 irq=11 (pin 2) base0=0
(N10/ICH 7 Family USB UHCI Controller #2)
0000:00:1d.0 vendor=8086 device=27c8 class=0c03 irq=9 (pin 1) base0=0
(N10/ICH 7 Family USB UHCI Controller #1)
0000:02:00.0 vendor=10ec device=8168 class=0200 irq=10 (pin 1)
base0=9001 (RTL8111/8168B PCI Express Gigabit Ethernet controller)
0000:00:1c.1 vendor=8086 device=27d2 class=0604 irq=10 (pin 2) base0=0
(N10/ICH 7 Family PCI Express Port 2)
0000:00:1c.0 vendor=8086 device=27d0 class=0604 irq=3 (pin 1) base0=0
(N10/ICH 7 Family PCI Express Port 1)
0000:00:1b.0 vendor=8086 device=27d8 class=0403 irq=3 (pin 1)
base0=d14c0004 (N10/ICH 7 Family High Definition Audio Controller)
0000:00:02.0 vendor=8086 device=2772 class=0300 irq=3 (pin 1)
base0=d1400000 (82945G/GZ Integrated Graphics Controller)
0000:00:00.0 vendor=8086 device=2770 class=0600 irq=0 (pin 0) base0=0
(82945G/GZ/P/PL Memory Controller Hub)
|
|
|
07/02/2012 12:18 PM
post93976
|
Mario Charest wrote:
>
> Mario Charest wrote:
>>> Armin,
>>>
>>> I got the say, I never expected you to show that much patience, lol!
>> I have a lot of "PCI customers" for QNX 6.5, so I'm well trained :) But I hope to get rid of this special fun with
QNX 6.5 SPI or SP2 ?? Or QNX 8 ???
> With BB10 most probably doom maybe QSS will have more time/resources to dedicated to speeding up the release cycle,
maybe not!
Well ... RIM should build the right hardware compatible to QNX .... CARS :)
--Armin
>
> PS this is my personal opinion based on information publicly available, I have no inside information. Sometimes
readers take me too seriously ;-)
>
>
>
>
>
> _______________________________________________
>
> General
> http://community.qnx.com/sf/go/post93971
> To cancel your subscription to this discussion, please e-mail general-community-unsubscribe@community.qnx.com
|
|
|
07/04/2012 5:58 AM
post94006
|
I got some problem...
When I am invoking Xilinx board through Intel Q57 Motherboard's PCIe slot
I am getting the output of pci -v command is
BAR0,BAR1,BAR2 are disabled, Interrupt connection is no connection
When I am invoking same Xilinx board through Advantech Intel Motherboard's
PCIe slot
I am getting the output of pci -v command is
BAR0,BAR1,BAR2 are enabled, Interrupt connection = 10.
Is their any problem with Advantech Motherboard or we need to do something
at this Motherboard?
Thanks & regards
Srilakshmi
-----Original Message-----
From: Armin Steinhoff [mailto:community-noreply@qnx.com]
Sent: Monday, July 02, 2012 9:44 PM
To: general-community@community.qnx.com
Cc: Mario Charest; Mario Charest
Subject: RE: PCI Express
Mario Charest wrote:
>
> Mario Charest wrote:
>>> Armin,
>>>
>>> I got the say, I never expected you to show that much patience, lol!
>> I have a lot of "PCI customers" for QNX 6.5, so I'm well trained :) But I
hope to get rid of this special fun with QNX 6.5 SPI or SP2 ?? Or QNX 8 ???
> With BB10 most probably doom maybe QSS will have more time/resources to
dedicated to speeding up the release cycle, maybe not!
Well ... RIM should build the right hardware compatible to QNX .... CARS :)
--Armin
>
> PS this is my personal opinion based on information publicly available, I
have no inside information. Sometimes readers take me too seriously ;-)
>
>
>
>
>
> _______________________________________________
>
> General
> http://community.qnx.com/sf/go/post93971
> To cancel your subscription to this discussion, please e-mail
general-community-unsubscribe@community.qnx.com
_______________________________________________
General
http://community.qnx.com/sf/go/post93976
To cancel your subscription to this discussion, please e-mail
general-community-unsubscribe@community.qnx.com
-----
No virus found in this message.
Checked by AVG - www.avg.com
Version: 2012.0.2177 / Virus Database: 2437/5105 - Release Date: 07/01/12
|
|
|
07/04/2012 7:30 AM
post94007
|
srilakshmi,
QNX 6.25 seems to have some problems with the PCI bus of the Intel Q57
Motherboard.
Please don't use the APIC/MSI mode of QNX 6.5 or at best go back to QNX
6.4.1
--Armin
srilakshmi wrote:
> I got some problem...
>
> When I am invoking Xilinx board through Intel Q57 Motherboard's PCIe slot
> I am getting the output of pci -v command is
> BAR0,BAR1,BAR2 are disabled, Interrupt connection is no connection
>
> When I am invoking same Xilinx board through Advantech Intel Motherboard's
> PCIe slot
> I am getting the output of pci -v command is
> BAR0,BAR1,BAR2 are enabled, Interrupt connection = 10.
>
> Is their any problem with Advantech Motherboard or we need to do something
> at this Motherboard?
>
> Thanks & regards
> Srilakshmi
>
>
> -----Original Message-----
> From: Armin Steinhoff [mailto:community-noreply@qnx.com]
> Sent: Monday, July 02, 2012 9:44 PM
> To: general-community@community.qnx.com
> Cc: Mario Charest; Mario Charest
> Subject: RE: PCI Express
>
> Mario Charest wrote:
>> Mario Charest wrote:
>>>> Armin,
>>>>
>>>> I got the say, I never expected you to show that much patience, lol!
>>> I have a lot of "PCI customers" for QNX 6.5, so I'm well trained :) But I
> hope to get rid of this special fun with QNX 6.5 SPI or SP2 ?? Or QNX 8 ???
>> With BB10 most probably doom maybe QSS will have more time/resources to
> dedicated to speeding up the release cycle, maybe not!
>
> Well ... RIM should build the right hardware compatible to QNX .... CARS :)
>
> --Armin
>
>> PS this is my personal opinion based on information publicly available, I
> have no inside information. Sometimes readers take me too seriously ;-)
>>
>>
>>
>>
>> _______________________________________________
>>
>> General
>> http://community.qnx.com/sf/go/post93971
>> To cancel your subscription to this discussion, please e-mail
> general-community-unsubscribe@community.qnx.com
>
>
>
>
>
>
> _______________________________________________
>
> General
> http://community.qnx.com/sf/go/post93976
> To cancel your subscription to this discussion, please e-mail
> general-community-unsubscribe@community.qnx.com
>
> -----
> No virus found in this message.
> Checked by AVG - www.avg.com
> Version: 2012.0.2177 / Virus Database: 2437/5105 - Release Date: 07/01/12
>
>
>
>
>
> _______________________________________________
>
> General
> http://community.qnx.com/sf/go/post94006
> To cancel your subscription to this discussion, please e-mail general-community-unsubscribe@community.qnx.com
>
|
|
|
07/04/2012 7:58 AM
post94010
|
Sorry I sent in opposite way
Actually,
When I am invoking Xilinx board through Advantech Motherboard's PCIe slot
I am getting the output of pci -v command is
BAR0,BAR1,BAR2 are disabled, Interrupt connection is no connection
When I am invoking same Xilinx board through Intel Q57 Motherboard's
PCIe slot
I am getting the output of pci -v command is
BAR0,BAR1,BAR2 are enabled, Interrupt connection = 10.
Is their any problem with Advantech Motherboard or we need to do something
at this Motherboard?
Thanks & Regards
Srilakshmi
-----Original Message-----
From: Armin Steinhoff [mailto:community-noreply@qnx.com]
Sent: Wednesday, July 04, 2012 4:50 PM
To: general-community@community.qnx.com
Cc: srilakshmi; srilakshmi
Subject: Re: PCI Express
srilakshmi,
QNX 6.25 seems to have some problems with the PCI bus of the Intel Q57
Motherboard.
Please don't use the APIC/MSI mode of QNX 6.5 or at best go back to QNX
6.4.1
--Armin
srilakshmi wrote:
> I got some problem...
>
> When I am invoking Xilinx board through Intel Q57 Motherboard's PCIe slot
> I am getting the output of pci -v command is
> BAR0,BAR1,BAR2 are disabled, Interrupt connection is no connection
>
> When I am invoking same Xilinx board through Advantech Intel Motherboard's
> PCIe slot
> I am getting the output of pci -v command is
> BAR0,BAR1,BAR2 are enabled, Interrupt connection = 10.
>
> Is their any problem with Advantech Motherboard or we need to do something
> at this Motherboard?
>
> Thanks & regards
> Srilakshmi
>
>
> -----Original Message-----
> From: Armin Steinhoff [mailto:community-noreply@qnx.com]
> Sent: Monday, July 02, 2012 9:44 PM
> To: general-community@community.qnx.com
> Cc: Mario Charest; Mario Charest
> Subject: RE: PCI Express
>
> Mario Charest wrote:
>> Mario Charest wrote:
>>>> Armin,
>>>>
>>>> I got the say, I never expected you to show that much patience, lol!
>>> I have a lot of "PCI customers" for QNX 6.5, so I'm well trained :) But
I
> hope to get rid of this special fun with QNX 6.5 SPI or SP2 ?? Or QNX 8
???
>> With BB10 most probably doom maybe QSS will have more time/resources to
> dedicated to speeding up the release cycle, maybe not!
>
> Well ... RIM should build the right hardware compatible to QNX .... CARS
:)
>
> --Armin
>
>> PS this is my personal opinion based on information publicly available, I
> have no inside information. Sometimes readers take me too seriously ;-)
>>
>>
>>
>>
>> _______________________________________________
>>
>> General
>> http://community.qnx.com/sf/go/post93971
>> To cancel your subscription to this discussion, please e-mail
> general-community-unsubscribe@community.qnx.com
>
>
>
>
>
>
> _______________________________________________
>
> General
> http://community.qnx.com/sf/go/post93976
> To cancel your subscription to this discussion, please e-mail
> general-community-unsubscribe@community.qnx.com
>
> -----
> No virus found in this message.
> Checked by AVG - www.avg.com
> Version: 2012.0.2177 / Virus Database: 2437/5105 - Release Date: 07/01/12
>
>
>
>
>
> _______________________________________________
>
> General
> http://community.qnx.com/sf/go/post94006
> To cancel your subscription to this discussion, please e-mail
general-community-unsubscribe@community.qnx.com
>
_______________________________________________
General
http://community.qnx.com/sf/go/post94007
To cancel your subscription to this discussion, please e-mail
general-community-unsubscribe@community.qnx.com
-----
No virus found in this message.
Checked by AVG -...
|
|
|
07/04/2012 7:47 AM
post94008
|
The BAR registers are only enabled once you run your program and perform a
pci_attach_device(). If you don't use the PCI_PERSIST flag, when your
program terminates, the BAR registers will be reset and disabled.
On 12-07-04 5:57 AM, "srilakshmi" <community-noreply@qnx.com> wrote:
>I got some problem...
>
>When I am invoking Xilinx board through Intel Q57 Motherboard's PCIe slot
>I am getting the output of pci -v command is
>BAR0,BAR1,BAR2 are disabled, Interrupt connection is no connection
>
>When I am invoking same Xilinx board through Advantech Intel Motherboard's
>PCIe slot
>I am getting the output of pci -v command is
>BAR0,BAR1,BAR2 are enabled, Interrupt connection = 10.
>
>Is their any problem with Advantech Motherboard or we need to do something
>at this Motherboard?
>
>Thanks & regards
> Srilakshmi
>
>
>-----Original Message-----
>From: Armin Steinhoff [mailto:community-noreply@qnx.com]
>Sent: Monday, July 02, 2012 9:44 PM
>To: general-community@community.qnx.com
>Cc: Mario Charest; Mario Charest
>Subject: RE: PCI Express
>
>Mario Charest wrote:
>>
>> Mario Charest wrote:
>>>> Armin,
>>>>
>>>> I got the say, I never expected you to show that much patience, lol!
>>> I have a lot of "PCI customers" for QNX 6.5, so I'm well trained :)
>>>But I
>hope to get rid of this special fun with QNX 6.5 SPI or SP2 ?? Or QNX 8
>???
>> With BB10 most probably doom maybe QSS will have more time/resources to
>dedicated to speeding up the release cycle, maybe not!
>
>Well ... RIM should build the right hardware compatible to QNX .... CARS
>:)
>
>--Armin
>
>>
>> PS this is my personal opinion based on information publicly available,
>>I
>have no inside information. Sometimes readers take me too seriously ;-)
>>
>>
>>
>>
>>
>> _______________________________________________
>>
>> General
>> http://community.qnx.com/sf/go/post93971
>> To cancel your subscription to this discussion, please e-mail
>general-community-unsubscribe@community.qnx.com
>
>
>
>
>
>
>_______________________________________________
>
>General
>http://community.qnx.com/sf/go/post93976
>To cancel your subscription to this discussion, please e-mail
>general-community-unsubscribe@community.qnx.com
>
>-----
>No virus found in this message.
>Checked by AVG - www.avg.com
>Version: 2012.0.2177 / Virus Database: 2437/5105 - Release Date: 07/01/12
>
>
>
>
>
>_______________________________________________
>
>General
>http://community.qnx.com/sf/go/post94006
>To cancel your subscription to this discussion, please e-mail
>general-community-unsubscribe@community.qnx.com
|
|
|
07/04/2012 7:48 AM
post94011
|
Hugh Brown wrote:
> The BAR registers are only enabled once you run your program and perform a
> pci_attach_device(). If you don't use the PCI_PERSIST flag, when your
> program terminates, the BAR registers will be reset and disabled.
... and this is new with QNX 6.5 ??
Regards
--Armin
>
>
>
>
> On 12-07-04 5:57 AM, "srilakshmi" <community-noreply@qnx.com> wrote:
>
>> I got some problem...
>>
>> When I am invoking Xilinx board through Intel Q57 Motherboard's PCIe slot
>> I am getting the output of pci -v command is
>> BAR0,BAR1,BAR2 are disabled, Interrupt connection is no connection
>>
>> When I am invoking same Xilinx board through Advantech Intel Motherboard's
>> PCIe slot
>> I am getting the output of pci -v command is
>> BAR0,BAR1,BAR2 are enabled, Interrupt connection = 10.
>>
>> Is their any problem with Advantech Motherboard or we need to do something
>> at this Motherboard?
>>
>> Thanks & regards
>> Srilakshmi
>>
>>
>> -----Original Message-----
>> From: Armin Steinhoff [mailto:community-noreply@qnx.com]
>> Sent: Monday, July 02, 2012 9:44 PM
>> To: general-community@community.qnx.com
>> Cc: Mario Charest; Mario Charest
>> Subject: RE: PCI Express
>>
>> Mario Charest wrote:
>>> Mario Charest wrote:
>>>>> Armin,
>>>>>
>>>>> I got the say, I never expected you to show that much patience, lol!
>>>> I have a lot of "PCI customers" for QNX 6.5, so I'm well trained :)
>>>> But I
>> hope to get rid of this special fun with QNX 6.5 SPI or SP2 ?? Or QNX 8
>> ???
>>> With BB10 most probably doom maybe QSS will have more time/resources to
>> dedicated to speeding up the release cycle, maybe not!
>>
>> Well ... RIM should build the right hardware compatible to QNX .... CARS
>> :)
>>
>> --Armin
>>
>>> PS this is my personal opinion based on information publicly available,
>>> I
>> have no inside information. Sometimes readers take me too seriously ;-)
>>>
>>>
>>>
>>>
>>> _______________________________________________
>>>
>>> General
>>> http://community.qnx.com/sf/go/post93971
>>> To cancel your subscription to this discussion, please e-mail
>> general-community-unsubscribe@community.qnx.com
>>
>>
>>
>>
>>
>>
>> _______________________________________________
>>
>> General
>> http://community.qnx.com/sf/go/post93976
>> To cancel your subscription to this discussion, please e-mail
>> general-community-unsubscribe@community.qnx.com
>>
>> -----
>> No virus found in this message.
>> Checked by AVG - www.avg.com
>> Version: 2012.0.2177 / Virus Database: 2437/5105 - Release Date: 07/01/12
>>
>>
>>
>>
>>
>> _______________________________________________
>>
>> General
>> http://community.qnx.com/sf/go/post94006
>> To cancel your subscription to this discussion, please e-mail
>> general-community-unsubscribe@community.qnx.com
>
>
>
>
> _______________________________________________
>
> General
> http://community.qnx.com/sf/go/post94008
> To cancel your subscription to this discussion, please e-mail general-community-unsubscribe@community.qnx.com
>
|
|
|
07/04/2012 7:57 AM
post94012
|
No, it has always been like that if a device is not initialized by the
BIOS.
On 12-07-04 7:51 AM, "Armin Steinhoff" <community-noreply@qnx.com> wrote:
>Hugh Brown wrote:
>> The BAR registers are only enabled once you run your program and
>>perform a
>> pci_attach_device(). If you don't use the PCI_PERSIST flag, when your
>> program terminates, the BAR registers will be reset and disabled.
>
>... and this is new with QNX 6.5 ??
>
>Regards
>
>--Armin
>
>>
>>
>>
>>
>> On 12-07-04 5:57 AM, "srilakshmi" <community-noreply@qnx.com> wrote:
>>
>>> I got some problem...
>>>
>>> When I am invoking Xilinx board through Intel Q57 Motherboard's PCIe
>>>slot
>>> I am getting the output of pci -v command is
>>> BAR0,BAR1,BAR2 are disabled, Interrupt connection is no connection
>>>
>>> When I am invoking same Xilinx board through Advantech Intel
>>>Motherboard's
>>> PCIe slot
>>> I am getting the output of pci -v command is
>>> BAR0,BAR1,BAR2 are enabled, Interrupt connection = 10.
>>>
>>> Is their any problem with Advantech Motherboard or we need to do
>>>something
>>> at this Motherboard?
>>>
>>> Thanks & regards
>>> Srilakshmi
>>>
>>>
>>> -----Original Message-----
>>> From: Armin Steinhoff [mailto:community-noreply@qnx.com]
>>> Sent: Monday, July 02, 2012 9:44 PM
>>> To: general-community@community.qnx.com
>>> Cc: Mario Charest; Mario Charest
>>> Subject: RE: PCI Express
>>>
>>> Mario Charest wrote:
>>>> Mario Charest wrote:
>>>>>> Armin,
>>>>>>
>>>>>> I got the say, I never expected you to show that much patience, lol!
>>>>> I have a lot of "PCI customers" for QNX 6.5, so I'm well trained :)
>>>>> But I
>>> hope to get rid of this special fun with QNX 6.5 SPI or SP2 ?? Or QNX 8
>>> ???
>>>> With BB10 most probably doom maybe QSS will have more time/resources
>>>>to
>>> dedicated to speeding up the release cycle, maybe not!
>>>
>>> Well ... RIM should build the right hardware compatible to QNX ....
>>>CARS
>>> :)
>>>
>>> --Armin
>>>
>>>> PS this is my personal opinion based on information publicly
>>>>available,
>>>> I
>>> have no inside information. Sometimes readers take me too seriously
>>>;-)
>>>>
>>>>
>>>>
>>>>
>>>> _______________________________________________
>>>>
>>>> General
>>>> http://community.qnx.com/sf/go/post93971
>>>> To cancel your subscription to this discussion, please e-mail
>>> general-community-unsubscribe@community.qnx.com
>>>
>>>
>>>
>>>
>>>
>>>
>>> _______________________________________________
>>>
>>> General
>>> http://community.qnx.com/sf/go/post93976
>>> To cancel your subscription to this discussion, please e-mail
>>> general-community-unsubscribe@community.qnx.com
>>>
>>> -----
>>> No virus found in this message.
>>> Checked by AVG - www.avg.com
>>> Version: 2012.0.2177 / Virus Database: 2437/5105 - Release Date:
>>>07/01/12
>>>
>>>
>>>
>>>
>>>
>>> _______________________________________________
>>>
>>> General
>>>...
|
|
|
07/04/2012 11:42 AM
post94028
|
Hugh,
I'm missing PCI related calls like pci_enable_msi or pci_disable_msi a.s.o.
With such calls it would be possible to initialize the PCIe devices for MSI operation.
(Please see the attached HOWTO ...)
Do we have a chance to get such routines in acceptable time frame ??
Regards
--Armin
|
|
|
07/04/2012 11:54 AM
post94029
|
Armin,
These functions are part of the pci_attach_device() function call. In the
flags section you either add PCI_USE_MSI or PCI_USE_MSIX depending on
which interrupt type you want to use. If you use these flags and the
device doesn't support MSI or MSIX, the PCI server will default to IRQ
interrupts.
Hugh.
--
Hugh Brown
QNX Software Systems Limited
1001 Farrar Rd.,
Ottawa. ON. K2K 0B3.
Telephone: 613-591-0931
On 12-07-04 11:42 AM, "Armin Steinhoff" <community-noreply@qnx.com> wrote:
>Hugh,
>
>I'm missing PCI related calls like pci_enable_msi or pci_disable_msi
>a.s.o.
>
>With such calls it would be possible to initialize the PCIe devices for
>MSI operation.
>(Please see the attached HOWTO ...)
>
>Do we have a chance to get such routines in acceptable time frame ??
>
>Regards
>
>--Armin
>
>
>
>
>_______________________________________________
>
>General
>http://community.qnx.com/sf/go/post94028
>To cancel your subscription to this discussion, please e-mail
>general-community-unsubscribe@community.qnx.com
|
|
|
07/04/2012 11:57 AM
post94030
|
Hugh,
OK ... but the OS must set the capabilies and the MSI-IRQ number for the
PCIe devices.
IMHO ... that's also not done by SP1.
--Armin
Hugh Brown wrote:
> Armin,
>
> These functions are part of the pci_attach_device() function call. In the
> flags section you either add PCI_USE_MSI or PCI_USE_MSIX depending on
> which interrupt type you want to use. If you use these flags and the
> device doesn't support MSI or MSIX, the PCI server will default to IRQ
> interrupts.
>
> Hugh.
>
|
|
|
07/04/2012 12:30 PM
post94031
|
The PCI server enables either the MSI or MSIX capability depending on
which is selected and also assigns MSI/X IRQ numbers to the device. Is
this what you are talking about?
--
Hugh Brown
QNX Software Systems Limited
1001 Farrar Rd.,
Ottawa. ON. K2K 0B3.
Telephone: 613-591-0931
On 12-07-04 12:00 PM, "Armin Steinhoff" <community-noreply@qnx.com> wrote:
>
>Hugh,
>
>OK ... but the OS must set the capabilies and the MSI-IRQ number for the
>PCIe devices.
>IMHO ... that's also not done by SP1.
>
>--Armin
>
>Hugh Brown wrote:
>> Armin,
>>
>> These functions are part of the pci_attach_device() function call. In
>>the
>> flags section you either add PCI_USE_MSI or PCI_USE_MSIX depending on
>> which interrupt type you want to use. If you use these flags and the
>> device doesn't support MSI or MSIX, the PCI server will default to IRQ
>> interrupts.
>>
>> Hugh.
>>
>
>
>
>
>
>
>_______________________________________________
>
>General
>http://community.qnx.com/sf/go/post94030
>To cancel your subscription to this discussion, please e-mail
>general-community-unsubscribe@community.qnx.com
|
|
|
07/04/2012 2:55 PM
post94033
|
Hugh Brown wrote:
> The PCI server enables either the MSI or MSIX capability depending on
> which is selected and also assigns MSI/X IRQ numbers to the device. Is
> this what you are talking about?
>
Yes and No.
From the example provided by the pci_attach_device documentation:
if (pci_read_config8 (bus, devfn, cap_ptr, 1, &cap)) <<<--- that means
the OS must set the capabilities before
<<<--- but in the dumps of pci or lspci I saw
<<<--- never entries of the MSI capabilities of PCIe devices
return (-1);
if (cap == PCI_CAP_MSI)
The assigned IRQ seems alway connected to an INTx line ... which is the
default non MSI mapping.
Regards
--Armin
|
|
|
07/04/2012 3:13 PM
post94034
|
If you run 'pci -v' you will see all of the capabilities for all of the devices. The MSI or MSIX interrupt is only
assigned once a pci_attach_device() has been performed, so if there is no driver running against a MSI or MSIX capable
device, you will see the standard IRQ interrupt. See the attached pci.txt file where the gigabit Ethernet device has
been assigned MSIX interrupts.
--
Hugh Brown
QNX Software Systems Limited
1001 Farrar Rd.,
Ottawa. ON. K2K 0B3.
Telephone: 613-591-0931
From: Armin Steinhoff <community-noreply@qnx.com<mailto:community-noreply@qnx.com>>
Reply-To: "general-community@community.qnx.com<mailto:general-community@community.qnx.com>" <general-community@
community.qnx.com<mailto:general-community@community.qnx.com>>
Date: Wednesday, 4 July, 2012 2:33 PM
To: "general-community@community.qnx.com<mailto:general-community@community.qnx.com>" <general-community@community.
qnx.com<mailto:general-community@community.qnx.com>>
Cc: Info System - IS Notifications <is-notifications@qnx.com<mailto:is-notifications@qnx.com>>, Info System - IS
Notifications <is-notifications@qnx.com<mailto:is-notifications@qnx.com>>, Info System - IS Notifications <is-
notifications@qnx.com<mailto:is-notifications@qnx.com>>, Info System - IS Notifications <is-notifications@qnx.com<mailto
:is-notifications@qnx.com>>
Subject: Re: PCI Express
Hugh Brown wrote:
The PCI server enables either the MSI or MSIX capability depending on
which is selected and also assigns MSI/X IRQ numbers to the device. Is
this what you are talking about?
Yes and No.
From the example provided by the pci_attach_device documentation:
if (pci_read_config8 (bus, devfn, cap_ptr, 1, &cap)) <<<--- that means the OS must set the capabilities before
<<<--- but in the dumps of pci or lspci
I saw
<<<--- never entries of the MSI
capabilities of PCIe devices
return (-1);
if (cap == PCI_CAP_MSI)
The assigned IRQ seems alway connected to an INTx line ... which is the default non MSI mapping.
Regards
--Armin
|
|
|
07/04/2012 6:42 PM
post94036
|
Hugh,
I have hier a PCI Express board and there are not the MSI capability set:
Class = Unknown (Unknown)
Vendor ID = 10b5h, PLX Technology, Inc.
Device ID = 86e1h, Unknown Unknown
PCI index = 0h
Class Codes = ff0000h
Revision ID = ach
Bus number = 9
Device number = 4
Function num = 0
Status Reg = 2b0h
Command Reg = 17h
I/O space access enabled
Memory space access enabled
Bus Master enabled
Special Cycle operations ignored
Memory Write and Invalidate enabled
Palette Snooping disabled
Parity Error Response disabled
Data/Address stepping disabled
SERR# driver disabled
Fast back-to-back transactions to different agents disabled
PCI INTx enabled
Header type = 0h Single-function
BIST = 0h Build-in-self-test not supported
Latency Timer = 20h
Cache Line Size= 10h un-cacheable
BAR - 0 [Mem] = 55480000h 32bit length 512 enabled
BAR - 1 [I/O] = 3000h length 256 enabled
BAR - 2 [Mem] = 55400000h 32bit length 524288 enabled
Subsystem Vendor ID = 14a0h
Subsystem ID = 2bh
Max Lat = 0ns
Min Gnt = 0ns
PCI Int Pin = INT A
Interrupt line = 18
CPU Interrupt = 12h
Capabilities Pointer = 40h
Capability ID = 1h - Power Management
Capabilities = 0h - 0h
Capability ID = 6h - CompactPCI Hot Swap <<<- it isn't a
CompactPCI board and I'm missing the capability 5h !
Capabilities = 0h - 3h
Capability ID = 3h - VPD
Capabilities = 0h - 0h
Device Dependent Registers:
0x040: 0148 0000 0000 0000 064c 0000 0300 0000
0x050: 0000 0000 0000 0000 0000 0000 0000 0000
...
0x0f0: 0000 0000 0000 0000 0000 0000 0000 0000
pci_attach_device returns also a false default IRQ back !
Regards
--Armin
Hugh Brown wrote:
> If you run 'pci -v' you will see all of the capabilities for all of
> the devices. The MSI or MSIX interrupt is only assigned once a
> pci_attach_device() has been performed, so if there is no driver
> running against a MSI or MSIX capable device, you will see the
> standard IRQ interrupt. See the attached pci.txt file where the
> gigabit Ethernet device has been assigned MSIX interrupts.
>
> --
> Hugh Brown
> QNX Software Systems Limited
> 1001 Farrar Rd.,
> Ottawa. ON. K2K 0B3.
> Telephone: 613-591-0931
>
>
>
> From: Armin Steinhoff <community-noreply@qnx.com
> <mailto:community-noreply@qnx.com>>
> Reply-To: "general-community@community.qnx.com
> <mailto:general-community@community.qnx.com>"
> <general-community@community.qnx.com
> <mailto:general-community@community.qnx.com>>
> Date: Wednesday, 4 July, 2012 2:33 PM
> To: "general-community@community.qnx.com
> <mailto:general-community@community.qnx.com>"
> <general-community@community.qnx.com
> <mailto:general-community@community.qnx.com>>
> Cc: Info System - IS Notifications <is-notifications@qnx.com
> <mailto:is-notifications@qnx.com>>, Info System - IS Notifications
> <is-notifications@qnx.com <mailto:is-notifications@qnx.com>>, Info
> System - IS Notifications <is-notifications@qnx.com
> <mailto:is-notifications@qnx.com>>, Info System - IS Notifications
> <is-notifications@qnx.com <mailto:is-notifications@qnx.com>>
> Subject: Re: PCI Express
>
> Hugh Brown wrote:
>> The PCI server enables either the MSI or MSIX capability depending on
>> which is selected and also assigns MSI/X IRQ numbers to the device. Is
>> this what you are talking about?
>>
> Yes and No.
> >From the example provided by the pci_attach_device documentation:
>
> if (pci_read_config8 (bus, devfn, cap_ptr, 1, &cap)) <<<--- that means
> the OS must set the...
View Full Message
|
|
|
07/04/2012 6:58 PM
post94037
|
Hugh,
I have hier the same PCI Express board placed in an other slot. There
are not the MSI capabilitie set,
but a MSI interrupt of 18 has been assigned. The crazy point is: the
board is working in default mode with that IRQ!
09:04.0 Unassigned class [ff00]: PLX Technology, Inc. Device 86e1 (rev ac)
Subsystem: SOFTING GmBH Device 002b
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr-
Stepping- SERR- FastB2B- DisINTx-
Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 32, Cache Line Size: 64 bytes
Interrupt: pin A routed to *IRQ 18*
Region 0: Memory at 55480000 (32-bit, non-prefetchable)
Region 1: I/O ports at 3000
Region 2: Memory at 55400000 (32-bit, non-prefetchable)
Capabilities: [40] Power Management version 0 *<<<<=== no MSI caps !*
Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA
PME(D0-,D1-,D2-,D3hot-,D3cold-)
Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
Capabilities: [48] CompactPCI hot-swap <?> *<<<=== wrong!*
Capabilities: [4c] Vital Product Data
Not readable
00: b5 10 e1 86 17 00 b0 02 ac 00 00 ff 10 20 00 00 <<< dump of the
config space
10: 00 00 48 55 01 30 00 00 00 00 40 55 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 a0 14 2b 00
30: 00 00 00 00 40 00 00 00 00 00 00 00 *12* 01 00 00
Regards
--Armin
Hugh Brown wrote:
> If you run 'pci -v' you will see all of the capabilities for all of
> the devices. The MSI or MSIX interrupt is only assigned once a
> pci_attach_device() has been performed, so if there is no driver
> running against a MSI or MSIX capable device, you will see the
> standard IRQ interrupt. See the attached pci.txt file where the
> gigabit Ethernet device has been assigned MSIX interrupts.
>
> --
> Hugh Brown
> QNX Software Systems Limited
> 1001 Farrar Rd.,
> Ottawa. ON. K2K 0B3.
> Telephone: 613-591-0931
>
>
>
> From: Armin Steinhoff <community-noreply@qnx.com
> <mailto:community-noreply@qnx.com>>
> Reply-To: "general-community@community.qnx.com
> <mailto:general-community@community.qnx.com>"
> <general-community@community.qnx.com
> <mailto:general-community@community.qnx.com>>
> Date: Wednesday, 4 July, 2012 2:33 PM
> To: "general-community@community.qnx.com
> <mailto:general-community@community.qnx.com>"
> <general-community@community.qnx.com
> <mailto:general-community@community.qnx.com>>
> Cc: Info System - IS Notifications <is-notifications@qnx.com
> <mailto:is-notifications@qnx.com>>, Info System - IS Notifications
> <is-notifications@qnx.com <mailto:is-notifications@qnx.com>>, Info
> System - IS Notifications <is-notifications@qnx.com
> <mailto:is-notifications@qnx.com>>, Info System - IS Notifications
> <is-notifications@qnx.com <mailto:is-notifications@qnx.com>>
> Subject: Re: PCI Express
>
> Hugh Brown wrote:
>> The PCI server enables either the MSI or MSIX capability depending on
>> which is selected and also assigns MSI/X IRQ numbers to the device. Is
>> this what you are talking about?
>>
> Yes and No.
> >From the example provided by the pci_attach_device documentation:
>
> if (pci_read_config8 (bus, devfn, cap_ptr, 1, &cap)) <<<--- that means
> the OS must set the capabilities before
> <<<--- but in the dumps of pci or lspci I saw
> <<<--- never entries of the MSI capabilities of PCIe devices
> return (-1);
> if (cap == PCI_CAP_MSI)
>
> The assigned IRQ seems alway connected to an INTx line ... which is
> the default non MSI mapping.
>
>...
|
|
|
07/05/2012 7:37 AM
post94052
|
Armin,
In your previous e-mail, the device doesn't have a capability 5 as it doesn't support MSI. The capabilities structure is
a linked list, so you cannot miss a capability.
When the local APIC is enabled it gives you 8 more IRQ interrupts and we number these from 16 to 23, so the interrupt
that you see below is not an MSI interrupt, but a normal IRQ. We number MSI/X interrupts from 0x100 upwards, but the PCI
interrupt line register only contains 8 bits, so you will see the interrupt line register set to 0x00 for interrupt
0x100 and to 0x01 for interrupt 0x101 etc. The correct interrupt is sent to the driver in the interrupt attach structure
as this value is 32-bits.
Hugh.
--
Hugh Brown
QNX Software Systems Limited
1001 Farrar Rd.,
Ottawa. ON. K2K 0B3.
Telephone: 613-591-0931
From: Armin Steinhoff <community-noreply@qnx.com<mailto:community-noreply@qnx.com>>
Reply-To: "general-community@community.qnx.com<mailto:general-community@community.qnx.com>" <general-community@
community.qnx.com<mailto:general-community@community.qnx.com>>
Date: Wednesday, 4 July, 2012 6:56 PM
To: "general-community@community.qnx.com<mailto:general-community@community.qnx.com>" <general-community@community.
qnx.com<mailto:general-community@community.qnx.com>>
Cc: Info System - IS Notifications <is-notifications@qnx.com<mailto:is-notifications@qnx.com>>, Info System - IS
Notifications <is-notifications@qnx.com<mailto:is-notifications@qnx.com>>, Info System - IS Notifications <is-
notifications@qnx.com<mailto:is-notifications@qnx.com>>, Info System - IS Notifications <is-notifications@qnx.com<mailto
:is-notifications@qnx.com>>
Subject: Re: PCI Express
Hugh,
I have hier the same PCI Express board placed in an other slot. There are not the MSI capabilitie set,
but a MSI interrupt of 18 has been assigned. The crazy point is: the board is working in default mode with that IRQ!
09:04.0 Unassigned class [ff00]: PLX Technology, Inc. Device 86e1 (rev ac)
Subsystem: SOFTING GmBH Device 002b
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 32, Cache Line Size: 64 bytes
Interrupt: pin A routed to IRQ 18
Region 0: Memory at 55480000 (32-bit, non-prefetchable)
Region 1: I/O ports at 3000
Region 2: Memory at 55400000 (32-bit, non-prefetchable)
Capabilities: [40] Power Management version 0 <<<<=== no MSI caps !
Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
Capabilities: [48] CompactPCI hot-swap <?> <<<=== wrong!
Capabilities: [4c] Vital Product Data
Not readable
00: b5 10 e1 86 17 00 b0 02 ac 00 00 ff 10 20 00 00 <<< dump of the config space
10: 00 00 48 55 01 30 00 00 00 00 40 55 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 a0 14 2b 00
30: 00 00 00 00 40 00 00 00 00 00 00 00 12 01 00 00
Regards
--Armin
Hugh Brown wrote:
If you run 'pci -v' you will see all of the capabilities for all of the devices. The MSI or MSIX interrupt is only
assigned once a pci_attach_device() has been performed, so if there is no driver running against a MSI or MSIX capable
device, you will see the standard IRQ interrupt. See the attached pci.txt file where the gigabit Ethernet device has
been assigned MSIX interrupts.
--
Hugh Brown
QNX Software Systems Limited
1001 Farrar Rd.,
Ottawa. ON. K2K 0B3.
Telephone: 613-591-0931
From: Armin Steinhoff <community-noreply@qnx.com<mailto:community-noreply@qnx.com>>
Reply-To: "general-community@community.qnx.com<mailto:general-community@community.qnx.com>"...
View Full Message
|
|
|
07/05/2012 8:12 AM
post94056
|
Hugh,
Hugh Brown wrote:
> Armin,
>
> In your previous e-mail, the device doesn't have a capability 5 as it
> doesn't support MSI.
OK ... I have to check this with the manufacturer of the board.
> The capabilities structure is a linked list, so you cannot miss a
> capability.
>
> When the local APIC is enabled it gives you 8 more IRQ interrupts and
> we number these from 16 to 23, so the interrupt that you see below is
> not an MSI interrupt, but a normal IRQ. We number MSI/X interrupts
> from 0x100 upwards, but the PCI interrupt line register only contains
> 8 bits, so you will see the interrupt line register set to 0x00 for
> interrupt 0x100 and to 0x01 for interrupt 0x101 etc. The correct
> interrupt is sent to the driver in the interrupt attach structure as
> this value is 32-bits.
Many thanks for the clarification.
Regards
--Armin
>
> Hugh.
>
> --
> Hugh Brown
> QNX Software Systems Limited
> 1001 Farrar Rd.,
> Ottawa. ON. K2K 0B3.
> Telephone: 613-591-0931
>
>
>
> From: Armin Steinhoff <community-noreply@qnx.com
> <mailto:community-noreply@qnx.com>>
> Reply-To: "general-community@community.qnx.com
> <mailto:general-community@community.qnx.com>"
> <general-community@community.qnx.com
> <mailto:general-community@community.qnx.com>>
> Date: Wednesday, 4 July, 2012 6:56 PM
> To: "general-community@community.qnx.com
> <mailto:general-community@community.qnx.com>"
> <general-community@community.qnx.com
> <mailto:general-community@community.qnx.com>>
> Cc: Info System - IS Notifications <is-notifications@qnx.com
> <mailto:is-notifications@qnx.com>>, Info System - IS Notifications
> <is-notifications@qnx.com <mailto:is-notifications@qnx.com>>, Info
> System - IS Notifications <is-notifications@qnx.com
> <mailto:is-notifications@qnx.com>>, Info System - IS Notifications
> <is-notifications@qnx.com <mailto:is-notifications@qnx.com>>
> Subject: Re: PCI Express
>
> Hugh,
>
> I have hier the same PCI Express board placed in an other slot. There
> are not the MSI capabilitie set,
> but a MSI interrupt of 18 has been assigned. The crazy point is: the
> board is working in default mode with that IRQ!
>
> 09:04.0 Unassigned class [ff00]: PLX Technology, Inc. Device 86e1 (rev ac)
> Subsystem: SOFTING GmBH Device 002b
> Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop-
> ParErr- Stepping- SERR- FastB2B- DisINTx-
> Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort-
> <TAbort- <MAbort- >SERR- <PERR- INTx-
> Latency: 32, Cache Line Size: 64 bytes
> Interrupt: pin A routed to *IRQ 18*
> Region 0: Memory at 55480000 (32-bit, non-prefetchable)
> Region 1: I/O ports at 3000
> Region 2: Memory at 55400000 (32-bit, non-prefetchable)
> Capabilities: [40] Power Management version 0 *<<<<=== no MSI caps !*
> Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA
> PME(D0-,D1-,D2-,D3hot-,D3cold-)
> Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
> Capabilities: [48] CompactPCI hot-swap <?> *<<<=== wrong!*
> Capabilities: [4c] Vital Product Data
> Not readable
> 00: b5 10 e1 86 17 00 b0 02 ac 00 00 ff 10 20 00 00 <<< dump of the
> config space
> 10: 00 00 48 55 01 30 00 00 00 00 40 55 00 00 00 00
> 20: 00 00 00 00 00 00 00 00 00 00 00 00 a0 14 2b 00
> 30: 00 00 00 00 40 00 00 00 00 00 00 00 *12* 01 00 00
>
> Regards
>
> --Armin
>
>
>
> Hugh Brown wrote:
>> If you run 'pci -v' you will see all of the capabilities for all of
>> the...
View Full Message
|
|
|
07/05/2012 12:58 AM
post94038
|
In QNX 6.5.0 pci_attach_device() don't have flags like PCI_USE_MSI or
PCI_USE_MSIX.
Thanks & Regards
Srilakshmi
-----Original Message-----
From: Hugh Brown [mailto:community-noreply@qnx.com]
Sent: Wednesday, July 04, 2012 8:59 PM
To: general-community@community.qnx.com
Subject: Re: PCI Express
Armin,
These functions are part of the pci_attach_device() function call. In the
flags section you either add PCI_USE_MSI or PCI_USE_MSIX depending on
which interrupt type you want to use. If you use these flags and the
device doesn't support MSI or MSIX, the PCI server will default to IRQ
interrupts.
Hugh.
--
Hugh Brown
QNX Software Systems Limited
1001 Farrar Rd.,
Ottawa. ON. K2K 0B3.
Telephone: 613-591-0931
On 12-07-04 11:42 AM, "Armin Steinhoff" <community-noreply@qnx.com> wrote:
>Hugh,
>
>I'm missing PCI related calls like pci_enable_msi or pci_disable_msi
>a.s.o.
>
>With such calls it would be possible to initialize the PCIe devices for
>MSI operation.
>(Please see the attached HOWTO ...)
>
>Do we have a chance to get such routines in acceptable time frame ??
>
>Regards
>
>--Armin
>
>
>
>
>_______________________________________________
>
>General
>http://community.qnx.com/sf/go/post94028
>To cancel your subscription to this discussion, please e-mail
>general-community-unsubscribe@community.qnx.com
_______________________________________________
General
http://community.qnx.com/sf/go/post94029
To cancel your subscription to this discussion, please e-mail
general-community-unsubscribe@community.qnx.com
-----
No virus found in this message.
Checked by AVG - www.avg.com
Version: 2012.0.2177 / Virus Database: 2437/5111 - Release Date: 07/04/12
|
|
|
07/05/2012 3:22 AM
post94042
|
Hi,
you have to use QNX 6.5.0 SP1
--Armin
srilakshmi wrote:
> In QNX 6.5.0 pci_attach_device() don't have flags like PCI_USE_MSI or
> PCI_USE_MSIX.
>
> Thanks & Regards
> Srilakshmi
>
>
> -----Original Message-----
> From: Hugh Brown [mailto:community-noreply@qnx.com]
> Sent: Wednesday, July 04, 2012 8:59 PM
> To: general-community@community.qnx.com
> Subject: Re: PCI Express
>
> Armin,
>
> These functions are part of the pci_attach_device() function call. In the
> flags section you either add PCI_USE_MSI or PCI_USE_MSIX depending on
> which interrupt type you want to use. If you use these flags and the
> device doesn't support MSI or MSIX, the PCI server will default to IRQ
> interrupts.
>
> Hugh.
>
|
|
|
07/05/2012 3:53 AM
post94043
|
I don't know SP1
Would you give me the information regarding SP1?
Thanks & Regards
Srilakshmi
-----Original Message-----
From: Armin Steinhoff [mailto:community-noreply@qnx.com]
Sent: Thursday, July 05, 2012 12:45 PM
To: general-community@community.qnx.com
Cc: srilakshmi; srilakshmi
Subject: Re: PCI Express
Hi,
you have to use QNX 6.5.0 SP1
--Armin
srilakshmi wrote:
> In QNX 6.5.0 pci_attach_device() don't have flags like PCI_USE_MSI or
> PCI_USE_MSIX.
>
> Thanks & Regards
> Srilakshmi
>
>
> -----Original Message-----
> From: Hugh Brown [mailto:community-noreply@qnx.com]
> Sent: Wednesday, July 04, 2012 8:59 PM
> To: general-community@community.qnx.com
> Subject: Re: PCI Express
>
> Armin,
>
> These functions are part of the pci_attach_device() function call. In the
> flags section you either add PCI_USE_MSI or PCI_USE_MSIX depending on
> which interrupt type you want to use. If you use these flags and the
> device doesn't support MSI or MSIX, the PCI server will default to IRQ
> interrupts.
>
> Hugh.
>
_______________________________________________
General
http://community.qnx.com/sf/go/post94042
To cancel your subscription to this discussion, please e-mail
general-community-unsubscribe@community.qnx.com
-----
No virus found in this message.
Checked by AVG - www.avg.com
Version: 2012.0.2177 / Virus Database: 2437/5111 - Release Date: 07/04/12
|
|
|
07/05/2012 3:54 AM
post94044
|
We are using QNX 6.5.0
Thanks & Regards
Srilakshmi
-----Original Message-----
From: Armin Steinhoff [mailto:community-noreply@qnx.com]
Sent: Thursday, July 05, 2012 12:45 PM
To: general-community@community.qnx.com
Cc: srilakshmi; srilakshmi
Subject: Re: PCI Express
Hi,
you have to use QNX 6.5.0 SP1
--Armin
srilakshmi wrote:
> In QNX 6.5.0 pci_attach_device() don't have flags like PCI_USE_MSI or
> PCI_USE_MSIX.
>
> Thanks & Regards
> Srilakshmi
>
>
> -----Original Message-----
> From: Hugh Brown [mailto:community-noreply@qnx.com]
> Sent: Wednesday, July 04, 2012 8:59 PM
> To: general-community@community.qnx.com
> Subject: Re: PCI Express
>
> Armin,
>
> These functions are part of the pci_attach_device() function call. In the
> flags section you either add PCI_USE_MSI or PCI_USE_MSIX depending on
> which interrupt type you want to use. If you use these flags and the
> device doesn't support MSI or MSIX, the PCI server will default to IRQ
> interrupts.
>
> Hugh.
>
_______________________________________________
General
http://community.qnx.com/sf/go/post94042
To cancel your subscription to this discussion, please e-mail
general-community-unsubscribe@community.qnx.com
-----
No virus found in this message.
Checked by AVG - www.avg.com
Version: 2012.0.2177 / Virus Database: 2437/5111 - Release Date: 07/04/12
|
|
|
07/05/2012 5:49 AM
post94046
|
SP1 is the "Service Pack 1 of QNX 6.5.0" ... it fixes several issues.
You can download it from the QNX homepage.
Or ask your distributor for the related CDs ..
--Armin
srilakshmi wrote:
> We are using QNX 6.5.0
>
> Thanks & Regards
> Srilakshmi
>
> -----Original Message-----
> From: Armin Steinhoff [mailto:community-noreply@qnx.com]
> Sent: Thursday, July 05, 2012 12:45 PM
> To: general-community@community.qnx.com
> Cc: srilakshmi; srilakshmi
> Subject: Re: PCI Express
>
>
> Hi,
>
> you have to use QNX 6.5.0 SP1
>
> --Armin
>
>
> srilakshmi wrote:
>> In QNX 6.5.0 pci_attach_device() don't have flags like PCI_USE_MSI or
>> PCI_USE_MSIX.
>>
>> Thanks & Regards
>> Srilakshmi
>>
>>
>> -----Original Message-----
>> From: Hugh Brown [mailto:community-noreply@qnx.com]
>> Sent: Wednesday, July 04, 2012 8:59 PM
>> To: general-community@community.qnx.com
>> Subject: Re: PCI Express
>>
>> Armin,
>>
>> These functions are part of the pci_attach_device() function call. In the
>> flags section you either add PCI_USE_MSI or PCI_USE_MSIX depending on
>> which interrupt type you want to use. If you use these flags and the
>> device doesn't support MSI or MSIX, the PCI server will default to IRQ
>> interrupts.
>>
>> Hugh.
>>
>
>
>
>
>
> _______________________________________________
>
> General
> http://community.qnx.com/sf/go/post94042
> To cancel your subscription to this discussion, please e-mail
> general-community-unsubscribe@community.qnx.com
>
> -----
> No virus found in this message.
> Checked by AVG - www.avg.com
> Version: 2012.0.2177 / Virus Database: 2437/5111 - Release Date: 07/04/12
>
>
>
>
>
> _______________________________________________
>
> General
> http://community.qnx.com/sf/go/post94044
> To cancel your subscription to this discussion, please e-mail general-community-unsubscribe@community.qnx.com
>
|
|
|
07/05/2012 8:56 AM
post94060
|
Do you send me any sample code for generating MSI in QNX(to Master FPGA)?
Thanks & Regards
Srilakshmi
-----Original Message-----
From: Armin Steinhoff [mailto:community-noreply@qnx.com]
Sent: Thursday, July 05, 2012 3:00 PM
To: general-community@community.qnx.com
Cc: srilakshmi; srilakshmi
Subject: Re: PCI Express
SP1 is the "Service Pack 1 of QNX 6.5.0" ... it fixes several issues.
You can download it from the QNX homepage.
Or ask your distributor for the related CDs ..
--Armin
srilakshmi wrote:
> We are using QNX 6.5.0
>
> Thanks & Regards
> Srilakshmi
>
> -----Original Message-----
> From: Armin Steinhoff [mailto:community-noreply@qnx.com]
> Sent: Thursday, July 05, 2012 12:45 PM
> To: general-community@community.qnx.com
> Cc: srilakshmi; srilakshmi
> Subject: Re: PCI Express
>
>
> Hi,
>
> you have to use QNX 6.5.0 SP1
>
> --Armin
>
>
> srilakshmi wrote:
>> In QNX 6.5.0 pci_attach_device() don't have flags like PCI_USE_MSI or
>> PCI_USE_MSIX.
>>
>> Thanks & Regards
>> Srilakshmi
>>
>>
>> -----Original Message-----
>> From: Hugh Brown [mailto:community-noreply@qnx.com]
>> Sent: Wednesday, July 04, 2012 8:59 PM
>> To: general-community@community.qnx.com
>> Subject: Re: PCI Express
>>
>> Armin,
>>
>> These functions are part of the pci_attach_device() function call. In the
>> flags section you either add PCI_USE_MSI or PCI_USE_MSIX depending on
>> which interrupt type you want to use. If you use these flags and the
>> device doesn't support MSI or MSIX, the PCI server will default to IRQ
>> interrupts.
>>
>> Hugh.
>>
>
>
>
>
>
> _______________________________________________
>
> General
> http://community.qnx.com/sf/go/post94042
> To cancel your subscription to this discussion, please e-mail
> general-community-unsubscribe@community.qnx.com
>
> -----
> No virus found in this message.
> Checked by AVG - www.avg.com
> Version: 2012.0.2177 / Virus Database: 2437/5111 - Release Date: 07/04/12
>
>
>
>
>
> _______________________________________________
>
> General
> http://community.qnx.com/sf/go/post94044
> To cancel your subscription to this discussion, please e-mail
general-community-unsubscribe@community.qnx.com
>
_______________________________________________
General
http://community.qnx.com/sf/go/post94046
To cancel your subscription to this discussion, please e-mail
general-community-unsubscribe@community.qnx.com
-----
No virus found in this message.
Checked by AVG - www.avg.com
Version: 2012.0.2177 / Virus Database: 2437/5111 - Release Date: 07/04/12
|
|
|
07/05/2012 8:34 AM
post94061
|
You don't generate an MSI to the FPGA, the FPGA will generate interrupts
to the processor.
On 12-07-05 8:29 AM, "srilakshmi" <community-noreply@qnx.com> wrote:
>Do you send me any sample code for generating MSI in QNX(to Master FPGA)?
>
>Thanks & Regards
> Srilakshmi
>-----Original Message-----
>From: Armin Steinhoff [mailto:community-noreply@qnx.com]
>Sent: Thursday, July 05, 2012 3:00 PM
>To: general-community@community.qnx.com
>Cc: srilakshmi; srilakshmi
>Subject: Re: PCI Express
>
>
>SP1 is the "Service Pack 1 of QNX 6.5.0" ... it fixes several issues.
>You can download it from the QNX homepage.
>Or ask your distributor for the related CDs ..
>
>--Armin
>
>srilakshmi wrote:
>> We are using QNX 6.5.0
>>
>> Thanks & Regards
>> Srilakshmi
>>
>> -----Original Message-----
>> From: Armin Steinhoff [mailto:community-noreply@qnx.com]
>> Sent: Thursday, July 05, 2012 12:45 PM
>> To: general-community@community.qnx.com
>> Cc: srilakshmi; srilakshmi
>> Subject: Re: PCI Express
>>
>>
>> Hi,
>>
>> you have to use QNX 6.5.0 SP1
>>
>> --Armin
>>
>>
>> srilakshmi wrote:
>>> In QNX 6.5.0 pci_attach_device() don't have flags like PCI_USE_MSI or
>>> PCI_USE_MSIX.
>>>
>>> Thanks & Regards
>>> Srilakshmi
>>>
>>>
>>> -----Original Message-----
>>> From: Hugh Brown [mailto:community-noreply@qnx.com]
>>> Sent: Wednesday, July 04, 2012 8:59 PM
>>> To: general-community@community.qnx.com
>>> Subject: Re: PCI Express
>>>
>>> Armin,
>>>
>>> These functions are part of the pci_attach_device() function call. In
>>>the
>>> flags section you either add PCI_USE_MSI or PCI_USE_MSIX depending on
>>> which interrupt type you want to use. If you use these flags and the
>>> device doesn't support MSI or MSIX, the PCI server will default to IRQ
>>> interrupts.
>>>
>>> Hugh.
>>>
>>
>>
>>
>>
>>
>> _______________________________________________
>>
>> General
>> http://community.qnx.com/sf/go/post94042
>> To cancel your subscription to this discussion, please e-mail
>> general-community-unsubscribe@community.qnx.com
>>
>> -----
>> No virus found in this message.
>> Checked by AVG - www.avg.com
>> Version: 2012.0.2177 / Virus Database: 2437/5111 - Release Date:
>>07/04/12
>>
>>
>>
>>
>>
>> _______________________________________________
>>
>> General
>> http://community.qnx.com/sf/go/post94044
>> To cancel your subscription to this discussion, please e-mail
>general-community-unsubscribe@community.qnx.com
>>
>
>
>
>
>
>
>_______________________________________________
>
>General
>http://community.qnx.com/sf/go/post94046
>To cancel your subscription to this discussion, please e-mail
>general-community-unsubscribe@community.qnx.com
>
>-----
>No virus found in this message.
>Checked by AVG - www.avg.com
>Version: 2012.0.2177 / Virus Database: 2437/5111 - Release Date: 07/04/12
>
>
>
>
>
>_______________________________________________
>
>General
>http://community.qnx.com/sf/go/post94060
>To cancel your subscription to this discussion, please e-mail
>general-community-unsubscribe@community.qnx.com
|
|
|
07/05/2012 9:22 AM
post94067
|
Yes, you are correct FPGA will generate interrupt to the processor.
Before and after generating FPGA interrupt to the processor I need to send
some message to FPGA.
Thanks & Regards
Srilakshmi
-----Original Message-----
From: Hugh Brown [mailto:community-noreply@qnx.com]
Sent: Thursday, July 05, 2012 6:03 PM
To: general-community@community.qnx.com
Subject: Re: PCI Express
You don't generate an MSI to the FPGA, the FPGA will generate interrupts
to the processor.
On 12-07-05 8:29 AM, "srilakshmi" <community-noreply@qnx.com> wrote:
>Do you send me any sample code for generating MSI in QNX(to Master FPGA)?
>
>Thanks & Regards
> Srilakshmi
>-----Original Message-----
>From: Armin Steinhoff [mailto:community-noreply@qnx.com]
>Sent: Thursday, July 05, 2012 3:00 PM
>To: general-community@community.qnx.com
>Cc: srilakshmi; srilakshmi
>Subject: Re: PCI Express
>
>
>SP1 is the "Service Pack 1 of QNX 6.5.0" ... it fixes several issues.
>You can download it from the QNX homepage.
>Or ask your distributor for the related CDs ..
>
>--Armin
>
>srilakshmi wrote:
>> We are using QNX 6.5.0
>>
>> Thanks & Regards
>> Srilakshmi
>>
>> -----Original Message-----
>> From: Armin Steinhoff [mailto:community-noreply@qnx.com]
>> Sent: Thursday, July 05, 2012 12:45 PM
>> To: general-community@community.qnx.com
>> Cc: srilakshmi; srilakshmi
>> Subject: Re: PCI Express
>>
>>
>> Hi,
>>
>> you have to use QNX 6.5.0 SP1
>>
>> --Armin
>>
>>
>> srilakshmi wrote:
>>> In QNX 6.5.0 pci_attach_device() don't have flags like PCI_USE_MSI or
>>> PCI_USE_MSIX.
>>>
>>> Thanks & Regards
>>> Srilakshmi
>>>
>>>
>>> -----Original Message-----
>>> From: Hugh Brown [mailto:community-noreply@qnx.com]
>>> Sent: Wednesday, July 04, 2012 8:59 PM
>>> To: general-community@community.qnx.com
>>> Subject: Re: PCI Express
>>>
>>> Armin,
>>>
>>> These functions are part of the pci_attach_device() function call. In
>>>the
>>> flags section you either add PCI_USE_MSI or PCI_USE_MSIX depending on
>>> which interrupt type you want to use. If you use these flags and the
>>> device doesn't support MSI or MSIX, the PCI server will default to IRQ
>>> interrupts.
>>>
>>> Hugh.
>>>
>>
>>
>>
>>
>>
>> _______________________________________________
>>
>> General
>> http://community.qnx.com/sf/go/post94042
>> To cancel your subscription to this discussion, please e-mail
>> general-community-unsubscribe@community.qnx.com
>>
>> -----
>> No virus found in this message.
>> Checked by AVG - www.avg.com
>> Version: 2012.0.2177 / Virus Database: 2437/5111 - Release Date:
>>07/04/12
>>
>>
>>
>>
>>
>> _______________________________________________
>>
>> General
>> http://community.qnx.com/sf/go/post94044
>> To cancel your subscription to this discussion, please e-mail
>general-community-unsubscribe@community.qnx.com
>>
>
>
>
>
>
>
>_______________________________________________
>
>General
>http://community.qnx.com/sf/go/post94046
>To cancel your subscription to this discussion, please e-mail
>general-community-unsubscribe@community.qnx.com
>
>-----
>No virus found in this message.
>Checked by AVG - www.avg.com
>Version: 2012.0.2177 / Virus Database: 2437/5111 - Release Date:...
|
|
|
07/05/2012 9:45 AM
post94069
|
srilakshmi wrote:
> Yes, you are correct FPGA will generate interrupt to the processor.
> Before and after generating FPGA interrupt to the processor I need to send
> some message to FPGA.
What messages are sent over the PCIe lane is deeply embedded in the
hardware and you and the OS have no access the PCIe message protocol.
You have to map the assigned shared memories of your PCIe board into
your memory space.
The FPGA reads/and writes to these shared memory segments ... so you
have to know from which position which data the FPGA reads and where the
FPGA is placing its response into the shared memory.
But this can only be answered from your "guy behind the chip scope" ...
--Armin
BTW I'm doing also some developments with FPGAs ...
>
> Thanks & Regards
> Srilakshmi
>
> -----Original Message-----
> From: Hugh Brown [mailto:community-noreply@qnx.com]
> Sent: Thursday, July 05, 2012 6:03 PM
> To: general-community@community.qnx.com
> Subject: Re: PCI Express
>
> You don't generate an MSI to the FPGA, the FPGA will generate interrupts
> to the processor.
>
>
>
> On 12-07-05 8:29 AM, "srilakshmi" <community-noreply@qnx.com> wrote:
>
>> Do you send me any sample code for generating MSI in QNX(to Master FPGA)?
>>
>> Thanks & Regards
>> Srilakshmi
>> -----Original Message-----
>> From: Armin Steinhoff [mailto:community-noreply@qnx.com]
>> Sent: Thursday, July 05, 2012 3:00 PM
>> To: general-community@community.qnx.com
>> Cc: srilakshmi; srilakshmi
>> Subject: Re: PCI Express
>>
>>
>> SP1 is the "Service Pack 1 of QNX 6.5.0" ... it fixes several issues.
>> You can download it from the QNX homepage.
>> Or ask your distributor for the related CDs ..
>>
>> --Armin
>>
>> srilakshmi wrote:
>>> We are using QNX 6.5.0
>>>
>>> Thanks & Regards
>>> Srilakshmi
>>>
>>> -----Original Message-----
>>> From: Armin Steinhoff [mailto:community-noreply@qnx.com]
>>> Sent: Thursday, July 05, 2012 12:45 PM
>>> To: general-community@community.qnx.com
>>> Cc: srilakshmi; srilakshmi
>>> Subject: Re: PCI Express
>>>
>>>
>>> Hi,
>>>
>>> you have to use QNX 6.5.0 SP1
>>>
>>> --Armin
>>>
>>>
>>> srilakshmi wrote:
>>>> In QNX 6.5.0 pci_attach_device() don't have flags like PCI_USE_MSI or
>>>> PCI_USE_MSIX.
>>>>
>>>> Thanks & Regards
>>>> Srilakshmi
>>>>
>>>>
>>>> -----Original Message-----
>>>> From: Hugh Brown [mailto:community-noreply@qnx.com]
>>>> Sent: Wednesday, July 04, 2012 8:59 PM
>>>> To: general-community@community.qnx.com
>>>> Subject: Re: PCI Express
>>>>
>>>> Armin,
>>>>
>>>> These functions are part of the pci_attach_device() function call. In
>>>> the
>>>> flags section you either add PCI_USE_MSI or PCI_USE_MSIX depending on
>>>> which interrupt type you want to use. If you use these flags and the
>>>> device doesn't support MSI or MSIX, the PCI server will default to IRQ
>>>> interrupts.
>>>>
>>>> Hugh.
>>>>
>>>
>>>
>>>
>>>
>>> _______________________________________________
>>>
>>> General
>>> http://community.qnx.com/sf/go/post94042
>>> To cancel your subscription to this discussion, please e-mail
>>> general-community-unsubscribe@community.qnx.com
>>>
>>>...
View Full Message
|
|
|
07/05/2012 8:39 AM
post94062
|
I think you are being asked to do something that seems to be way beyond your capabilities.
Good luck.
-----Message d'origine-----
De : srilakshmi [mailto:community-noreply@qnx.com]
Envoyé : Thursday, July 05, 2012 8:30 AM
À : general-community@community.qnx.com
Objet : RE: PCI Express
Do you send me any sample code for generating MSI in QNX(to Master FPGA)?
Thanks & Regards
Srilakshmi
-----Original Message-----
From: Armin Steinhoff [mailto:community-noreply@qnx.com]
Sent: Thursday, July 05, 2012 3:00 PM
To: general-community@community.qnx.com
Cc: srilakshmi; srilakshmi
Subject: Re: PCI Express
SP1 is the "Service Pack 1 of QNX 6.5.0" ... it fixes several issues.
You can download it from the QNX homepage.
Or ask your distributor for the related CDs ..
--Armin
srilakshmi wrote:
> We are using QNX 6.5.0
>
> Thanks & Regards
> Srilakshmi
>
> -----Original Message-----
> From: Armin Steinhoff [mailto:community-noreply@qnx.com]
> Sent: Thursday, July 05, 2012 12:45 PM
> To: general-community@community.qnx.com
> Cc: srilakshmi; srilakshmi
> Subject: Re: PCI Express
>
>
> Hi,
>
> you have to use QNX 6.5.0 SP1
>
> --Armin
>
>
> srilakshmi wrote:
>> In QNX 6.5.0 pci_attach_device() don't have flags like PCI_USE_MSI or
>> PCI_USE_MSIX.
>>
>> Thanks & Regards
>> Srilakshmi
>>
>>
>> -----Original Message-----
>> From: Hugh Brown [mailto:community-noreply@qnx.com]
>> Sent: Wednesday, July 04, 2012 8:59 PM
>> To: general-community@community.qnx.com
>> Subject: Re: PCI Express
>>
>> Armin,
>>
>> These functions are part of the pci_attach_device() function call. In the
>> flags section you either add PCI_USE_MSI or PCI_USE_MSIX depending on
>> which interrupt type you want to use. If you use these flags and the
>> device doesn't support MSI or MSIX, the PCI server will default to IRQ
>> interrupts.
>>
>> Hugh.
>>
>
>
>
>
>
> _______________________________________________
>
> General
> http://community.qnx.com/sf/go/post94042
> To cancel your subscription to this discussion, please e-mail
> general-community-unsubscribe@community.qnx.com
>
> -----
> No virus found in this message.
> Checked by AVG - www.avg.com
> Version: 2012.0.2177 / Virus Database: 2437/5111 - Release Date: 07/04/12
>
>
>
>
>
> _______________________________________________
>
> General
> http://community.qnx.com/sf/go/post94044
> To cancel your subscription to this discussion, please e-mail
general-community-unsubscribe@community.qnx.com
>
_______________________________________________
General
http://community.qnx.com/sf/go/post94046
To cancel your subscription to this discussion, please e-mail
general-community-unsubscribe@community.qnx.com
-----
No virus found in this message.
Checked by AVG - www.avg.com
Version: 2012.0.2177 / Virus Database: 2437/5111 - Release Date: 07/04/12
_______________________________________________
General
http://community.qnx.com/sf/go/post94060
To cancel your subscription to this discussion, please e-mail general-community-unsubscribe@community.qnx.com
|
|
|
07/05/2012 9:34 AM
post94068
|
Yes, I don't have proper knowledge on what I am asking.
But I need to do all these things.
Through the attachment I am sending some code in that code some problem is their its not executing from
pci_attach_device function.
The code is for
I need to write 01020304 message Master FPGA then FPGA generates interrupt and do some operations then again when I sent
05060708 message FPGA disables the interrupt.
Would you please help me...
Thanks & Regards
Srilakshmi
-----Original Message-----
From: Mario Charest [mailto:community-noreply@qnx.com]
Sent: Thursday, July 05, 2012 6:06 PM
To: general-community@community.qnx.com
Subject: RE: PCI Express
I think you are being asked to do something that seems to be way beyond your capabilities.
Good luck.
-----Message d'origine-----
De : srilakshmi [mailto:community-noreply@qnx.com]
Envoyé : Thursday, July 05, 2012 8:30 AM
À : general-community@community.qnx.com
Objet : RE: PCI Express
Do you send me any sample code for generating MSI in QNX(to Master FPGA)?
Thanks & Regards
Srilakshmi
-----Original Message-----
From: Armin Steinhoff [mailto:community-noreply@qnx.com]
Sent: Thursday, July 05, 2012 3:00 PM
To: general-community@community.qnx.com
Cc: srilakshmi; srilakshmi
Subject: Re: PCI Express
SP1 is the "Service Pack 1 of QNX 6.5.0" ... it fixes several issues.
You can download it from the QNX homepage.
Or ask your distributor for the related CDs ..
--Armin
srilakshmi wrote:
> We are using QNX 6.5.0
>
> Thanks & Regards
> Srilakshmi
>
> -----Original Message-----
> From: Armin Steinhoff [mailto:community-noreply@qnx.com]
> Sent: Thursday, July 05, 2012 12:45 PM
> To: general-community@community.qnx.com
> Cc: srilakshmi; srilakshmi
> Subject: Re: PCI Express
>
>
> Hi,
>
> you have to use QNX 6.5.0 SP1
>
> --Armin
>
>
> srilakshmi wrote:
>> In QNX 6.5.0 pci_attach_device() don't have flags like PCI_USE_MSI or
>> PCI_USE_MSIX.
>>
>> Thanks & Regards
>> Srilakshmi
>>
>>
>> -----Original Message-----
>> From: Hugh Brown [mailto:community-noreply@qnx.com]
>> Sent: Wednesday, July 04, 2012 8:59 PM
>> To: general-community@community.qnx.com
>> Subject: Re: PCI Express
>>
>> Armin,
>>
>> These functions are part of the pci_attach_device() function call. In the
>> flags section you either add PCI_USE_MSI or PCI_USE_MSIX depending on
>> which interrupt type you want to use. If you use these flags and the
>> device doesn't support MSI or MSIX, the PCI server will default to IRQ
>> interrupts.
>>
>> Hugh.
>>
>
>
>
>
>
> _______________________________________________
>
> General
> http://community.qnx.com/sf/go/post94042
> To cancel your subscription to this discussion, please e-mail
> general-community-unsubscribe@community.qnx.com
>
> -----
> No virus found in this message.
> Checked by AVG - www.avg.com
> Version: 2012.0.2177 / Virus Database: 2437/5111 - Release Date: 07/04/12
>
>
>
>
>
> _______________________________________________
>
> General
> http://community.qnx.com/sf/go/post94044
> To cancel your subscription to this discussion, please e-mail
general-community-unsubscribe@community.qnx.com
>
_______________________________________________
General
http://community.qnx.com/sf/go/post94046
To cancel your subscription to this discussion, please e-mail
general-community-unsubscribe@community.qnx.com
-----
No virus found in this message.
Checked by AVG - www.avg.com
Version: 2012.0.2177 / Virus Database: 2437/5111 - Release Date: 07/04/12
_______________________________________________
General
http://community.qnx.com/sf/go/post94060
To...
View Full Message
|
|
|
07/05/2012 9:50 AM
post94070
|
Attachment ??
srilakshmi wrote:
> Yes, I don't have proper knowledge on what I am asking.
> But I need to do all these things.
> Through the attachment I am sending some code in that code some problem is their its not executing from
pci_attach_device function.
> The code is for
> I need to write 01020304 message Master FPGA then FPGA generates interrupt and do some operations then again when I
sent 05060708 message FPGA disables the interrupt.
> Would you please help me...
>
> Thanks & Regards
> Srilakshmi
>
> -----Original Message-----
> From: Mario Charest [mailto:community-noreply@qnx.com]
> Sent: Thursday, July 05, 2012 6:06 PM
> To: general-community@community.qnx.com
> Subject: RE: PCI Express
>
>
> I think you are being asked to do something that seems to be way beyond your capabilities.
> Good luck.
>
> -----Message d'origine-----
> De : srilakshmi [mailto:community-noreply@qnx.com]
> Envoyé : Thursday, July 05, 2012 8:30 AM
> À : general-community@community.qnx.com
> Objet : RE: PCI Express
>
> Do you send me any sample code for generating MSI in QNX(to Master FPGA)?
>
> Thanks & Regards
> Srilakshmi
> -----Original Message-----
> From: Armin Steinhoff [mailto:community-noreply@qnx.com]
> Sent: Thursday, July 05, 2012 3:00 PM
> To: general-community@community.qnx.com
> Cc: srilakshmi; srilakshmi
> Subject: Re: PCI Express
>
>
> SP1 is the "Service Pack 1 of QNX 6.5.0" ... it fixes several issues.
> You can download it from the QNX homepage.
> Or ask your distributor for the related CDs ..
>
> --Armin
>
> srilakshmi wrote:
>> We are using QNX 6.5.0
>>
>> Thanks & Regards
>> Srilakshmi
>>
>> -----Original Message-----
>> From: Armin Steinhoff [mailto:community-noreply@qnx.com]
>> Sent: Thursday, July 05, 2012 12:45 PM
>> To: general-community@community.qnx.com
>> Cc: srilakshmi; srilakshmi
>> Subject: Re: PCI Express
>>
>>
>> Hi,
>>
>> you have to use QNX 6.5.0 SP1
>>
>> --Armin
>>
>>
>> srilakshmi wrote:
>>> In QNX 6.5.0 pci_attach_device() don't have flags like PCI_USE_MSI or
>>> PCI_USE_MSIX.
>>>
>>> Thanks & Regards
>>> Srilakshmi
>>>
>>>
>>> -----Original Message-----
>>> From: Hugh Brown [mailto:community-noreply@qnx.com]
>>> Sent: Wednesday, July 04, 2012 8:59 PM
>>> To: general-community@community.qnx.com
>>> Subject: Re: PCI Express
>>>
>>> Armin,
>>>
>>> These functions are part of the pci_attach_device() function call. In the
>>> flags section you either add PCI_USE_MSI or PCI_USE_MSIX depending on
>>> which interrupt type you want to use. If you use these flags and the
>>> device doesn't support MSI or MSIX, the PCI server will default to IRQ
>>> interrupts.
>>>
>>> Hugh.
>>>
>>
>>
>>
>>
>> _______________________________________________
>>
>> General
>> http://community.qnx.com/sf/go/post94042
>> To cancel your subscription to this discussion, please e-mail
>> general-community-unsubscribe@community.qnx.com
>>
>> -----
>> No virus found in this message.
>> Checked by AVG - www.avg.com
>> Version: 2012.0.2177 / Virus Database: 2437/5111 - Release Date: 07/04/12
>>
>>
>>
>>
>>
>> _______________________________________________
>>
>> General
>> http://community.qnx.com/sf/go/post94044
>> To cancel your subscription to this discussion, please e-mail
>...
View Full Message
|
|
|
07/06/2012 12:55 AM
post94107
|
Yes, I don't have proper knowledge on what I am asking.
But I need to do all these things.
Through the attachment I am sending some code in that code some problem is their its not executing from
pci_attach_device function.
The code is for
I need to send(write) 01020304 message to Master FPGA then FPGA generates interrupt and do some operations then again
when I sent 05060708 message FPGA disables the interrupt.
Would you please help me...
Address location is BAR0[mem] fd7ff000h
Thanks & Regards
Srilakshmi
-----Original Message-----
From: Armin Steinhoff [mailto:community-noreply@qnx.com]
Sent: Thursday, July 05, 2012 7:01 PM
To: general-community@community.qnx.com
Cc: srilakshmi; srilakshmi
Subject: Re: PCI Express
Attachment ??
srilakshmi wrote:
> Yes, I don't have proper knowledge on what I am asking.
> But I need to do all these things.
> Through the attachment I am sending some code in that code some problem is their its not executing from
pci_attach_device function.
> The code is for
> I need to write 01020304 message Master FPGA then FPGA generates interrupt and do some operations then again when I
sent 05060708 message FPGA disables the interrupt.
> Would you please help me...
>
> Thanks & Regards
> Srilakshmi
>
> -----Original Message-----
> From: Mario Charest [mailto:community-noreply@qnx.com]
> Sent: Thursday, July 05, 2012 6:06 PM
> To: general-community@community.qnx.com
> Subject: RE: PCI Express
>
>
> I think you are being asked to do something that seems to be way beyond your capabilities.
> Good luck.
>
> -----Message d'origine-----
> De : srilakshmi [mailto:community-noreply@qnx.com]
> Envoyé : Thursday, July 05, 2012 8:30 AM
> À : general-community@community.qnx.com
> Objet : RE: PCI Express
>
> Do you send me any sample code for generating MSI in QNX(to Master FPGA)?
>
> Thanks & Regards
> Srilakshmi
> -----Original Message-----
> From: Armin Steinhoff [mailto:community-noreply@qnx.com]
> Sent: Thursday, July 05, 2012 3:00 PM
> To: general-community@community.qnx.com
> Cc: srilakshmi; srilakshmi
> Subject: Re: PCI Express
>
>
> SP1 is the "Service Pack 1 of QNX 6.5.0" ... it fixes several issues.
> You can download it from the QNX homepage.
> Or ask your distributor for the related CDs ..
>
> --Armin
>
> srilakshmi wrote:
>> We are using QNX 6.5.0
>>
>> Thanks & Regards
>> Srilakshmi
>>
>> -----Original Message-----
>> From: Armin Steinhoff [mailto:community-noreply@qnx.com]
>> Sent: Thursday, July 05, 2012 12:45 PM
>> To: general-community@community.qnx.com
>> Cc: srilakshmi; srilakshmi
>> Subject: Re: PCI Express
>>
>>
>> Hi,
>>
>> you have to use QNX 6.5.0 SP1
>>
>> --Armin
>>
>>
>> srilakshmi wrote:
>>> In QNX 6.5.0 pci_attach_device() don't have flags like PCI_USE_MSI or
>>> PCI_USE_MSIX.
>>>
>>> Thanks & Regards
>>> Srilakshmi
>>>
>>>
>>> -----Original Message-----
>>> From: Hugh Brown [mailto:community-noreply@qnx.com]
>>> Sent: Wednesday, July 04, 2012 8:59 PM
>>> To: general-community@community.qnx.com
>>> Subject: Re: PCI Express
>>>
>>> Armin,
>>>
>>> These functions are part of the pci_attach_device() function call. In the
>>> flags section you either add PCI_USE_MSI or PCI_USE_MSIX depending on
>>> which interrupt type you want to use. If you use these flags and the
>>> device doesn't support MSI or MSIX, the PCI server will default to IRQ
>>> interrupts.
>>>
>>>...
View Full Message
|
|
|
07/06/2012 2:55 AM
post94108
|
Just a question about the interrupt number used in
id=InterruptAttach(10,intr_handler,0,0,_NTO_INTR_FLAGS_PROCESS);
is this the same IRQ as reported by pinfo->irq ? Normaly you have to use
the interrupt number reported by pci_attach_device.
But there is still a bug in pci_attach_device because it returns for
unknown reasons wrong IRQ numbers.
Please check if pinfo->irq is the IRQ reported by pci -vv or lspci -vv
--Armin
srilakshmi wrote:
> Yes, I don't have proper knowledge on what I am asking.
> But I need to do all these things.
> Through the attachment I am sending some code in that code some problem is their its not executing from
pci_attach_device function.
> The code is for
> I need to send(write) 01020304 message to Master FPGA then FPGA generates interrupt and do some operations then again
when I sent 05060708 message FPGA disables the interrupt.
> Would you please help me...
> Address location is BAR0[mem] fd7ff000h
>
> Thanks & Regards
> Srilakshmi
>
> -----Original Message-----
> From: Armin Steinhoff [mailto:community-noreply@qnx.com]
> Sent: Thursday, July 05, 2012 7:01 PM
> To: general-community@community.qnx.com
> Cc: srilakshmi; srilakshmi
> Subject: Re: PCI Express
>
>
> Attachment ??
>
> srilakshmi wrote:
>> Yes, I don't have proper knowledge on what I am asking.
>> But I need to do all these things.
>> Through the attachment I am sending some code in that code some problem is their its not executing from
pci_attach_device function.
>> The code is for
>> I need to write 01020304 message Master FPGA then FPGA generates interrupt and do some operations then again when I
sent 05060708 message FPGA disables the interrupt.
>> Would you please help me...
>>
>> Thanks & Regards
>> Srilakshmi
>>
>> -----Original Message-----
>> From: Mario Charest [mailto:community-noreply@qnx.com]
>> Sent: Thursday, July 05, 2012 6:06 PM
>> To: general-community@community.qnx.com
>> Subject: RE: PCI Express
>>
>>
>> I think you are being asked to do something that seems to be way beyond your capabilities.
>> Good luck.
>>
>> -----Message d'origine-----
>> De : srilakshmi [mailto:community-noreply@qnx.com]
>> Envoyé : Thursday, July 05, 2012 8:30 AM
>> À : general-community@community.qnx.com
>> Objet : RE: PCI Express
>>
>> Do you send me any sample code for generating MSI in QNX(to Master FPGA)?
>>
>> Thanks & Regards
>> Srilakshmi
>> -----Original Message-----
>> From: Armin Steinhoff [mailto:community-noreply@qnx.com]
>> Sent: Thursday, July 05, 2012 3:00 PM
>> To: general-community@community.qnx.com
>> Cc: srilakshmi; srilakshmi
>> Subject: Re: PCI Express
>>
>>
>> SP1 is the "Service Pack 1 of QNX 6.5.0" ... it fixes several issues.
>> You can download it from the QNX homepage.
>> Or ask your distributor for the related CDs ..
>>
>> --Armin
>>
>> srilakshmi wrote:
>>> We are using QNX 6.5.0
>>>
>>> Thanks & Regards
>>> Srilakshmi
>>>
>>> -----Original Message-----
>>> From: Armin Steinhoff [mailto:community-noreply@qnx.com]
>>> Sent: Thursday, July 05, 2012 12:45 PM
>>> To: general-community@community.qnx.com
>>> Cc: srilakshmi; srilakshmi
>>> Subject: Re: PCI Express
>>>
>>>
>>> Hi,
>>>
>>> you have to use QNX 6.5.0 SP1
>>>
>>> --Armin
>>>
>>>
>>> srilakshmi wrote:
>>>> In QNX 6.5.0 pci_attach_device() don't have flags like PCI_USE_MSI...
View Full Message
|
|
|
07/06/2012 5:57 AM
post94114
|
Yes 10 is the no. reported by pinfo->irq.
Thanks & Regards
Srilakshmi
-----Original Message-----
From: Armin Steinhoff [mailto:community-noreply@qnx.com]
Sent: Friday, July 06, 2012 12:03 PM
To: general-community@community.qnx.com
Cc: srilakshmi; srilakshmi
Subject: Re: PCI Express
Just a question about the interrupt number used in
id=InterruptAttach(10,intr_handler,0,0,_NTO_INTR_FLAGS_PROCESS);
is this the same IRQ as reported by pinfo->irq ? Normaly you have to use
the interrupt number reported by pci_attach_device.
But there is still a bug in pci_attach_device because it returns for
unknown reasons wrong IRQ numbers.
Please check if pinfo->irq is the IRQ reported by pci -vv or lspci -vv
--Armin
srilakshmi wrote:
> Yes, I don't have proper knowledge on what I am asking.
> But I need to do all these things.
> Through the attachment I am sending some code in that code some problem is their its not executing from
pci_attach_device function.
> The code is for
> I need to send(write) 01020304 message to Master FPGA then FPGA generates interrupt and do some operations then again
when I sent 05060708 message FPGA disables the interrupt.
> Would you please help me...
> Address location is BAR0[mem] fd7ff000h
>
> Thanks & Regards
> Srilakshmi
>
> -----Original Message-----
> From: Armin Steinhoff [mailto:community-noreply@qnx.com]
> Sent: Thursday, July 05, 2012 7:01 PM
> To: general-community@community.qnx.com
> Cc: srilakshmi; srilakshmi
> Subject: Re: PCI Express
>
>
> Attachment ??
>
> srilakshmi wrote:
>> Yes, I don't have proper knowledge on what I am asking.
>> But I need to do all these things.
>> Through the attachment I am sending some code in that code some problem is their its not executing from
pci_attach_device function.
>> The code is for
>> I need to write 01020304 message Master FPGA then FPGA generates interrupt and do some operations then again when I
sent 05060708 message FPGA disables the interrupt.
>> Would you please help me...
>>
>> Thanks & Regards
>> Srilakshmi
>>
>> -----Original Message-----
>> From: Mario Charest [mailto:community-noreply@qnx.com]
>> Sent: Thursday, July 05, 2012 6:06 PM
>> To: general-community@community.qnx.com
>> Subject: RE: PCI Express
>>
>>
>> I think you are being asked to do something that seems to be way beyond your capabilities.
>> Good luck.
>>
>> -----Message d'origine-----
>> De : srilakshmi [mailto:community-noreply@qnx.com]
>> Envoyé : Thursday, July 05, 2012 8:30 AM
>> À : general-community@community.qnx.com
>> Objet : RE: PCI Express
>>
>> Do you send me any sample code for generating MSI in QNX(to Master FPGA)?
>>
>> Thanks & Regards
>> Srilakshmi
>> -----Original Message-----
>> From: Armin Steinhoff [mailto:community-noreply@qnx.com]
>> Sent: Thursday, July 05, 2012 3:00 PM
>> To: general-community@community.qnx.com
>> Cc: srilakshmi; srilakshmi
>> Subject: Re: PCI Express
>>
>>
>> SP1 is the "Service Pack 1 of QNX 6.5.0" ... it fixes several issues.
>> You can download it from the QNX homepage.
>> Or ask your distributor for the related CDs ..
>>
>> --Armin
>>
>> srilakshmi wrote:
>>> We are using QNX 6.5.0
>>>
>>> Thanks & Regards
>>> Srilakshmi
>>>
>>> -----Original Message-----
>>> From: Armin Steinhoff [mailto:community-noreply@qnx.com]
>>> Sent: Thursday, July 05, 2012 12:45 PM
>>> To: general-community@community.qnx.com
>>> Cc: srilakshmi; srilakshmi
>>> Subject: Re: PCI...
View Full Message
|
|
|
07/06/2012 6:47 AM
post94115
|
srilakshmi wrote:
> Yes 10 is the no. reported by pinfo->irq.
... end this is the same number reported by pci -vvv ??
--Armin
>
> Thanks & Regards
> Srilakshmi
>
> -----Original Message-----
> From: Armin Steinhoff [mailto:community-noreply@qnx.com]
> Sent: Friday, July 06, 2012 12:03 PM
> To: general-community@community.qnx.com
> Cc: srilakshmi; srilakshmi
> Subject: Re: PCI Express
>
>
> Just a question about the interrupt number used in
>
> id=InterruptAttach(10,intr_handler,0,0,_NTO_INTR_FLAGS_PROCESS);
>
> is this the same IRQ as reported by pinfo->irq ? Normaly you have to use
> the interrupt number reported by pci_attach_device.
> But there is still a bug in pci_attach_device because it returns for
> unknown reasons wrong IRQ numbers.
>
> Please check if pinfo->irq is the IRQ reported by pci -vv or lspci -vv
>
> --Armin
>
>
>
> srilakshmi wrote:
>> Yes, I don't have proper knowledge on what I am asking.
>> But I need to do all these things.
>> Through the attachment I am sending some code in that code some problem is their its not executing from
pci_attach_device function.
>> The code is for
>> I need to send(write) 01020304 message to Master FPGA then FPGA generates interrupt and do some operations then again
when I sent 05060708 message FPGA disables the interrupt.
>> Would you please help me...
>> Address location is BAR0[mem] fd7ff000h
>>
>> Thanks & Regards
>> Srilakshmi
>>
>> -----Original Message-----
>> From: Armin Steinhoff [mailto:community-noreply@qnx.com]
>> Sent: Thursday, July 05, 2012 7:01 PM
>> To: general-community@community.qnx.com
>> Cc: srilakshmi; srilakshmi
>> Subject: Re: PCI Express
>>
>>
>> Attachment ??
>>
>> srilakshmi wrote:
>>> Yes, I don't have proper knowledge on what I am asking.
>>> But I need to do all these things.
>>> Through the attachment I am sending some code in that code some problem is their its not executing from
pci_attach_device function.
>>> The code is for
>>> I need to write 01020304 message Master FPGA then FPGA generates interrupt and do some operations then again when I
sent 05060708 message FPGA disables the interrupt.
>>> Would you please help me...
>>>
>>> Thanks & Regards
>>> Srilakshmi
>>>
>>> -----Original Message-----
>>> From: Mario Charest [mailto:community-noreply@qnx.com]
>>> Sent: Thursday, July 05, 2012 6:06 PM
>>> To: general-community@community.qnx.com
>>> Subject: RE: PCI Express
>>>
>>>
>>> I think you are being asked to do something that seems to be way beyond your capabilities.
>>> Good luck.
>>>
>>> -----Message d'origine-----
>>> De : srilakshmi [mailto:community-noreply@qnx.com]
>>> Envoyé : Thursday, July 05, 2012 8:30 AM
>>> À : general-community@community.qnx.com
>>> Objet : RE: PCI Express
>>>
>>> Do you send me any sample code for generating MSI in QNX(to Master FPGA)?
>>>
>>> Thanks & Regards
>>> Srilakshmi
>>> -----Original Message-----
>>> From: Armin Steinhoff [mailto:community-noreply@qnx.com]
>>> Sent: Thursday, July 05, 2012 3:00 PM
>>> To: general-community@community.qnx.com
>>> Cc: srilakshmi; srilakshmi
>>> Subject: Re: PCI Express
>>>
>>>
>>> SP1 is the "Service Pack 1 of QNX 6.5.0" ... it fixes several issues.
>>> You can download it from the QNX homepage.
>>> Or ask your distributor for the related CDs...
View Full Message
|
|
|
07/06/2012 7:52 AM
post94116
|
Yes same no. reported by pci -vvv command also
Thanks & Regards
Srilakshmi
-----Original Message-----
From: Armin Steinhoff [mailto:community-noreply@qnx.com]
Sent: Friday, July 06, 2012 4:14 PM
To: general-community@community.qnx.com
Cc: srilakshmi; srilakshmi
Subject: Re: PCI Express
srilakshmi wrote:
> Yes 10 is the no. reported by pinfo->irq.
... end this is the same number reported by pci -vvv ??
--Armin
>
> Thanks & Regards
> Srilakshmi
>
> -----Original Message-----
> From: Armin Steinhoff [mailto:community-noreply@qnx.com]
> Sent: Friday, July 06, 2012 12:03 PM
> To: general-community@community.qnx.com
> Cc: srilakshmi; srilakshmi
> Subject: Re: PCI Express
>
>
> Just a question about the interrupt number used in
>
> id=InterruptAttach(10,intr_handler,0,0,_NTO_INTR_FLAGS_PROCESS);
>
> is this the same IRQ as reported by pinfo->irq ? Normaly you have to use
> the interrupt number reported by pci_attach_device.
> But there is still a bug in pci_attach_device because it returns for
> unknown reasons wrong IRQ numbers.
>
> Please check if pinfo->irq is the IRQ reported by pci -vv or lspci -vv
>
> --Armin
>
>
>
> srilakshmi wrote:
>> Yes, I don't have proper knowledge on what I am asking.
>> But I need to do all these things.
>> Through the attachment I am sending some code in that code some problem is their its not executing from
pci_attach_device function.
>> The code is for
>> I need to send(write) 01020304 message to Master FPGA then FPGA generates interrupt and do some operations then again
when I sent 05060708 message FPGA disables the interrupt.
>> Would you please help me...
>> Address location is BAR0[mem] fd7ff000h
>>
>> Thanks & Regards
>> Srilakshmi
>>
>> -----Original Message-----
>> From: Armin Steinhoff [mailto:community-noreply@qnx.com]
>> Sent: Thursday, July 05, 2012 7:01 PM
>> To: general-community@community.qnx.com
>> Cc: srilakshmi; srilakshmi
>> Subject: Re: PCI Express
>>
>>
>> Attachment ??
>>
>> srilakshmi wrote:
>>> Yes, I don't have proper knowledge on what I am asking.
>>> But I need to do all these things.
>>> Through the attachment I am sending some code in that code some problem is their its not executing from
pci_attach_device function.
>>> The code is for
>>> I need to write 01020304 message Master FPGA then FPGA generates interrupt and do some operations then again when I
sent 05060708 message FPGA disables the interrupt.
>>> Would you please help me...
>>>
>>> Thanks & Regards
>>> Srilakshmi
>>>
>>> -----Original Message-----
>>> From: Mario Charest [mailto:community-noreply@qnx.com]
>>> Sent: Thursday, July 05, 2012 6:06 PM
>>> To: general-community@community.qnx.com
>>> Subject: RE: PCI Express
>>>
>>>
>>> I think you are being asked to do something that seems to be way beyond your capabilities.
>>> Good luck.
>>>
>>> -----Message d'origine-----
>>> De : srilakshmi [mailto:community-noreply@qnx.com]
>>> Envoyé : Thursday, July 05, 2012 8:30 AM
>>> À : general-community@community.qnx.com
>>> Objet : RE: PCI Express
>>>
>>> Do you send me any sample code for generating MSI in QNX(to Master FPGA)?
>>>
>>> Thanks & Regards
>>> Srilakshmi
>>> -----Original Message-----
>>> From: Armin Steinhoff [mailto:community-noreply@qnx.com]
>>> Sent: Thursday, July 05, 2012 3:00 PM
>>> To:...
View Full Message
|
|
|
07/06/2012 8:50 AM
post94118
|
OK ... then it should work!
--Armin
srilakshmi wrote:
> Yes same no. reported by pci -vvv command also
> Thanks & Regards
> Srilakshmi
>
> -----Original Message-----
> From: Armin Steinhoff [mailto:community-noreply@qnx.com]
> Sent: Friday, July 06, 2012 4:14 PM
> To: general-community@community.qnx.com
> Cc: srilakshmi; srilakshmi
> Subject: Re: PCI Express
>
> srilakshmi wrote:
>> Yes 10 is the no. reported by pinfo->irq.
> ... end this is the same number reported by pci -vvv ??
>
> --Armin
>
>> Thanks & Regards
>> Srilakshmi
>>
>> -----Original Message-----
>> From: Armin Steinhoff [mailto:community-noreply@qnx.com]
>> Sent: Friday, July 06, 2012 12:03 PM
>> To: general-community@community.qnx.com
>> Cc: srilakshmi; srilakshmi
>> Subject: Re: PCI Express
>>
>>
>> Just a question about the interrupt number used in
>>
>> id=InterruptAttach(10,intr_handler,0,0,_NTO_INTR_FLAGS_PROCESS);
>>
>> is this the same IRQ as reported by pinfo->irq ? Normaly you have to use
>> the interrupt number reported by pci_attach_device.
>> But there is still a bug in pci_attach_device because it returns for
>> unknown reasons wrong IRQ numbers.
>>
>> Please check if pinfo->irq is the IRQ reported by pci -vv or lspci -vv
>>
>> --Armin
>>
>>
>>
>> srilakshmi wrote:
>>> Yes, I don't have proper knowledge on what I am asking.
>>> But I need to do all these things.
>>> Through the attachment I am sending some code in that code some problem is their its not executing from
pci_attach_device function.
>>> The code is for
>>> I need to send(write) 01020304 message to Master FPGA then FPGA generates interrupt and do some operations then
again when I sent 05060708 message FPGA disables the interrupt.
>>> Would you please help me...
>>> Address location is BAR0[mem] fd7ff000h
>>>
>>> Thanks & Regards
>>> Srilakshmi
>>>
>>> -----Original Message-----
>>> From: Armin Steinhoff [mailto:community-noreply@qnx.com]
>>> Sent: Thursday, July 05, 2012 7:01 PM
>>> To: general-community@community.qnx.com
>>> Cc: srilakshmi; srilakshmi
>>> Subject: Re: PCI Express
>>>
>>>
>>> Attachment ??
>>>
>>> srilakshmi wrote:
>>>> Yes, I don't have proper knowledge on what I am asking.
>>>> But I need to do all these things.
>>>> Through the attachment I am sending some code in that code some problem is their its not executing from
pci_attach_device function.
>>>> The code is for
>>>> I need to write 01020304 message Master FPGA then FPGA generates interrupt and do some operations then again when I
sent 05060708 message FPGA disables the interrupt.
>>>> Would you please help me...
>>>>
>>>> Thanks & Regards
>>>> Srilakshmi
>>>>
>>>> -----Original Message-----
>>>> From: Mario Charest [mailto:community-noreply@qnx.com]
>>>> Sent: Thursday, July 05, 2012 6:06 PM
>>>> To: general-community@community.qnx.com
>>>> Subject: RE: PCI Express
>>>>
>>>>
>>>> I think you are being asked to do something that seems to be way beyond your capabilities.
>>>> Good luck.
>>>>
>>>> -----Message d'origine-----
>>>> De : srilakshmi [mailto:community-noreply@qnx.com]
>>>> Envoyé : Thursday, July 05, 2012 8:30 AM
>>>> À :...
View Full Message
|
|
|
07/06/2012 9:28 AM
post94121
|
But its not working..
You please help me
Thanks & Regards
Srilakshmi
-----Original Message-----
From: Armin Steinhoff [mailto:community-noreply@qnx.com]
Sent: Friday, July 06, 2012 6:15 PM
To: general-community@community.qnx.com
Cc: srilakshmi; srilakshmi
Subject: Re: PCI Express
OK ... then it should work!
--Armin
srilakshmi wrote:
> Yes same no. reported by pci -vvv command also
> Thanks & Regards
> Srilakshmi
>
> -----Original Message-----
> From: Armin Steinhoff [mailto:community-noreply@qnx.com]
> Sent: Friday, July 06, 2012 4:14 PM
> To: general-community@community.qnx.com
> Cc: srilakshmi; srilakshmi
> Subject: Re: PCI Express
>
> srilakshmi wrote:
>> Yes 10 is the no. reported by pinfo->irq.
> ... end this is the same number reported by pci -vvv ??
>
> --Armin
>
>> Thanks & Regards
>> Srilakshmi
>>
>> -----Original Message-----
>> From: Armin Steinhoff [mailto:community-noreply@qnx.com]
>> Sent: Friday, July 06, 2012 12:03 PM
>> To: general-community@community.qnx.com
>> Cc: srilakshmi; srilakshmi
>> Subject: Re: PCI Express
>>
>>
>> Just a question about the interrupt number used in
>>
>> id=InterruptAttach(10,intr_handler,0,0,_NTO_INTR_FLAGS_PROCESS);
>>
>> is this the same IRQ as reported by pinfo->irq ? Normaly you have to use
>> the interrupt number reported by pci_attach_device.
>> But there is still a bug in pci_attach_device because it returns for
>> unknown reasons wrong IRQ numbers.
>>
>> Please check if pinfo->irq is the IRQ reported by pci -vv or lspci -vv
>>
>> --Armin
>>
>>
>>
>> srilakshmi wrote:
>>> Yes, I don't have proper knowledge on what I am asking.
>>> But I need to do all these things.
>>> Through the attachment I am sending some code in that code some problem is their its not executing from
pci_attach_device function.
>>> The code is for
>>> I need to send(write) 01020304 message to Master FPGA then FPGA generates interrupt and do some operations then
again when I sent 05060708 message FPGA disables the interrupt.
>>> Would you please help me...
>>> Address location is BAR0[mem] fd7ff000h
>>>
>>> Thanks & Regards
>>> Srilakshmi
>>>
>>> -----Original Message-----
>>> From: Armin Steinhoff [mailto:community-noreply@qnx.com]
>>> Sent: Thursday, July 05, 2012 7:01 PM
>>> To: general-community@community.qnx.com
>>> Cc: srilakshmi; srilakshmi
>>> Subject: Re: PCI Express
>>>
>>>
>>> Attachment ??
>>>
>>> srilakshmi wrote:
>>>> Yes, I don't have proper knowledge on what I am asking.
>>>> But I need to do all these things.
>>>> Through the attachment I am sending some code in that code some problem is their its not executing from
pci_attach_device function.
>>>> The code is for
>>>> I need to write 01020304 message Master FPGA then FPGA generates interrupt and do some operations then again when I
sent 05060708 message FPGA disables the interrupt.
>>>> Would you please help me...
>>>>
>>>> Thanks & Regards
>>>> Srilakshmi
>>>>
>>>> -----Original Message-----
>>>> From: Mario Charest [mailto:community-noreply@qnx.com]
>>>> Sent: Thursday, July 05, 2012 6:06 PM
>>>> To: general-community@community.qnx.com
>>>> Subject: RE: PCI Express
>>>>
>>>>
>>>> I think you are being asked to do something that seems to be way beyond your...
View Full Message
|
|
|
07/06/2012 9:38 AM
post94126
|
Would it not make more sense to do the write action
pdw = base_ptr[0];
*pdw = 0x01020304;
after start of the interrupt thread ??
And you are writing in the main prog then to the right place and the
right pattern ?
--Armin
srilakshmi wrote:
> But its not working..
> You please help me
>
> Thanks & Regards
> Srilakshmi
>
> -----Original Message-----
> From: Armin Steinhoff [mailto:community-noreply@qnx.com]
> Sent: Friday, July 06, 2012 6:15 PM
> To: general-community@community.qnx.com
> Cc: srilakshmi; srilakshmi
> Subject: Re: PCI Express
>
>
> OK ... then it should work!
>
> --Armin
>
> srilakshmi wrote:
>> Yes same no. reported by pci -vvv command also
>> Thanks & Regards
>> Srilakshmi
>>
>> -----Original Message-----
>> From: Armin Steinhoff [mailto:community-noreply@qnx.com]
>> Sent: Friday, July 06, 2012 4:14 PM
>> To: general-community@community.qnx.com
>> Cc: srilakshmi; srilakshmi
>> Subject: Re: PCI Express
>>
>> srilakshmi wrote:
>>> Yes 10 is the no. reported by pinfo->irq.
>> ... end this is the same number reported by pci -vvv ??
>>
>> --Armin
>>
>>> Thanks & Regards
>>> Srilakshmi
>>>
>>> -----Original Message-----
>>> From: Armin Steinhoff [mailto:community-noreply@qnx.com]
>>> Sent: Friday, July 06, 2012 12:03 PM
>>> To: general-community@community.qnx.com
>>> Cc: srilakshmi; srilakshmi
>>> Subject: Re: PCI Express
>>>
>>>
>>> Just a question about the interrupt number used in
>>>
>>> id=InterruptAttach(10,intr_handler,0,0,_NTO_INTR_FLAGS_PROCESS);
>>>
>>> is this the same IRQ as reported by pinfo->irq ? Normaly you have to use
>>> the interrupt number reported by pci_attach_device.
>>> But there is still a bug in pci_attach_device because it returns for
>>> unknown reasons wrong IRQ numbers.
>>>
>>> Please check if pinfo->irq is the IRQ reported by pci -vv or lspci -vv
>>>
>>> --Armin
>>>
>>>
>>>
>>> srilakshmi wrote:
>>>> Yes, I don't have proper knowledge on what I am asking.
>>>> But I need to do all these things.
>>>> Through the attachment I am sending some code in that code some problem is their its not executing from
pci_attach_device function.
>>>> The code is for
>>>> I need to send(write) 01020304 message to Master FPGA then FPGA generates interrupt and do some operations then
again when I sent 05060708 message FPGA disables the interrupt.
>>>> Would you please help me...
>>>> Address location is BAR0[mem] fd7ff000h
>>>>
>>>> Thanks & Regards
>>>> Srilakshmi
>>>>
>>>> -----Original Message-----
>>>> From: Armin Steinhoff [mailto:community-noreply@qnx.com]
>>>> Sent: Thursday, July 05, 2012 7:01 PM
>>>> To: general-community@community.qnx.com
>>>> Cc: srilakshmi; srilakshmi
>>>> Subject: Re: PCI Express
>>>>
>>>>
>>>> Attachment ??
>>>>
>>>> srilakshmi wrote:
>>>>> Yes, I don't have proper knowledge on what I am asking.
>>>>> But I need to do all these things.
>>>>> Through the attachment I am sending some code in that code some problem is their its not executing from
pci_attach_device function.
>>>>> The code is for
>>>>> I need to write 01020304 message Master FPGA then FPGA generates interrupt and do some operations then again...
View Full Message
|
|
|
07/10/2012 8:08 AM
post94163
|
Now I have completed some part of my task.
Now I need to send bulk of data with packet for this may be I need to use DMA transactions.
Would u pls help me?
Thanks & Regards
Srilakshmi
-----Original Message-----
From: Armin Steinhoff [mailto:community-noreply@qnx.com]
Sent: Friday, July 06, 2012 7:09 PM
To: general-community@community.qnx.com
Cc: srilakshmi; srilakshmi
Subject: Re: PCI Express
Would it not make more sense to do the write action
pdw = base_ptr[0];
*pdw = 0x01020304;
after start of the interrupt thread ??
And you are writing in the main prog then to the right place and the
right pattern ?
--Armin
srilakshmi wrote:
> But its not working..
> You please help me
>
> Thanks & Regards
> Srilakshmi
>
> -----Original Message-----
> From: Armin Steinhoff [mailto:community-noreply@qnx.com]
> Sent: Friday, July 06, 2012 6:15 PM
> To: general-community@community.qnx.com
> Cc: srilakshmi; srilakshmi
> Subject: Re: PCI Express
>
>
> OK ... then it should work!
>
> --Armin
>
> srilakshmi wrote:
>> Yes same no. reported by pci -vvv command also
>> Thanks & Regards
>> Srilakshmi
>>
>> -----Original Message-----
>> From: Armin Steinhoff [mailto:community-noreply@qnx.com]
>> Sent: Friday, July 06, 2012 4:14 PM
>> To: general-community@community.qnx.com
>> Cc: srilakshmi; srilakshmi
>> Subject: Re: PCI Express
>>
>> srilakshmi wrote:
>>> Yes 10 is the no. reported by pinfo->irq.
>> ... end this is the same number reported by pci -vvv ??
>>
>> --Armin
>>
>>> Thanks & Regards
>>> Srilakshmi
>>>
>>> -----Original Message-----
>>> From: Armin Steinhoff [mailto:community-noreply@qnx.com]
>>> Sent: Friday, July 06, 2012 12:03 PM
>>> To: general-community@community.qnx.com
>>> Cc: srilakshmi; srilakshmi
>>> Subject: Re: PCI Express
>>>
>>>
>>> Just a question about the interrupt number used in
>>>
>>> id=InterruptAttach(10,intr_handler,0,0,_NTO_INTR_FLAGS_PROCESS);
>>>
>>> is this the same IRQ as reported by pinfo->irq ? Normaly you have to use
>>> the interrupt number reported by pci_attach_device.
>>> But there is still a bug in pci_attach_device because it returns for
>>> unknown reasons wrong IRQ numbers.
>>>
>>> Please check if pinfo->irq is the IRQ reported by pci -vv or lspci -vv
>>>
>>> --Armin
>>>
>>>
>>>
>>> srilakshmi wrote:
>>>> Yes, I don't have proper knowledge on what I am asking.
>>>> But I need to do all these things.
>>>> Through the attachment I am sending some code in that code some problem is their its not executing from
pci_attach_device function.
>>>> The code is for
>>>> I need to send(write) 01020304 message to Master FPGA then FPGA generates interrupt and do some operations then
again when I sent 05060708 message FPGA disables the interrupt.
>>>> Would you please help me...
>>>> Address location is BAR0[mem] fd7ff000h
>>>>
>>>> Thanks & Regards
>>>> Srilakshmi
>>>>
>>>> -----Original Message-----
>>>> From: Armin Steinhoff [mailto:community-noreply@qnx.com]
>>>> Sent: Thursday, July 05, 2012 7:01 PM
>>>> To: general-community@community.qnx.com
>>>> Cc: srilakshmi; srilakshmi
>>>> Subject: Re: PCI Express
>>>>
>>>>
>>>> Attachment ??
>>>>
>>>> srilakshmi wrote:
>>>>> Yes, I don't have...
View Full Message
|
|
|
07/10/2012 8:46 AM
post94164
|
srilakshmi wrote:
> Now I have completed some part of my task.
What does it mean? The FPGA is able to create interrupts ?
--Armin
> Now I need to send bulk of data with packet for this may be I need to use DMA transactions.
> Would u pls help me?
>
> Thanks & Regards
> Srilakshmi
>
>
> -----Original Message-----
> From: Armin Steinhoff [mailto:community-noreply@qnx.com]
> Sent: Friday, July 06, 2012 7:09 PM
> To: general-community@community.qnx.com
> Cc: srilakshmi; srilakshmi
> Subject: Re: PCI Express
>
> Would it not make more sense to do the write action
>
> pdw = base_ptr[0];
> *pdw = 0x01020304;
>
> after start of the interrupt thread ??
>
> And you are writing in the main prog then to the right place and the
> right pattern ?
>
> --Armin
>
>
> srilakshmi wrote:
>> But its not working..
>> You please help me
>>
>> Thanks & Regards
>> Srilakshmi
>>
>> -----Original Message-----
>> From: Armin Steinhoff [mailto:community-noreply@qnx.com]
>> Sent: Friday, July 06, 2012 6:15 PM
>> To: general-community@community.qnx.com
>> Cc: srilakshmi; srilakshmi
>> Subject: Re: PCI Express
>>
>>
>> OK ... then it should work!
>>
>> --Armin
>>
>> srilakshmi wrote:
>>> Yes same no. reported by pci -vvv command also
>>> Thanks & Regards
>>> Srilakshmi
>>>
>>> -----Original Message-----
>>> From: Armin Steinhoff [mailto:community-noreply@qnx.com]
>>> Sent: Friday, July 06, 2012 4:14 PM
>>> To: general-community@community.qnx.com
>>> Cc: srilakshmi; srilakshmi
>>> Subject: Re: PCI Express
>>>
>>> srilakshmi wrote:
>>>> Yes 10 is the no. reported by pinfo->irq.
>>> ... end this is the same number reported by pci -vvv ??
>>>
>>> --Armin
>>>
>>>> Thanks & Regards
>>>> Srilakshmi
>>>>
>>>> -----Original Message-----
>>>> From: Armin Steinhoff [mailto:community-noreply@qnx.com]
>>>> Sent: Friday, July 06, 2012 12:03 PM
>>>> To: general-community@community.qnx.com
>>>> Cc: srilakshmi; srilakshmi
>>>> Subject: Re: PCI Express
>>>>
>>>>
>>>> Just a question about the interrupt number used in
>>>>
>>>> id=InterruptAttach(10,intr_handler,0,0,_NTO_INTR_FLAGS_PROCESS);
>>>>
>>>> is this the same IRQ as reported by pinfo->irq ? Normaly you have to use
>>>> the interrupt number reported by pci_attach_device.
>>>> But there is still a bug in pci_attach_device because it returns for
>>>> unknown reasons wrong IRQ numbers.
>>>>
>>>> Please check if pinfo->irq is the IRQ reported by pci -vv or lspci -vv
>>>>
>>>> --Armin
>>>>
>>>>
>>>>
>>>> srilakshmi wrote:
>>>>> Yes, I don't have proper knowledge on what I am asking.
>>>>> But I need to do all these things.
>>>>> Through the attachment I am sending some code in that code some problem is their its not executing from
pci_attach_device function.
>>>>> The code is for
>>>>> I need to send(write) 01020304 message to Master FPGA then FPGA generates interrupt and do some operations then
again when I sent 05060708 message FPGA disables the interrupt.
>>>>> Would you please help me...
>>>>> Address location is BAR0[mem] fd7ff000h
>>>>>
>>>>> Thanks &...
View Full Message
|
|
|
07/11/2012 4:57 AM
post94185
|
Yes when I send data like 01020304 FPGA creates Interrupts again when I send 05060708 disables the Interrupts.
Now I need to send bulk of data(1024bytes) with single packet.
Thanks & Regards
Srilakshmi
-----Original Message-----
From: Armin Steinhoff [mailto:community-noreply@qnx.com]
Sent: Tuesday, July 10, 2012 5:58 PM
To: general-community@community.qnx.com
Cc: srilakshmi; srilakshmi
Subject: Re: PCI Express
srilakshmi wrote:
> Now I have completed some part of my task.
What does it mean? The FPGA is able to create interrupts ?
--Armin
> Now I need to send bulk of data with packet for this may be I need to use DMA transactions.
> Would u pls help me?
>
> Thanks & Regards
> Srilakshmi
>
>
> -----Original Message-----
> From: Armin Steinhoff [mailto:community-noreply@qnx.com]
> Sent: Friday, July 06, 2012 7:09 PM
> To: general-community@community.qnx.com
> Cc: srilakshmi; srilakshmi
> Subject: Re: PCI Express
>
> Would it not make more sense to do the write action
>
> pdw = base_ptr[0];
> *pdw = 0x01020304;
>
> after start of the interrupt thread ??
>
> And you are writing in the main prog then to the right place and the
> right pattern ?
>
> --Armin
>
>
> srilakshmi wrote:
>> But its not working..
>> You please help me
>>
>> Thanks & Regards
>> Srilakshmi
>>
>> -----Original Message-----
>> From: Armin Steinhoff [mailto:community-noreply@qnx.com]
>> Sent: Friday, July 06, 2012 6:15 PM
>> To: general-community@community.qnx.com
>> Cc: srilakshmi; srilakshmi
>> Subject: Re: PCI Express
>>
>>
>> OK ... then it should work!
>>
>> --Armin
>>
>> srilakshmi wrote:
>>> Yes same no. reported by pci -vvv command also
>>> Thanks & Regards
>>> Srilakshmi
>>>
>>> -----Original Message-----
>>> From: Armin Steinhoff [mailto:community-noreply@qnx.com]
>>> Sent: Friday, July 06, 2012 4:14 PM
>>> To: general-community@community.qnx.com
>>> Cc: srilakshmi; srilakshmi
>>> Subject: Re: PCI Express
>>>
>>> srilakshmi wrote:
>>>> Yes 10 is the no. reported by pinfo->irq.
>>> ... end this is the same number reported by pci -vvv ??
>>>
>>> --Armin
>>>
>>>> Thanks & Regards
>>>> Srilakshmi
>>>>
>>>> -----Original Message-----
>>>> From: Armin Steinhoff [mailto:community-noreply@qnx.com]
>>>> Sent: Friday, July 06, 2012 12:03 PM
>>>> To: general-community@community.qnx.com
>>>> Cc: srilakshmi; srilakshmi
>>>> Subject: Re: PCI Express
>>>>
>>>>
>>>> Just a question about the interrupt number used in
>>>>
>>>> id=InterruptAttach(10,intr_handler,0,0,_NTO_INTR_FLAGS_PROCESS);
>>>>
>>>> is this the same IRQ as reported by pinfo->irq ? Normaly you have to use
>>>> the interrupt number reported by pci_attach_device.
>>>> But there is still a bug in pci_attach_device because it returns for
>>>> unknown reasons wrong IRQ numbers.
>>>>
>>>> Please check if pinfo->irq is the IRQ reported by pci -vv or lspci -vv
>>>>
>>>> --Armin
>>>>
>>>>
>>>>
>>>> srilakshmi wrote:
>>>>> Yes, I don't have proper knowledge on what I am asking.
>>>>> But I need to do all these things.
>>>>> Through the attachment I am sending some code in that code some problem is their its not executing from
pci_attach_device...
View Full Message
|
|
|
07/11/2012 10:00 AM
post94189
|
srilakshmi wrote:
> Yes when I send data like 01020304 FPGA creates Interrupts again when I send 05060708 disables the Interrupts.
> Now I need to send bulk of data(1024bytes) with single packet.
OK ... sounds great !
If the PCIe chip has a DMA interface you need at first a DMA buffer.
The proc below allocates one.
// allocate DMA memory
void *dma_malloc(uint32_t len, off_t * paddr)
{
void * vaddr;
vaddr = mmap( 0, len, PROT_READ|PROT_WRITE,
MAP_PHYS|MAP_ANON|MAP_PRIVATE, NOFD, 0 );
if(vaddr == NULL)
return(NULL);
if(mem_offset( vaddr, NOFD, 1, paddr, NULL ))
return(NULL);
return(vaddr);
}
The physical address of the buffer is located in paddr ... you have to
use it for feeding your DMA interface.
The returned address is the address of the DMA buffer located in your
address space.
If DMA isn't supported you have to map different base address registers
which are referencing plain data memory segments of the board.
--Armin
>
> Thanks & Regards
> Srilakshmi
>
>
> -----Original Message-----
> From: Armin Steinhoff [mailto:community-noreply@qnx.com]
> Sent: Tuesday, July 10, 2012 5:58 PM
> To: general-community@community.qnx.com
> Cc: srilakshmi; srilakshmi
> Subject: Re: PCI Express
>
> srilakshmi wrote:
>> Now I have completed some part of my task.
> What does it mean? The FPGA is able to create interrupts ?
>
> --Armin
>
>
>> Now I need to send bulk of data with packet for this may be I need to use DMA transactions.
>> Would u pls help me?
>>
>> Thanks & Regards
>> Srilakshmi
>>
>>
>> -----Original Message-----
>> From: Armin Steinhoff [mailto:community-noreply@qnx.com]
>> Sent: Friday, July 06, 2012 7:09 PM
>> To: general-community@community.qnx.com
>> Cc: srilakshmi; srilakshmi
>> Subject: Re: PCI Express
>>
>> Would it not make more sense to do the write action
>>
>> pdw = base_ptr[0];
>> *pdw = 0x01020304;
>>
>> after start of the interrupt thread ??
>>
>> And you are writing in the main prog then to the right place and the
>> right pattern ?
>>
>> --Armin
>>
>>
>> srilakshmi wrote:
>>> But its not working..
>>> You please help me
>>>
>>> Thanks & Regards
>>> Srilakshmi
>>>
>>> -----Original Message-----
>>> From: Armin Steinhoff [mailto:community-noreply@qnx.com]
>>> Sent: Friday, July 06, 2012 6:15 PM
>>> To: general-community@community.qnx.com
>>> Cc: srilakshmi; srilakshmi
>>> Subject: Re: PCI Express
>>>
>>>
>>> OK ... then it should work!
>>>
>>> --Armin
>>>
>>> srilakshmi wrote:
>>>> Yes same no. reported by pci -vvv command also
>>>> Thanks & Regards
>>>> Srilakshmi
>>>>
>>>> -----Original Message-----
>>>> From: Armin Steinhoff [mailto:community-noreply@qnx.com]
>>>> Sent: Friday, July 06, 2012 4:14 PM
>>>> To: general-community@community.qnx.com
>>>> Cc: srilakshmi; srilakshmi
>>>> Subject: Re: PCI Express
>>>>
>>>> srilakshmi wrote:
>>>>> Yes 10 is the no. reported by pinfo->irq.
>>>> ... end this is the same number reported by pci -vvv ??
>>>>
>>>> --Armin
>>>>
>>>>> Thanks & Regards
>>>>> Srilakshmi
>>>>>
>>>>> -----Original Message-----
>>>>> From: Armin Steinhoff [mailto:community-noreply@qnx.com]
>>>>> Sent: Friday, July 06, 2012 12:03...
View Full Message
|
|
|
07/05/2012 9:17 AM
post94066
|
srilakshmi wrote:
> Do you send me any sample code for generating MSI in QNX(to Master FPGA)?
Please realize that only the PCI Express board can send MSI interrupt
messages to the Intel chipset.
That means: PCIe chip ---->>> sends *M*essage *S*ignaled *I*nterrupt
(MSI) ---->>> chip set ---> CPU
There is *NO way* to do it in the reverse direction. That's the way the
hardware has been designed ....
--Armin
>
> Thanks & Regards
> Srilakshmi
> -----Original Message-----
> From: Armin Steinhoff [mailto:community-noreply@qnx.com]
> Sent: Thursday, July 05, 2012 3:00 PM
> To: general-community@community.qnx.com
> Cc: srilakshmi; srilakshmi
> Subject: Re: PCI Express
>
>
> SP1 is the "Service Pack 1 of QNX 6.5.0" ... it fixes several issues.
> You can download it from the QNX homepage.
> Or ask your distributor for the related CDs ..
>
> --Armin
>
> srilakshmi wrote:
>> We are using QNX 6.5.0
>>
>> Thanks & Regards
>> Srilakshmi
>>
>> -----Original Message-----
>> From: Armin Steinhoff [mailto:community-noreply@qnx.com]
>> Sent: Thursday, July 05, 2012 12:45 PM
>> To: general-community@community.qnx.com
>> Cc: srilakshmi; srilakshmi
>> Subject: Re: PCI Express
>>
>>
>> Hi,
>>
>> you have to use QNX 6.5.0 SP1
>>
>> --Armin
>>
>>
>> srilakshmi wrote:
>>> In QNX 6.5.0 pci_attach_device() don't have flags like PCI_USE_MSI or
>>> PCI_USE_MSIX.
>>>
>>> Thanks & Regards
>>> Srilakshmi
>>>
>>>
>>> -----Original Message-----
>>> From: Hugh Brown [mailto:community-noreply@qnx.com]
>>> Sent: Wednesday, July 04, 2012 8:59 PM
>>> To: general-community@community.qnx.com
>>> Subject: Re: PCI Express
>>>
>>> Armin,
>>>
>>> These functions are part of the pci_attach_device() function call. In the
>>> flags section you either add PCI_USE_MSI or PCI_USE_MSIX depending on
>>> which interrupt type you want to use. If you use these flags and the
>>> device doesn't support MSI or MSIX, the PCI server will default to IRQ
>>> interrupts.
>>>
>>> Hugh.
>>>
>>
>>
>>
>>
>> _______________________________________________
>>
>> General
>> http://community.qnx.com/sf/go/post94042
>> To cancel your subscription to this discussion, please e-mail
>> general-community-unsubscribe@community.qnx.com
>>
>> -----
>> No virus found in this message.
>> Checked by AVG - www.avg.com
>> Version: 2012.0.2177 / Virus Database: 2437/5111 - Release Date: 07/04/12
>>
>>
>>
>>
>>
>> _______________________________________________
>>
>> General
>> http://community.qnx.com/sf/go/post94044
>> To cancel your subscription to this discussion, please e-mail
> general-community-unsubscribe@community.qnx.com
>
>
>
>
>
> _______________________________________________
>
> General
> http://community.qnx.com/sf/go/post94046
> To cancel your subscription to this discussion, please e-mail
> general-community-unsubscribe@community.qnx.com
>
> -----
> No virus found in this message.
> Checked by AVG - www.avg.com
> Version: 2012.0.2177 / Virus Database: 2437/5111 - Release Date: 07/04/12
>
>
>
>
>
> _______________________________________________
>
> General
> http://community.qnx.com/sf/go/post94060
> To cancel your subscription to this discussion, please e-mail...
|
|
|
07/04/2012 8:07 AM
post94015
|
Hugh,
Hugh Brown wrote:
> The BAR registers are only enabled once you run your program and perform a
> pci_attach_device(). If you don't use the PCI_PERSIST flag, when your
> program terminates, the BAR registers will be reset and disabled.
No, that can't be the case. PCI_PERSIST had a clear semantic in context
with PCI_SHARE.
If a PCI device isn't shared by other resource managers no one would set
PCI_PERSIST in its resource manager.
With the new semantic of PCI_PERSIST would be every restart of a
resource manager impossible !
--Armin
>
>
>
>
> On 12-07-04 5:57 AM, "srilakshmi" <community-noreply@qnx.com> wrote:
>
>> I got some problem...
>>
>> When I am invoking Xilinx board through Intel Q57 Motherboard's PCIe slot
>> I am getting the output of pci -v command is
>> BAR0,BAR1,BAR2 are disabled, Interrupt connection is no connection
>>
>> When I am invoking same Xilinx board through Advantech Intel Motherboard's
>> PCIe slot
>> I am getting the output of pci -v command is
>> BAR0,BAR1,BAR2 are enabled, Interrupt connection = 10.
>>
>> Is their any problem with Advantech Motherboard or we need to do something
>> at this Motherboard?
>>
>> Thanks & regards
>> Srilakshmi
>>
>>
>> -----Original Message-----
>> From: Armin Steinhoff [mailto:community-noreply@qnx.com]
>> Sent: Monday, July 02, 2012 9:44 PM
>> To: general-community@community.qnx.com
>> Cc: Mario Charest; Mario Charest
>> Subject: RE: PCI Express
>>
>> Mario Charest wrote:
>>> Mario Charest wrote:
>>>>> Armin,
>>>>>
>>>>> I got the say, I never expected you to show that much patience, lol!
>>>> I have a lot of "PCI customers" for QNX 6.5, so I'm well trained :)
>>>> But I
>> hope to get rid of this special fun with QNX 6.5 SPI or SP2 ?? Or QNX 8
>> ???
>>> With BB10 most probably doom maybe QSS will have more time/resources to
>> dedicated to speeding up the release cycle, maybe not!
>>
>> Well ... RIM should build the right hardware compatible to QNX .... CARS
>> :)
>>
>> --Armin
>>
>>> PS this is my personal opinion based on information publicly available,
>>> I
>> have no inside information. Sometimes readers take me too seriously ;-)
>>>
>>>
>>>
>>>
>>> _______________________________________________
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>>
>>
>>
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