Joel Pilon(deleted)
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Re: Slow mmap memory access
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Joel Pilon(deleted)
09/26/2012 1:09 PM
post95851
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Re: Slow mmap memory access
On ARM there would be more options, but for x86 you can get some form of
write-through cache with shm_ctl and SHMCTL_LAZYWRITE. You then need to
map it using the FD, I can't remember if you need to map with or without
PROT_NOCACHE.
-Joel
On 12-09-26 12:44 PM, Mario Charest wrote:
>
>
>> -----Message d'origine-----
>> De : Javier I. Acosta M. [mailto:community-noreply@qnx.com]
>> Envoyé : 26 septembre 2012 11:58
>> À : general-community
>> Objet : Re: RE: RE: Slow mmap memory access
>>
>> Thanks Mario, I am testing with cache disabled but I wanted to know if there
>> was any other tweaks I could apply. The fact that disabling the cache slows it
>> that much it does not seem very convincing to me, there must be something
>> going on under the hood that I am not aware.
>
> Possible but modern processor suffer a MAJOR performance hit when going to system ram instead of cache.
>
> An i7-3960 (it has 4 channels) as a memory read speed of 20G/sec, while the L1 cache has 155G/Sec !!!! L2 has 87G and
L3 32G. And the corresponding latency is RAM: 47ns, L1: 0.8ns, L2: 2.5ns, L3: 5.3ns. This is on an overlock system
though, so the gap between memory and cache would be reduce if not overclocked. But that gives you an idea...
>
>
>
>>
>> Thanks again,
>> Javier
>>
>>
>>
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