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06/20/2012 2:47 PM
post93788
|
srilakshmi wrote:
> How to recognize interrupts coming from FPGA through PCI?
is this a board with a PCI interface together with separate FPGA chip??
Or is the PCI interface realized as a core of the FPGA?
Could you post the output of "pci -vvv" ?
> Please provide me
> document or code regarding this.
>
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06/21/2012 1:34 AM
post93792
|
Through the attached file I am sending the output of pci -vvv.
My project board contains both Intel chip and FPGA chip on same board.
through PCI express slot we are connecting Xilinx board. Through PCIe we are
communicating with each other. And the result is checking at FPGA side by
Chipscope software.
And the previous which you have sent to me is not working because
pci_dev_info predefined structure doesn't contain members like HeaderType,
CpuBmstrTranslation, CpuIsaTranslation, CpuMemTranslation, NumIrq,
info.MsiDefs[i].count
Srilakshmi
-----Original Message-----
From: Armin Steinhoff [mailto:community-noreply@qnx.com]
Sent: Wednesday, June 20, 2012 11:59 PM
To: general-community@community.qnx.com
Cc: srilakshmi; srilakshmi
Subject: Re: PCI Express
srilakshmi wrote:
> How to recognize interrupts coming from FPGA through PCI?
is this a board with a PCI interface together with separate FPGA chip??
Or is the PCI interface realized as a core of the FPGA?
Could you post the output of "pci -vvv" ?
> Please provide me
> document or code regarding this.
>
_______________________________________________
General
http://community.qnx.com/sf/go/post93788
To cancel your subscription to this discussion, please e-mail
general-community-unsubscribe@community.qnx.com
-----
No virus found in this message.
Checked by AVG - www.avg.com
Version: 2012.0.2177 / Virus Database: 2437/5081 - Release Date: 06/20/12
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06/21/2012 4:37 AM
post93794
|
srilakshmi wrote:
> Through the attached file I am sending the output of pci -vvv.
> My project board contains both Intel chip and FPGA chip on same board.
> through PCI express slot we are connecting Xilinx board. Through PCIe we are
> communicating with each other. And the result is checking at FPGA side by
> Chipscope software.
Ok ... and this is a board from Xilinx with the vendor ID 10EEh ??
This board seems to be completely disabled ...
No I/O memory, no memory, no connection to an interrupt line.
Also the memory of 128 bytes referenced by BAR[0] is disabled !
Please see the marks at the printouts of the "pci" command:
Vendor ID = 10eeh, Xilinx Corporation
Device ID = 7h, Unknown Unknown
PCI index = 0h
Class Codes = 050000h
Revision ID = 0h
Bus number = 2
Device number = 0
Function num = 0
Status Reg = 10h
Command Reg = 0h
I/O space access *disabled* <<<============ !!!
Memory space access *disabled* <<<============ !!!
Bus Master disabled
Special Cycle operations ignored
Memory Write and Invalidate *disabled* <<<============ !!!
Palette Snooping disabled
Parity Error Response disabled
Data/Address stepping disabled
SERR# driver disabled
Fast back-to-back transactions to different agents disabled
PCI INTx enabled
Header type = 0h Single-function
BIST = 0h Build-in-self-test not supported
Latency Timer = 0h
Cache Line Size= 0h
BAR - 0 [Mem] = 0h 32bit length 128 *disabled* <<<========= !!!
Subsystem Vendor ID = 10eeh
Subsystem ID = 7h
Max Lat = 0ns
Min Gnt = 0ns
PCI Int Pin = INT A
Interrupt line = *no connection* <<<========== !!!
> And the previous which you have sent to me is not working because
> pci_dev_info predefined structure doesn't contain members like HeaderType,
> CpuBmstrTranslation, CpuIsaTranslation, CpuMemTranslation, NumIrq,
> info.MsiDefs[i].count
The example code previously posted by Hugh Brown is for QNX 6.5.
Are you working with QNX 6.4.x ??
Best Regards
--Armin
http://www.steinhoff-automation.com
>
>
>
> Srilakshmi
>
>
> -----Original Message-----
> From: Armin Steinhoff [mailto:community-noreply@qnx.com]
> Sent: Wednesday, June 20, 2012 11:59 PM
> To: general-community@community.qnx.com
> Cc: srilakshmi; srilakshmi
> Subject: Re: PCI Express
>
> srilakshmi wrote:
>> How to recognize interrupts coming from FPGA through PCI?
> is this a board with a PCI interface together with separate FPGA chip??
> Or is the PCI interface realized as a core of the FPGA?
>
> Could you post the output of "pci -vvv" ?
>
>
>> Please provide me
>> document or code regarding this.
>>
>
>
>
>
> _______________________________________________
>
> General
> http://community.qnx.com/sf/go/post93788
> To cancel your subscription to this discussion, please e-mail
> general-community-unsubscribe@community.qnx.com
>
> -----
> No virus found in this message.
> Checked by AVG - www.avg.com
> Version: 2012.0.2177 / Virus Database: 2437/5081 - Release Date: 06/20/12
>
>
>
>
> _______________________________________________
>
> General
> http://community.qnx.com/sf/go/post93792
> To cancel your subscription to this discussion, please e-mail general-community-unsubscribe@community.qnx.com
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06/21/2012 5:55 AM
post93798
|
I am working with QNX 6.5.0.But in Regarding APIs for pci_dev_info
predefined structure doesn't contains members like HeaderType,
CpuBmstrTranslation, CpuIsaTranslation, CpuMemTranslation, NumIrq,
info.MsiDefs[i].count.
That code is not working for interrupts.
Please provide me document or code.
I need to activate interrupts (recognize interrupts coming from FPGA )
Srilakshmi
From: Armin Steinhoff [mailto:community-noreply@qnx.com]
Sent: Thursday, June 21, 2012 2:08 PM
To: general-community@community.qnx.com
Cc: srilakshmi; srilakshmi
Subject: Re: PCI Express
srilakshmi wrote:
Through the attached file I am sending the output of pci -vvv.
My project board contains both Intel chip and FPGA chip on same board.
through PCI express slot we are connecting Xilinx board. Through PCIe we are
communicating with each other. And the result is checking at FPGA side by
Chipscope software.
Ok ... and this is a board from Xilinx with the vendor ID 10EEh ??
This board seems to be completely disabled ...
No I/O memory, no memory, no connection to an interrupt line.
Also the memory of 128 bytes referenced by BAR[0] is disabled !
Please see the marks at the printouts of the "pci" command:
Vendor ID = 10eeh, Xilinx Corporation
Device ID = 7h, Unknown Unknown
PCI index = 0h
Class Codes = 050000h
Revision ID = 0h
Bus number = 2
Device number = 0
Function num = 0
Status Reg = 10h
Command Reg = 0h
I/O space access disabled <<<============ !!!
Memory space access disabled <<<============ !!!
Bus Master disabled
Special Cycle operations ignored
Memory Write and Invalidate disabled <<<============ !!!
Palette Snooping disabled
Parity Error Response disabled
Data/Address stepping disabled
SERR# driver disabled
Fast back-to-back transactions to different agents disabled
PCI INTx enabled
Header type = 0h Single-function
BIST = 0h Build-in-self-test not supported
Latency Timer = 0h
Cache Line Size= 0h
BAR - 0 [Mem] = 0h 32bit length 128 disabled <<<========= !!!
Subsystem Vendor ID = 10eeh
Subsystem ID = 7h
Max Lat = 0ns
Min Gnt = 0ns
PCI Int Pin = INT A
Interrupt line = no connection <<<========== !!!
And the previous which you have sent to me is not working because
pci_dev_info predefined structure doesn't contain members like HeaderType,
CpuBmstrTranslation, CpuIsaTranslation, CpuMemTranslation, NumIrq,
info.MsiDefs[i].count
The example code previously posted by Hugh Brown is for QNX 6.5.
Are you working with QNX 6.4.x ??
Best Regards
--Armin
http://www.steinhoff-automation.com
Srilakshmi
-----Original Message-----
From: Armin Steinhoff [mailto:community-noreply@qnx.com]
Sent: Wednesday, June 20, 2012 11:59 PM
To: general-community@community.qnx.com
Cc: srilakshmi; srilakshmi
Subject: Re: PCI Express
srilakshmi wrote:
How to recognize interrupts coming from FPGA through PCI?
is this a board with a PCI interface together with separate FPGA chip??
Or is the PCI interface realized as a core of the FPGA?
Could you post the output of "pci -vvv" ?
Please provide me
document or code regarding this.
_______________________________________________
General
http://community.qnx.com/sf/go/post93788
To cancel your subscription to this discussion, please e-mail
general-community-unsubscribe@community.qnx.com
-----
No virus found in this message.
Checked by AVG - www.avg.com
Version: 2012.0.2177 / Virus Database: 2437/5081 - Release Date: 06/20/12
_______________________________________________
General
http://community.qnx.com/sf/go/post93792
To cancel your subscription to this discussion, please...
View Full Message
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06/21/2012 7:06 AM
post93802
|
srilakshmi wrote:
>
> I am working with QNX 6.5.0.But in Regarding APIs for pci_dev_info
> predefined structure doesn't contains members like HeaderType,
>
remove the code refrencing HeaderType ... it seems not to be a member
of the "released" version of pci_dev_info!
Also remove USE_MSI and USE_MSIX from pci_attach_device ...
> CpuBmstrTranslation, CpuIsaTranslation, CpuMemTranslation,
>
pci_dev_info contains these members
> NumIrq,
>
NumIrq is Irq ...
> info.MsiDefs[i].count...
>
remove any references to MsiDefs ... ... seems not to be a member of the
"released" version of pci_dev_info.
> That code is not working for interrupts.
>
That code does absolutely nothing with the interrupt.
Have a look to the call InterrupAttach a.s.o
--Armin
> Please provide me document or code.
>
> I need to activate interrupts (recognize interrupts coming from FPGA )
>
> Srilakshmi
>
> *From:*Armin Steinhoff [mailto:community-noreply@qnx.com]
> *Sent:* Thursday, June 21, 2012 2:08 PM
> *To:* general-community@community.qnx.com
> *Cc:* srilakshmi; srilakshmi
> *Subject:* Re: PCI Express
>
> srilakshmi wrote:
>
> Through the attached file I am sending the output of pci -vvv.
> My project board contains both Intel chip and FPGA chip on same board.
> through PCI express slot we are connecting Xilinx board. Through PCIe we are
> communicating with each other. And the result is checking at FPGA side by
> Chipscope software.
>
>
> Ok ... and this is a board from Xilinx with the vendor ID 10EEh ??
>
> This board seems to be completely disabled ...
> No I/O memory, no memory, no connection to an interrupt line.
> Also the memory of 128 bytes referenced by BAR[0] is disabled !
>
> Please see the marks at the printouts of the "pci" command:
>
> Vendor ID = 10eeh, Xilinx Corporation
> Device ID = 7h, Unknown Unknown
> PCI index = 0h
> Class Codes = 050000h
> Revision ID = 0h
> Bus number = 2
> Device number = 0
> Function num = 0
> Status Reg = 10h
> Command Reg = 0h
> I/O space access *disabled* <<<============ !!!
> Memory space access *disabled* <<<============ !!!
> Bus Master disabled
> Special Cycle operations ignored
> Memory Write and Invalidate *disabled* <<<============ !!!
> Palette Snooping disabled
> Parity Error Response disabled
> Data/Address stepping disabled
> SERR# driver disabled
> Fast back-to-back transactions to different agents disabled
> PCI INTx enabled
> Header type = 0h Single-function
> BIST = 0h Build-in-self-test not supported
> Latency Timer = 0h
> Cache Line Size= 0h
> BAR - 0 [Mem] = 0h 32bit length 128 *disabled* <<<========= !!!
> Subsystem Vendor ID = 10eeh
> Subsystem ID = 7h
> Max Lat = 0ns
> Min Gnt = 0ns
> PCI Int Pin = INT A
> Interrupt line = *no connection* <<<========== !!!
>
>
>
>
> And the previous which you have sent to me is not working because
> pci_dev_info predefined structure doesn't contain members like HeaderType,
> CpuBmstrTranslation, CpuIsaTranslation, CpuMemTranslation, NumIrq,
> info.MsiDefs[i].count
>
>
> The example code previously posted by Hugh Brown is for QNX 6.5.
> Are you working with QNX 6.4.x ??
>
> Best Regards
>
> --Armin
>
> http://www.steinhoff-automation.com
>
>
>
>
>
> Srilakshmi
>
>
> -----Original Message-----
> From: Armin Steinhoff [mailto:community-noreply@qnx.com]
> Sent: Wednesday, June 20, 2012 11:59 PM
> To:general-community@community.qnx.com ...
View Full Message
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06/21/2012 6:43 AM
post93799
|
How to enable the interrupt line?
Please provide me sample code or document or explanaion
From: Armin Steinhoff [mailto:community-noreply@qnx.com]
Sent: Thursday, June 21, 2012 2:08 PM
To: general-community@community.qnx.com
Cc: srilakshmi; srilakshmi
Subject: Re: PCI Express
srilakshmi wrote:
Through the attached file I am sending the output of pci -vvv.
My project board contains both Intel chip and FPGA chip on same board.
through PCI express slot we are connecting Xilinx board. Through PCIe we are
communicating with each other. And the result is checking at FPGA side by
Chipscope software.
Ok ... and this is a board from Xilinx with the vendor ID 10EEh ??
This board seems to be completely disabled ...
No I/O memory, no memory, no connection to an interrupt line.
Also the memory of 128 bytes referenced by BAR[0] is disabled !
Please see the marks at the printouts of the "pci" command:
Vendor ID = 10eeh, Xilinx Corporation
Device ID = 7h, Unknown Unknown
PCI index = 0h
Class Codes = 050000h
Revision ID = 0h
Bus number = 2
Device number = 0
Function num = 0
Status Reg = 10h
Command Reg = 0h
I/O space access disabled <<<============ !!!
Memory space access disabled <<<============ !!!
Bus Master disabled
Special Cycle operations ignored
Memory Write and Invalidate disabled <<<============ !!!
Palette Snooping disabled
Parity Error Response disabled
Data/Address stepping disabled
SERR# driver disabled
Fast back-to-back transactions to different agents disabled
PCI INTx enabled
Header type = 0h Single-function
BIST = 0h Build-in-self-test not supported
Latency Timer = 0h
Cache Line Size= 0h
BAR - 0 [Mem] = 0h 32bit length 128 disabled <<<========= !!!
Subsystem Vendor ID = 10eeh
Subsystem ID = 7h
Max Lat = 0ns
Min Gnt = 0ns
PCI Int Pin = INT A
Interrupt line = no connection <<<========== !!!
And the previous which you have sent to me is not working because
pci_dev_info predefined structure doesn't contain members like HeaderType,
CpuBmstrTranslation, CpuIsaTranslation, CpuMemTranslation, NumIrq,
info.MsiDefs[i].count
The example code previously posted by Hugh Brown is for QNX 6.5.
Are you working with QNX 6.4.x ??
Best Regards
--Armin
http://www.steinhoff-automation.com
Srilakshmi
-----Original Message-----
From: Armin Steinhoff [mailto:community-noreply@qnx.com]
Sent: Wednesday, June 20, 2012 11:59 PM
To: general-community@community.qnx.com
Cc: srilakshmi; srilakshmi
Subject: Re: PCI Express
srilakshmi wrote:
How to recognize interrupts coming from FPGA through PCI?
is this a board with a PCI interface together with separate FPGA chip??
Or is the PCI interface realized as a core of the FPGA?
Could you post the output of "pci -vvv" ?
Please provide me
document or code regarding this.
_______________________________________________
General
http://community.qnx.com/sf/go/post93788
To cancel your subscription to this discussion, please e-mail
general-community-unsubscribe@community.qnx.com
-----
No virus found in this message.
Checked by AVG - www.avg.com
Version: 2012.0.2177 / Virus Database: 2437/5081 - Release Date: 06/20/12
_______________________________________________
General
http://community.qnx.com/sf/go/post93792
To cancel your subscription to this discussion, please e-mail
general-community-unsubscribe@community.qnx.com
_____
No virus found in this message.
Checked by AVG - www.avg.com
Version: 2012.0.2177 / Virus Database: 2437/5082 - Release Date: 06/20/12
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06/21/2012 6:47 AM
post93800
|
srilakshmi wrote:
>
> How to enable the interrupt line?
>
Your basically problem is that the board (FPGA core?) doesn't initialize
at hardware level the PCI interface.
The configuration data of the PCI interfaces are normaly provided by a
serial ROM.
Please checkout why the PCI interface isn't initialized!
Nothing can be done with an uninitialized PCI interface ...
--Armin
> Please provide me sample code or document or explanaion
>
> *From:*Armin Steinhoff [mailto:community-noreply@qnx.com]
> *Sent:* Thursday, June 21, 2012 2:08 PM
> *To:* general-community@community.qnx.com
> *Cc:* srilakshmi; srilakshmi
> *Subject:* Re: PCI Express
>
> srilakshmi wrote:
>
> Through the attached file I am sending the output of pci -vvv.
> My project board contains both Intel chip and FPGA chip on same board.
> through PCI express slot we are connecting Xilinx board. Through PCIe we are
> communicating with each other. And the result is checking at FPGA side by
> Chipscope software.
>
>
> Ok ... and this is a board from Xilinx with the vendor ID 10EEh ??
>
> This board seems to be completely disabled ...
> No I/O memory, no memory, no connection to an interrupt line.
> Also the memory of 128 bytes referenced by BAR[0] is disabled !
>
> Please see the marks at the printouts of the "pci" command:
>
> Vendor ID = 10eeh, Xilinx Corporation
> Device ID = 7h, Unknown Unknown
> PCI index = 0h
> Class Codes = 050000h
> Revision ID = 0h
> Bus number = 2
> Device number = 0
> Function num = 0
> Status Reg = 10h
> Command Reg = 0h
> I/O space access *disabled* <<<============ !!!
> Memory space access *disabled* <<<============ !!!
> Bus Master disabled
> Special Cycle operations ignored
> Memory Write and Invalidate *disabled* <<<============ !!!
> Palette Snooping disabled
> Parity Error Response disabled
> Data/Address stepping disabled
> SERR# driver disabled
> Fast back-to-back transactions to different agents disabled
> PCI INTx enabled
> Header type = 0h Single-function
> BIST = 0h Build-in-self-test not supported
> Latency Timer = 0h
> Cache Line Size= 0h
> BAR - 0 [Mem] = 0h 32bit length 128 *disabled* <<<========= !!!
> Subsystem Vendor ID = 10eeh
> Subsystem ID = 7h
> Max Lat = 0ns
> Min Gnt = 0ns
> PCI Int Pin = INT A
> Interrupt line = *no connection* <<<========== !!!
>
>
>
>
> And the previous which you have sent to me is not working because
> pci_dev_info predefined structure doesn't contain members like HeaderType,
> CpuBmstrTranslation, CpuIsaTranslation, CpuMemTranslation, NumIrq,
> info.MsiDefs[i].count
>
>
> The example code previously posted by Hugh Brown is for QNX 6.5.
> Are you working with QNX 6.4.x ??
>
> Best Regards
>
> --Armin
>
> http://www.steinhoff-automation.com
>
>
>
>
>
> Srilakshmi
>
>
> -----Original Message-----
> From: Armin Steinhoff [mailto:community-noreply@qnx.com]
> Sent: Wednesday, June 20, 2012 11:59 PM
> To:general-community@community.qnx.com <mailto:general-community@community.qnx.com>;
> Cc: srilakshmi; srilakshmi
> Subject: Re: PCI Express
>
> srilakshmi wrote:
>
> How to recognize interrupts coming from FPGA through PCI?
>
>
> is this a board with a PCI interface together with separate FPGA chip??
> Or is the PCI interface realized as a core of the FPGA?
>
> Could you post the output of "pci -vvv" ?
>
>
>
> Please provide me
>
> document or code...
View Full Message
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06/21/2012 7:00 AM
post93801
|
How to rectify this problem?
From: Armin Steinhoff [mailto:community-noreply@qnx.com]
Sent: Thursday, June 21, 2012 4:20 PM
To: general-community@community.qnx.com
Cc: srilakshmi; srilakshmi
Subject: Re: PCI Express
srilakshmi wrote:
How to enable the interrupt line?
Your basically problem is that the board (FPGA core?) doesn't initialize at
hardware level the PCI interface.
The configuration data of the PCI interfaces are normaly provided by a
serial ROM.
Please checkout why the PCI interface isn't initialized!
Nothing can be done with an uninitialized PCI interface ...
--Armin
Please provide me sample code or document or explanaion
From: Armin Steinhoff [mailto:community-noreply@qnx.com]
Sent: Thursday, June 21, 2012 2:08 PM
To: general-community@community.qnx.com
Cc: srilakshmi; srilakshmi
Subject: Re: PCI Express
srilakshmi wrote:
Through the attached file I am sending the output of pci -vvv.
My project board contains both Intel chip and FPGA chip on same board.
through PCI express slot we are connecting Xilinx board. Through PCIe we are
communicating with each other. And the result is checking at FPGA side by
Chipscope software.
Ok ... and this is a board from Xilinx with the vendor ID 10EEh ??
This board seems to be completely disabled ...
No I/O memory, no memory, no connection to an interrupt line.
Also the memory of 128 bytes referenced by BAR[0] is disabled !
Please see the marks at the printouts of the "pci" command:
Vendor ID = 10eeh, Xilinx Corporation
Device ID = 7h, Unknown Unknown
PCI index = 0h
Class Codes = 050000h
Revision ID = 0h
Bus number = 2
Device number = 0
Function num = 0
Status Reg = 10h
Command Reg = 0h
I/O space access disabled <<<============ !!!
Memory space access disabled <<<============ !!!
Bus Master disabled
Special Cycle operations ignored
Memory Write and Invalidate disabled <<<============ !!!
Palette Snooping disabled
Parity Error Response disabled
Data/Address stepping disabled
SERR# driver disabled
Fast back-to-back transactions to different agents disabled
PCI INTx enabled
Header type = 0h Single-function
BIST = 0h Build-in-self-test not supported
Latency Timer = 0h
Cache Line Size= 0h
BAR - 0 [Mem] = 0h 32bit length 128 disabled <<<========= !!!
Subsystem Vendor ID = 10eeh
Subsystem ID = 7h
Max Lat = 0ns
Min Gnt = 0ns
PCI Int Pin = INT A
Interrupt line = no connection <<<========== !!!
And the previous which you have sent to me is not working because
pci_dev_info predefined structure doesn't contain members like HeaderType,
CpuBmstrTranslation, CpuIsaTranslation, CpuMemTranslation, NumIrq,
info.MsiDefs[i].count
The example code previously posted by Hugh Brown is for QNX 6.5.
Are you working with QNX 6.4.x ??
Best Regards
--Armin
http://www.steinhoff-automation.com
Srilakshmi
-----Original Message-----
From: Armin Steinhoff [mailto:community-noreply@qnx.com]
Sent: Wednesday, June 20, 2012 11:59 PM
To: general-community@community.qnx.com
Cc: srilakshmi; srilakshmi
Subject: Re: PCI Express
srilakshmi wrote:
How to recognize interrupts coming from FPGA through PCI?
is this a board with a PCI interface together with separate FPGA chip??
Or is the PCI interface realized as a core of the FPGA?
Could you post the output of "pci -vvv" ?
Please provide me
document or code regarding this.
_______________________________________________
General
http://community.qnx.com/sf/go/post93788
To cancel your subscription to this discussion, please e-mail
general-community-unsubscribe@community.qnx.com
-----
No virus found in this message.
Checked by AVG -...
View Full Message
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06/21/2012 7:16 AM
post93805
|
srilakshmi wrote:
>
> How to rectify this problem?
>
Please ask the guy behind the ChipScope :) He should know it ...
--Armin
> *From:*Armin Steinhoff [mailto:community-noreply@qnx.com]
> *Sent:* Thursday, June 21, 2012 4:20 PM
> *To:* general-community@community.qnx.com
> *Cc:* srilakshmi; srilakshmi
> *Subject:* Re: PCI Express
>
> srilakshmi wrote:
>
> How to enable the interrupt line?
>
>
> Your basically problem is that the board (FPGA core?) doesn't
> initialize at hardware level the PCI interface.
> The configuration data of the PCI interfaces are normaly provided by a
> serial ROM.
> Please checkout why the PCI interface isn't initialized!
>
> Nothing can be done with an uninitialized PCI interface ...
>
> --Armin
>
>
>
>
> Please provide me sample code or document or explanaion
>
> *From:*Armin Steinhoff [mailto:community-noreply@qnx.com]
> *Sent:* Thursday, June 21, 2012 2:08 PM
> *To:* general-community@community.qnx.com
> <mailto:general-community@community.qnx.com>;
> *Cc:* srilakshmi; srilakshmi
> *Subject:* Re: PCI Express
>
> srilakshmi wrote:
>
> Through the attached file I am sending the output of pci -vvv.
> My project board contains both Intel chip and FPGA chip on same board.
> through PCI express slot we are connecting Xilinx board. Through PCIe we are
> communicating with each other. And the result is checking at FPGA side by
> Chipscope software.
>
>
> Ok ... and this is a board from Xilinx with the vendor ID 10EEh ??
>
> This board seems to be completely disabled ...
> No I/O memory, no memory, no connection to an interrupt line.
> Also the memory of 128 bytes referenced by BAR[0] is disabled !
>
> Please see the marks at the printouts of the "pci" command:
>
> Vendor ID = 10eeh, Xilinx Corporation
> Device ID = 7h, Unknown Unknown
> PCI index = 0h
> Class Codes = 050000h
> Revision ID = 0h
> Bus number = 2
> Device number = 0
> Function num = 0
> Status Reg = 10h
> Command Reg = 0h
> I/O space access *disabled* <<<============ !!!
> Memory space access *disabled* <<<============ !!!
> Bus Master disabled
> Special Cycle operations ignored
> Memory Write and Invalidate *disabled* <<<============ !!!
> Palette Snooping disabled
> Parity Error Response disabled
> Data/Address stepping disabled
> SERR# driver disabled
> Fast back-to-back transactions to different agents disabled
> PCI INTx enabled
> Header type = 0h Single-function
> BIST = 0h Build-in-self-test not supported
> Latency Timer = 0h
> Cache Line Size= 0h
> BAR - 0 [Mem] = 0h 32bit length 128 *disabled* <<<========= !!!
> Subsystem Vendor ID = 10eeh
> Subsystem ID = 7h
> Max Lat = 0ns
> Min Gnt = 0ns
> PCI Int Pin = INT A
> Interrupt line = *no connection* <<<========== !!!
>
>
>
>
>
> And the previous which you have sent to me is not working because
> pci_dev_info predefined structure doesn't contain members like HeaderType,
> CpuBmstrTranslation, CpuIsaTranslation, CpuMemTranslation, NumIrq,
> info.MsiDefs[i].count
>
>
> The example code previously posted by Hugh Brown is for QNX 6.5.
> Are you working with QNX 6.4.x ??
>
> Best Regards
>
> --Armin
>
> http://www.steinhoff-automation.com
>
>
>
>
>
>
> Srilakshmi
>
>
> -----Original Message-----
> From: Armin Steinhoff [mailto:community-noreply@qnx.com]
> Sent: Wednesday, June 20, 2012 11:59 PM
> To:general-community@community.qnx.com ...
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06/21/2012 7:48 AM
post93807
|
When we are executing the code BAR 0 is mapping &128 bytes of data is
transmitting to FPGA board through PCIe slot. Now the problem is enabling
and recognizing the interrupts.
For this I need help
From: Armin Steinhoff [mailto:community-noreply@qnx.com]
Sent: Thursday, June 21, 2012 4:42 PM
To: general-community@community.qnx.com
Cc: srilakshmi; srilakshmi
Subject: Re: PCI Express
srilakshmi wrote:
How to rectify this problem?
Please ask the guy behind the ChipScope :) He should know it ...
--Armin
From: Armin Steinhoff [mailto:community-noreply@qnx.com]
Sent: Thursday, June 21, 2012 4:20 PM
To: general-community@community.qnx.com
Cc: srilakshmi; srilakshmi
Subject: Re: PCI Express
srilakshmi wrote:
How to enable the interrupt line?
Your basically problem is that the board (FPGA core?) doesn't initialize at
hardware level the PCI interface.
The configuration data of the PCI interfaces are normaly provided by a
serial ROM.
Please checkout why the PCI interface isn't initialized!
Nothing can be done with an uninitialized PCI interface ...
--Armin
Please provide me sample code or document or explanaion
From: Armin Steinhoff [mailto:community-noreply@qnx.com]
Sent: Thursday, June 21, 2012 2:08 PM
To: general-community@community.qnx.com
Cc: srilakshmi; srilakshmi
Subject: Re: PCI Express
srilakshmi wrote:
Through the attached file I am sending the output of pci -vvv.
My project board contains both Intel chip and FPGA chip on same board.
through PCI express slot we are connecting Xilinx board. Through PCIe we are
communicating with each other. And the result is checking at FPGA side by
Chipscope software.
Ok ... and this is a board from Xilinx with the vendor ID 10EEh ??
This board seems to be completely disabled ...
No I/O memory, no memory, no connection to an interrupt line.
Also the memory of 128 bytes referenced by BAR[0] is disabled !
Please see the marks at the printouts of the "pci" command:
Vendor ID = 10eeh, Xilinx Corporation
Device ID = 7h, Unknown Unknown
PCI index = 0h
Class Codes = 050000h
Revision ID = 0h
Bus number = 2
Device number = 0
Function num = 0
Status Reg = 10h
Command Reg = 0h
I/O space access disabled <<<============ !!!
Memory space access disabled <<<============ !!!
Bus Master disabled
Special Cycle operations ignored
Memory Write and Invalidate disabled <<<============ !!!
Palette Snooping disabled
Parity Error Response disabled
Data/Address stepping disabled
SERR# driver disabled
Fast back-to-back transactions to different agents disabled
PCI INTx enabled
Header type = 0h Single-function
BIST = 0h Build-in-self-test not supported
Latency Timer = 0h
Cache Line Size= 0h
BAR - 0 [Mem] = 0h 32bit length 128 disabled <<<========= !!!
Subsystem Vendor ID = 10eeh
Subsystem ID = 7h
Max Lat = 0ns
Min Gnt = 0ns
PCI Int Pin = INT A
Interrupt line = no connection <<<========== !!!
And the previous which you have sent to me is not working because
pci_dev_info predefined structure doesn't contain members like HeaderType,
CpuBmstrTranslation, CpuIsaTranslation, CpuMemTranslation, NumIrq,
info.MsiDefs[i].count
The example code previously posted by Hugh Brown is for QNX 6.5.
Are you working with QNX 6.4.x ??
Best Regards
--Armin
http://www.steinhoff-automation.com
Srilakshmi
-----Original Message-----
From: Armin Steinhoff [mailto:community-noreply@qnx.com]
Sent: Wednesday, June 20, 2012 11:59 PM
To: general-community@community.qnx.com
Cc: srilakshmi; srilakshmi
Subject: Re: PCI Express
srilakshmi wrote:
How to recognize interrupts coming from FPGA through PCI?
is...
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06/21/2012 7:09 AM
post93803
|
When I am executing above attached code I am getting configuration data..
From: Armin Steinhoff [mailto:community-noreply@qnx.com]
Sent: Thursday, June 21, 2012 4:20 PM
To: general-community@community.qnx.com
Cc: srilakshmi; srilakshmi
Subject: Re: PCI Express
srilakshmi wrote:
How to enable the interrupt line?
Your basically problem is that the board (FPGA core?) doesn't initialize at
hardware level the PCI interface.
The configuration data of the PCI interfaces are normaly provided by a
serial ROM.
Please checkout why the PCI interface isn't initialized!
Nothing can be done with an uninitialized PCI interface ...
--Armin
Please provide me sample code or document or explanaion
From: Armin Steinhoff [mailto:community-noreply@qnx.com]
Sent: Thursday, June 21, 2012 2:08 PM
To: general-community@community.qnx.com
Cc: srilakshmi; srilakshmi
Subject: Re: PCI Express
srilakshmi wrote:
Through the attached file I am sending the output of pci -vvv.
My project board contains both Intel chip and FPGA chip on same board.
through PCI express slot we are connecting Xilinx board. Through PCIe we are
communicating with each other. And the result is checking at FPGA side by
Chipscope software.
Ok ... and this is a board from Xilinx with the vendor ID 10EEh ??
This board seems to be completely disabled ...
No I/O memory, no memory, no connection to an interrupt line.
Also the memory of 128 bytes referenced by BAR[0] is disabled !
Please see the marks at the printouts of the "pci" command:
Vendor ID = 10eeh, Xilinx Corporation
Device ID = 7h, Unknown Unknown
PCI index = 0h
Class Codes = 050000h
Revision ID = 0h
Bus number = 2
Device number = 0
Function num = 0
Status Reg = 10h
Command Reg = 0h
I/O space access disabled <<<============ !!!
Memory space access disabled <<<============ !!!
Bus Master disabled
Special Cycle operations ignored
Memory Write and Invalidate disabled <<<============ !!!
Palette Snooping disabled
Parity Error Response disabled
Data/Address stepping disabled
SERR# driver disabled
Fast back-to-back transactions to different agents disabled
PCI INTx enabled
Header type = 0h Single-function
BIST = 0h Build-in-self-test not supported
Latency Timer = 0h
Cache Line Size= 0h
BAR - 0 [Mem] = 0h 32bit length 128 disabled <<<========= !!!
Subsystem Vendor ID = 10eeh
Subsystem ID = 7h
Max Lat = 0ns
Min Gnt = 0ns
PCI Int Pin = INT A
Interrupt line = no connection <<<========== !!!
And the previous which you have sent to me is not working because
pci_dev_info predefined structure doesn't contain members like HeaderType,
CpuBmstrTranslation, CpuIsaTranslation, CpuMemTranslation, NumIrq,
info.MsiDefs[i].count
The example code previously posted by Hugh Brown is for QNX 6.5.
Are you working with QNX 6.4.x ??
Best Regards
--Armin
http://www.steinhoff-automation.com
Srilakshmi
-----Original Message-----
From: Armin Steinhoff [mailto:community-noreply@qnx.com]
Sent: Wednesday, June 20, 2012 11:59 PM
To: general-community@community.qnx.com
Cc: srilakshmi; srilakshmi
Subject: Re: PCI Express
srilakshmi wrote:
How to recognize interrupts coming from FPGA through PCI?
is this a board with a PCI interface together with separate FPGA chip??
Or is the PCI interface realized as a core of the FPGA?
Could you post the output of "pci -vvv" ?
Please provide me
document or code regarding this.
_______________________________________________
General
http://community.qnx.com/sf/go/post93788
To cancel your subscription to this discussion, please e-mail
general-community-unsubscribe@community.qnx.com
-----
No...
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06/21/2012 7:36 AM
post93806
|
srilakshmi wrote:
>
> When I am executing above attached code I am getting configuration data..
>
Yes ... but you are reading configuration data from an uninitialzed
device which provides invalid data.
Just some comments about your code:
pci_read_config32(2,0,0x04,10,&buf); --> why not are
inf.BusNumber and inf. DevFunc not used ?
You have to check the memory type by PCI_IS_MEM() before you use
PCI_MEM_ADDR( )
It's not a good idea to map an IO address into normal memory.
If you have a support contract ... go back to QNX 6.4.1.
--Armin
> *From:*Armin Steinhoff [mailto:community-noreply@qnx.com]
> *Sent:* Thursday, June 21, 2012 4:20 PM
> *To:* general-community@community.qnx.com
> *Cc:* srilakshmi; srilakshmi
> *Subject:* Re: PCI Express
>
> srilakshmi wrote:
>
> How to enable the interrupt line?
>
>
> Your basically problem is that the board (FPGA core?) doesn't
> initialize at hardware level the PCI interface.
> The configuration data of the PCI interfaces are normaly provided by a
> serial ROM.
> Please checkout why the PCI interface isn't initialized!
>
> Nothing can be done with an uninitialized PCI interface ...
>
> --Armin
>
>
>
>
> Please provide me sample code or document or explanaion
>
> *From:*Armin Steinhoff [mailto:community-noreply@qnx.com]
> *Sent:* Thursday, June 21, 2012 2:08 PM
> *To:* general-community@community.qnx.com
> <mailto:general-community@community.qnx.com>;
> *Cc:* srilakshmi; srilakshmi
> *Subject:* Re: PCI Express
>
> srilakshmi wrote:
>
> Through the attached file I am sending the output of pci -vvv.
> My project board contains both Intel chip and FPGA chip on same board.
> through PCI express slot we are connecting Xilinx board. Through PCIe we are
> communicating with each other. And the result is checking at FPGA side by
> Chipscope software.
>
>
> Ok ... and this is a board from Xilinx with the vendor ID 10EEh ??
>
> This board seems to be completely disabled ...
> No I/O memory, no memory, no connection to an interrupt line.
> Also the memory of 128 bytes referenced by BAR[0] is disabled !
>
> Please see the marks at the printouts of the "pci" command:
>
> Vendor ID = 10eeh, Xilinx Corporation
> Device ID = 7h, Unknown Unknown
> PCI index = 0h
> Class Codes = 050000h
> Revision ID = 0h
> Bus number = 2
> Device number = 0
> Function num = 0
> Status Reg = 10h
> Command Reg = 0h
> I/O space access *disabled* <<<============ !!!
> Memory space access *disabled* <<<============ !!!
> Bus Master disabled
> Special Cycle operations ignored
> Memory Write and Invalidate *disabled* <<<============ !!!
> Palette Snooping disabled
> Parity Error Response disabled
> Data/Address stepping disabled
> SERR# driver disabled
> Fast back-to-back transactions to different agents disabled
> PCI INTx enabled
> Header type = 0h Single-function
> BIST = 0h Build-in-self-test not supported
> Latency Timer = 0h
> Cache Line Size= 0h
> BAR - 0 [Mem] = 0h 32bit length 128 *disabled* <<<========= !!!
> Subsystem Vendor ID = 10eeh
> Subsystem ID = 7h
> Max Lat = 0ns
> Min Gnt = 0ns
> PCI Int Pin = INT A
> Interrupt line = *no connection* <<<========== !!!
>
>
>
>
>
> And the previous which you have sent to me is not working because
> pci_dev_info predefined structure doesn't contain members like HeaderType,
> CpuBmstrTranslation, CpuIsaTranslation, CpuMemTranslation, NumIrq,
> info.MsiDefs[i].count
>
>
> The example code...
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06/21/2012 7:55 AM
post93808
|
But at FPGA side they receiving data through this code
From: Armin Steinhoff [mailto:community-noreply@qnx.com]
Sent: Thursday, June 21, 2012 5:08 PM
To: general-community@community.qnx.com
Cc: srilakshmi; srilakshmi
Subject: Re: PCI Express
srilakshmi wrote:
When I am executing above attached code I am getting configuration data..
Yes ... but you are reading configuration data from an uninitialzed device
which provides invalid data.
Just some comments about your code:
pci_read_config32(2,0,0x04,10,&buf); --> why not are inf.BusNumber and
inf. DevFunc not used ?
You have to check the memory type by PCI_IS_MEM() before you use
PCI_MEM_ADDR( )
It's not a good idea to map an IO address into normal memory.
If you have a support contract ... go back to QNX 6.4.1.
--Armin
From: Armin Steinhoff [mailto:community-noreply@qnx.com]
Sent: Thursday, June 21, 2012 4:20 PM
To: general-community@community.qnx.com
Cc: srilakshmi; srilakshmi
Subject: Re: PCI Express
srilakshmi wrote:
How to enable the interrupt line?
Your basically problem is that the board (FPGA core?) doesn't initialize at
hardware level the PCI interface.
The configuration data of the PCI interfaces are normaly provided by a
serial ROM.
Please checkout why the PCI interface isn't initialized!
Nothing can be done with an uninitialized PCI interface ...
--Armin
Please provide me sample code or document or explanaion
From: Armin Steinhoff [mailto:community-noreply@qnx.com]
Sent: Thursday, June 21, 2012 2:08 PM
To: general-community@community.qnx.com
Cc: srilakshmi; srilakshmi
Subject: Re: PCI Express
srilakshmi wrote:
Through the attached file I am sending the output of pci -vvv.
My project board contains both Intel chip and FPGA chip on same board.
through PCI express slot we are connecting Xilinx board. Through PCIe we are
communicating with each other. And the result is checking at FPGA side by
Chipscope software.
Ok ... and this is a board from Xilinx with the vendor ID 10EEh ??
This board seems to be completely disabled ...
No I/O memory, no memory, no connection to an interrupt line.
Also the memory of 128 bytes referenced by BAR[0] is disabled !
Please see the marks at the printouts of the "pci" command:
Vendor ID = 10eeh, Xilinx Corporation
Device ID = 7h, Unknown Unknown
PCI index = 0h
Class Codes = 050000h
Revision ID = 0h
Bus number = 2
Device number = 0
Function num = 0
Status Reg = 10h
Command Reg = 0h
I/O space access disabled <<<============ !!!
Memory space access disabled <<<============ !!!
Bus Master disabled
Special Cycle operations ignored
Memory Write and Invalidate disabled <<<============ !!!
Palette Snooping disabled
Parity Error Response disabled
Data/Address stepping disabled
SERR# driver disabled
Fast back-to-back transactions to different agents disabled
PCI INTx enabled
Header type = 0h Single-function
BIST = 0h Build-in-self-test not supported
Latency Timer = 0h
Cache Line Size= 0h
BAR - 0 [Mem] = 0h 32bit length 128 disabled <<<========= !!!
Subsystem Vendor ID = 10eeh
Subsystem ID = 7h
Max Lat = 0ns
Min Gnt = 0ns
PCI Int Pin = INT A
Interrupt line = no connection <<<========== !!!
And the previous which you have sent to me is not working because
pci_dev_info predefined structure doesn't contain members like HeaderType,
CpuBmstrTranslation, CpuIsaTranslation, CpuMemTranslation, NumIrq,
info.MsiDefs[i].count
The example code previously posted by Hugh Brown is for QNX 6.5.
Are you working with QNX 6.4.x ??
Best Regards
--Armin
http://www.steinhoff-automation.com
Srilakshmi
-----Original...
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06/21/2012 7:59 AM
post93809
|
We used pci_read_config32(2,0,0x04,10,&buf); for enabling DMA master to
transfer data to FPGA
From: Armin Steinhoff [mailto:community-noreply@qnx.com]
Sent: Thursday, June 21, 2012 5:08 PM
To: general-community@community.qnx.com
Cc: srilakshmi; srilakshmi
Subject: Re: PCI Express
srilakshmi wrote:
When I am executing above attached code I am getting configuration data..
Yes ... but you are reading configuration data from an uninitialzed device
which provides invalid data.
Just some comments about your code:
pci_read_config32(2,0,0x04,10,&buf); --> why not are inf.BusNumber and
inf. DevFunc not used ?
You have to check the memory type by PCI_IS_MEM() before you use
PCI_MEM_ADDR( )
It's not a good idea to map an IO address into normal memory.
If you have a support contract ... go back to QNX 6.4.1.
--Armin
From: Armin Steinhoff [mailto:community-noreply@qnx.com]
Sent: Thursday, June 21, 2012 4:20 PM
To: general-community@community.qnx.com
Cc: srilakshmi; srilakshmi
Subject: Re: PCI Express
srilakshmi wrote:
How to enable the interrupt line?
Your basically problem is that the board (FPGA core?) doesn't initialize at
hardware level the PCI interface.
The configuration data of the PCI interfaces are normaly provided by a
serial ROM.
Please checkout why the PCI interface isn't initialized!
Nothing can be done with an uninitialized PCI interface ...
--Armin
Please provide me sample code or document or explanaion
From: Armin Steinhoff [mailto:community-noreply@qnx.com]
Sent: Thursday, June 21, 2012 2:08 PM
To: general-community@community.qnx.com
Cc: srilakshmi; srilakshmi
Subject: Re: PCI Express
srilakshmi wrote:
Through the attached file I am sending the output of pci -vvv.
My project board contains both Intel chip and FPGA chip on same board.
through PCI express slot we are connecting Xilinx board. Through PCIe we are
communicating with each other. And the result is checking at FPGA side by
Chipscope software.
Ok ... and this is a board from Xilinx with the vendor ID 10EEh ??
This board seems to be completely disabled ...
No I/O memory, no memory, no connection to an interrupt line.
Also the memory of 128 bytes referenced by BAR[0] is disabled !
Please see the marks at the printouts of the "pci" command:
Vendor ID = 10eeh, Xilinx Corporation
Device ID = 7h, Unknown Unknown
PCI index = 0h
Class Codes = 050000h
Revision ID = 0h
Bus number = 2
Device number = 0
Function num = 0
Status Reg = 10h
Command Reg = 0h
I/O space access disabled <<<============ !!!
Memory space access disabled <<<============ !!!
Bus Master disabled
Special Cycle operations ignored
Memory Write and Invalidate disabled <<<============ !!!
Palette Snooping disabled
Parity Error Response disabled
Data/Address stepping disabled
SERR# driver disabled
Fast back-to-back transactions to different agents disabled
PCI INTx enabled
Header type = 0h Single-function
BIST = 0h Build-in-self-test not supported
Latency Timer = 0h
Cache Line Size= 0h
BAR - 0 [Mem] = 0h 32bit length 128 disabled <<<========= !!!
Subsystem Vendor ID = 10eeh
Subsystem ID = 7h
Max Lat = 0ns
Min Gnt = 0ns
PCI Int Pin = INT A
Interrupt line = no connection <<<========== !!!
And the previous which you have sent to me is not working because
pci_dev_info predefined structure doesn't contain members like HeaderType,
CpuBmstrTranslation, CpuIsaTranslation, CpuMemTranslation, NumIrq,
info.MsiDefs[i].count
The example code previously posted by Hugh Brown is for QNX 6.5.
Are you working with QNX 6.4.x ??
Best Regards
--Armin
http://www.steinhoff-automation.com
...
View Full Message
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06/21/2012 9:02 AM
post93810
|
srilakshmi wrote:
>
> We used pci_read_config32(2,0,0x04,10,&buf); for enabling DMA master
> to transfer data to FPGA
>
pci_read_config32(2,0,0x04,10,&buf); reads the following members of the
config space:
uint16_t Command; /* 0x04 */
uint16_t Status; /* 0x06 */
uint8_t Revision_ID; /* 0x08 */
uint8_t Class_Code[3]; /* 0x09 */
uint8_t Cache_Line_Size; /* 0x0C */
uint8_t Latency_Timer; /* 0x0D */
uint8_t Header_Type; /* 0x0E */
uint8_t BIST; /* 0x0F */
uint32_t Base_Address_Regs[6]; /* 0x10 */
uint32_t CardBus_CIS; /* 0x28 */
uint16_t Sub_Vendor_ID; /* 0x2C */
I don't know why reading the config space beginning at offset 0x04
should enable DMA processing ??
That's plain nonsens. Does your PCI interface really support DMA to an
asigned piece of memory ??
if you want to do DMA you have to run the PCI adapter at least as bus
master
hdl = pci_attach_device( NULL, PCI_INIT_ALL, pidx, &inf ); -->
hdl = pci_attach_device (NULL, PCI_INIT_ALL | PCI_INIT_ROM | PCI_PERSIST
| PCI_MASTER_ENABLE ,pidx, &inf);
--Armin
> *From:*Armin Steinhoff [mailto:community-noreply@qnx.com]
> *Sent:* Thursday, June 21, 2012 5:08 PM
> *To:* general-community@community.qnx.com
> *Cc:* srilakshmi; srilakshmi
> *Subject:* Re: PCI Express
>
> srilakshmi wrote:
>
> When I am executing above attached code I am getting configuration data..
>
>
> Yes ... but you are reading configuration data from an uninitialzed
> device which provides invalid data.
> Just some comments about your code:
>
> pci_read_config32(2,0,0x04,10,&buf); --> why not are
> inf.BusNumber and inf. DevFunc not used ?
>
> You have to check the memory type by PCI_IS_MEM() before you use
> PCI_MEM_ADDR( )
> It's not a good idea to map an IO address into normal memory.
>
> If you have a support contract ... go back to QNX 6.4.1.
>
> --Armin
>
>
>
> *From:*Armin Steinhoff [mailto:community-noreply@qnx.com]
> *Sent:* Thursday, June 21, 2012 4:20 PM
> *To:* general-community@community.qnx.com
> <mailto:general-community@community.qnx.com>;
> *Cc:* srilakshmi; srilakshmi
> *Subject:* Re: PCI Express
>
> srilakshmi wrote:
>
> How to enable the interrupt line?
>
>
> Your basically problem is that the board (FPGA core?) doesn't
> initialize at hardware level the PCI interface.
> The configuration data of the PCI interfaces are normaly provided by a
> serial ROM.
> Please checkout why the PCI interface isn't initialized!
>
> Nothing can be done with an uninitialized PCI interface ...
>
> --Armin
>
>
>
>
>
> Please provide me sample code or document or explanaion
>
> *From:*Armin Steinhoff [mailto:community-noreply@qnx.com]
> *Sent:* Thursday, June 21, 2012 2:08 PM
> *To:* general-community@community.qnx.com
> <mailto:general-community@community.qnx.com>;
> *Cc:* srilakshmi; srilakshmi
> *Subject:* Re: PCI Express
>
> srilakshmi wrote:
>
> Through the attached file I am sending the output of pci -vvv.
> My project board contains both Intel chip and FPGA chip on same board.
> through PCI express slot we are connecting Xilinx board. Through PCIe we are
> communicating with each other. And the result is checking at FPGA side by
> Chipscope software.
>
>
> Ok ... and this is a board from Xilinx with the vendor ID 10EEh...
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06/28/2012 5:47 AM
post93917
|
Through the attachment I am sending output of pci -vvv command.
Now I need to enable interrupt.
You please provide me sample code for interrupts(functions for interrupts
are like InterruptAttach(),InterruptAttachEvent(),Interruptdetach,).
I am using QNX 6.5.0
From: Armin Steinhoff [mailto:community-noreply@qnx.com]
Sent: Thursday, June 21, 2012 6:35 PM
To: general-community@community.qnx.com
Cc: srilakshmi; srilakshmi
Subject: Re: PCI Express
srilakshmi wrote:
We used pci_read_config32(2,0,0x04,10,&buf); for enabling DMA master to
transfer data to FPGA
pci_read_config32(2,0,0x04,10,&buf); reads the following members of the
config space:
uint16_t Command; /* 0x04 */
uint16_t Status; /* 0x06 */
uint8_t Revision_ID; /* 0x08 */
uint8_t Class_Code[3]; /* 0x09 */
uint8_t Cache_Line_Size; /* 0x0C */
uint8_t Latency_Timer; /* 0x0D */
uint8_t Header_Type; /* 0x0E */
uint8_t BIST; /* 0x0F */
uint32_t Base_Address_Regs[6]; /* 0x10 */
uint32_t CardBus_CIS; /* 0x28 */
uint16_t Sub_Vendor_ID; /* 0x2C */
I don't know why reading the config space beginning at offset 0x04 should
enable DMA processing ??
That's plain nonsens. Does your PCI interface really support DMA to an
asigned piece of memory ??
if you want to do DMA you have to run the PCI adapter at least as bus master
hdl = pci_attach_device( NULL, PCI_INIT_ALL, pidx, &inf ); --> hdl =
pci_attach_device (NULL, PCI_INIT_ALL | PCI_INIT_ROM | PCI_PERSIST |
PCI_MASTER_ENABLE ,pidx, &inf);
--Armin
From: Armin Steinhoff [mailto:community-noreply@qnx.com]
Sent: Thursday, June 21, 2012 5:08 PM
To: general-community@community.qnx.com
Cc: srilakshmi; srilakshmi
Subject: Re: PCI Express
srilakshmi wrote:
When I am executing above attached code I am getting configuration data..
Yes ... but you are reading configuration data from an uninitialzed device
which provides invalid data.
Just some comments about your code:
pci_read_config32(2,0,0x04,10,&buf); --> why not are inf.BusNumber and
inf. DevFunc not used ?
You have to check the memory type by PCI_IS_MEM() before you use
PCI_MEM_ADDR( )
It's not a good idea to map an IO address into normal memory.
If you have a support contract ... go back to QNX 6.4.1.
--Armin
From: Armin Steinhoff [mailto:community-noreply@qnx.com]
Sent: Thursday, June 21, 2012 4:20 PM
To: general-community@community.qnx.com
Cc: srilakshmi; srilakshmi
Subject: Re: PCI Express
srilakshmi wrote:
How to enable the interrupt line?
Your basically problem is that the board (FPGA core?) doesn't initialize at
hardware level the PCI interface.
The configuration data of the PCI interfaces are normaly provided by a
serial ROM.
Please checkout why the PCI interface isn't initialized!
Nothing can be done with an uninitialized PCI interface ...
--Armin
Please provide me sample code or document or explanaion
From: Armin Steinhoff [mailto:community-noreply@qnx.com]
Sent: Thursday, June 21, 2012 2:08 PM
To: general-community@community.qnx.com
Cc: srilakshmi; srilakshmi
Subject: Re: PCI Express
srilakshmi wrote:
Through the attached file I am sending the output of pci -vvv.
My project board contains both Intel chip and FPGA chip on same board.
through PCI express slot we are connecting Xilinx board. Through PCIe we are
communicating with each other. And the result is checking at FPGA side by
Chipscope software.
Ok ... and this is a board from Xilinx with the...
View Full Message
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06/28/2012 8:59 AM
post93919
|
Congratulation ! The PCI device is now in a good state !!
http://www.qnx.com/developers/docs/6.5.0/topic/com.qnx.doc.neutrino_prog/inthandler.html
--Armin
srilakshmi wrote:
>
> Through the attachment I am sending output of pci --vvv command.
>
> Now I need to enable interrupt.
>
> You please provide me sample code for interrupts(functions for
> interrupts are like
> InterruptAttach(),InterruptAttachEvent(),Interruptdetach,).
>
> I am using QNX 6.5.0
>
> *From:*Armin Steinhoff [mailto:community-noreply@qnx.com]
> *Sent:* Thursday, June 21, 2012 6:35 PM
> *To:* general-community@community.qnx.com
> *Cc:* srilakshmi; srilakshmi
> *Subject:* Re: PCI Express
>
> srilakshmi wrote:
>
> We used pci_read_config32(2,0,0x04,10,&buf); for enabling DMA master
> to transfer data to FPGA
>
>
> pci_read_config32(2,0,0x04,10,&buf); reads the following members of
> the config space:
>
> uint16_t Command; /* 0x04 */
> uint16_t Status; /* 0x06 */
> uint8_t Revision_ID; /* 0x08 */
> uint8_t Class_Code[3]; /* 0x09 */
> uint8_t Cache_Line_Size; /* 0x0C */
> uint8_t Latency_Timer; /* 0x0D */
> uint8_t Header_Type; /* 0x0E */
> uint8_t BIST; /* 0x0F */
> uint32_t Base_Address_Regs[6]; /* 0x10 */
> uint32_t CardBus_CIS; /* 0x28 */
> uint16_t Sub_Vendor_ID; /* 0x2C */
>
> I don't know why reading the config space beginning at offset 0x04
> should enable DMA processing ??
> That's plain nonsens. Does your PCI interface really support DMA to an
> asigned piece of memory ??
>
> if you want to do DMA you have to run the PCI adapter at least as bus
> master
> hdl = pci_attach_device( NULL, PCI_INIT_ALL, pidx, &inf ); -->
> hdl = pci_attach_device (NULL, PCI_INIT_ALL | PCI_INIT_ROM |
> PCI_PERSIST | PCI_MASTER_ENABLE ,pidx, &inf);
>
>
> --Armin
>
>
>
>
> *From:*Armin Steinhoff [mailto:community-noreply@qnx.com]
> *Sent:* Thursday, June 21, 2012 5:08 PM
> *To:* general-community@community.qnx.com
> <mailto:general-community@community.qnx.com>;
> *Cc:* srilakshmi; srilakshmi
> *Subject:* Re: PCI Express
>
> srilakshmi wrote:
>
> When I am executing above attached code I am getting configuration data..
>
>
> Yes ... but you are reading configuration data from an uninitialzed
> device which provides invalid data.
> Just some comments about your code:
>
> pci_read_config32(2,0,0x04,10,&buf); --> why not are
> inf.BusNumber and inf. DevFunc not used ?
>
> You have to check the memory type by PCI_IS_MEM() before you use
> PCI_MEM_ADDR( )
> It's not a good idea to map an IO address into normal memory.
>
> If you have a support contract ... go back to QNX 6.4.1.
>
> --Armin
>
>
>
>
> *From:*Armin Steinhoff [mailto:community-noreply@qnx.com]
> *Sent:* Thursday, June 21, 2012 4:20 PM
> *To:* general-community@community.qnx.com
> <mailto:general-community@community.qnx.com>;
> *Cc:* srilakshmi; srilakshmi
> *Subject:* Re: PCI Express
>
> srilakshmi wrote:
>
> How to enable the interrupt line?
>
>
> Your basically problem is that the board (FPGA core?) doesn't
> initialize at hardware level the PCI interface.
> The configuration data of the PCI interfaces are normaly provided by a
> serial ROM.
> Please checkout why the PCI interface isn't initialized!
>
> Nothing can be done with an uninitialized PCI interface ...
>
> --Armin
>
>
>
>
>
>
> Please provide me sample code or document or explanaion
>
> *From:*Armin Steinhoff...
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06/29/2012 5:20 AM
post93949
|
Through the attachment I am sending new output of pci -vvv command.
FPGA developer has changed some values like Device ID, Irq..
Now my target is interrupts to master FPGA through PCIe.
Will you please provide me guidance / suggestions?
Send me any sample code regarding interrupts.
Thanks & Regards
Srilakshmi
From: Armin Steinhoff [mailto:community-noreply@qnx.com]
Sent: Thursday, June 21, 2012 6:35 PM
To: general-community@community.qnx.com
Cc: srilakshmi; srilakshmi
Subject: Re: PCI Express
srilakshmi wrote:
We used pci_read_config32(2,0,0x04,10,&buf); for enabling DMA master to
transfer data to FPGA
pci_read_config32(2,0,0x04,10,&buf); reads the following members of the
config space:
uint16_t Command; /* 0x04 */
uint16_t Status; /* 0x06 */
uint8_t Revision_ID; /* 0x08 */
uint8_t Class_Code[3]; /* 0x09 */
uint8_t Cache_Line_Size; /* 0x0C */
uint8_t Latency_Timer; /* 0x0D */
uint8_t Header_Type; /* 0x0E */
uint8_t BIST; /* 0x0F */
uint32_t Base_Address_Regs[6]; /* 0x10 */
uint32_t CardBus_CIS; /* 0x28 */
uint16_t Sub_Vendor_ID; /* 0x2C */
I don't know why reading the config space beginning at offset 0x04 should
enable DMA processing ??
That's plain nonsens. Does your PCI interface really support DMA to an
asigned piece of memory ??
if you want to do DMA you have to run the PCI adapter at least as bus master
hdl = pci_attach_device( NULL, PCI_INIT_ALL, pidx, &inf ); --> hdl =
pci_attach_device (NULL, PCI_INIT_ALL | PCI_INIT_ROM | PCI_PERSIST |
PCI_MASTER_ENABLE ,pidx, &inf);
--Armin
From: Armin Steinhoff [mailto:community-noreply@qnx.com]
Sent: Thursday, June 21, 2012 5:08 PM
To: general-community@community.qnx.com
Cc: srilakshmi; srilakshmi
Subject: Re: PCI Express
srilakshmi wrote:
When I am executing above attached code I am getting configuration data..
Yes ... but you are reading configuration data from an uninitialzed device
which provides invalid data.
Just some comments about your code:
pci_read_config32(2,0,0x04,10,&buf); --> why not are inf.BusNumber and
inf. DevFunc not used ?
You have to check the memory type by PCI_IS_MEM() before you use
PCI_MEM_ADDR( )
It's not a good idea to map an IO address into normal memory.
If you have a support contract ... go back to QNX 6.4.1.
--Armin
From: Armin Steinhoff [mailto:community-noreply@qnx.com]
Sent: Thursday, June 21, 2012 4:20 PM
To: general-community@community.qnx.com
Cc: srilakshmi; srilakshmi
Subject: Re: PCI Express
srilakshmi wrote:
How to enable the interrupt line?
Your basically problem is that the board (FPGA core?) doesn't initialize at
hardware level the PCI interface.
The configuration data of the PCI interfaces are normaly provided by a
serial ROM.
Please checkout why the PCI interface isn't initialized!
Nothing can be done with an uninitialized PCI interface ...
--Armin
Please provide me sample code or document or explanaion
From: Armin Steinhoff [mailto:community-noreply@qnx.com]
Sent: Thursday, June 21, 2012 2:08 PM
To: general-community@community.qnx.com
Cc: srilakshmi; srilakshmi
Subject: Re: PCI Express
srilakshmi wrote:
Through the attached file I am sending the output of pci -vvv.
My project board contains both Intel chip and FPGA chip on same board.
through PCI express slot we are connecting Xilinx board. Through PCIe we are
communicating with each other. And the result is checking at FPGA side...
View Full Message
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06/29/2012 10:38 AM
post93951
|
srilakshmi wrote:
>
> Through the attachment I am sending new output of pci --vvv command.
>
> FPGA developer has changed some values like Device ID, Irq....
>
> Now my target is interrupts to master FPGA through PCIe.
>
> Will you please provide me guidance / suggestions?
>
Yes ... but I have no intention to do your job :)
However ... load the example code from:
http://www.qnx.com/download/download/23638/cookbook_code.zip
--Armin
> Send me any sample code regarding interrupts.
>
> Thanks & Regards
>
> Srilakshmi
>
> *From:*Armin Steinhoff [mailto:community-noreply@qnx.com]
> *Sent:* Thursday, June 21, 2012 6:35 PM
> *To:* general-community@community.qnx.com
> *Cc:* srilakshmi; srilakshmi
> *Subject:* Re: PCI Express
>
> srilakshmi wrote:
>
> We used pci_read_config32(2,0,0x04,10,&buf); for enabling DMA master
> to transfer data to FPGA
>
>
> pci_read_config32(2,0,0x04,10,&buf); reads the following members of
> the config space:
>
> uint16_t Command; /* 0x04 */
> uint16_t Status; /* 0x06 */
> uint8_t Revision_ID; /* 0x08 */
> uint8_t Class_Code[3]; /* 0x09 */
> uint8_t Cache_Line_Size; /* 0x0C */
> uint8_t Latency_Timer; /* 0x0D */
> uint8_t Header_Type; /* 0x0E */
> uint8_t BIST; /* 0x0F */
> uint32_t Base_Address_Regs[6]; /* 0x10 */
> uint32_t CardBus_CIS; /* 0x28 */
> uint16_t Sub_Vendor_ID; /* 0x2C */
>
> I don't know why reading the config space beginning at offset 0x04
> should enable DMA processing ??
> That's plain nonsens. Does your PCI interface really support DMA to an
> asigned piece of memory ??
>
> if you want to do DMA you have to run the PCI adapter at least as bus
> master
> hdl = pci_attach_device( NULL, PCI_INIT_ALL, pidx, &inf ); -->
> hdl = pci_attach_device (NULL, PCI_INIT_ALL | PCI_INIT_ROM |
> PCI_PERSIST | PCI_MASTER_ENABLE ,pidx, &inf);
>
>
> --Armin
>
>
>
>
> *From:*Armin Steinhoff [mailto:community-noreply@qnx.com]
> *Sent:* Thursday, June 21, 2012 5:08 PM
> *To:* general-community@community.qnx.com
> <mailto:general-community@community.qnx.com>;
> *Cc:* srilakshmi; srilakshmi
> *Subject:* Re: PCI Express
>
> srilakshmi wrote:
>
> When I am executing above attached code I am getting configuration data..
>
>
> Yes ... but you are reading configuration data from an uninitialzed
> device which provides invalid data.
> Just some comments about your code:
>
> pci_read_config32(2,0,0x04,10,&buf); --> why not are
> inf.BusNumber and inf. DevFunc not used ?
>
> You have to check the memory type by PCI_IS_MEM() before you use
> PCI_MEM_ADDR( )
> It's not a good idea to map an IO address into normal memory.
>
> If you have a support contract ... go back to QNX 6.4.1.
>
> --Armin
>
>
>
>
> *From:*Armin Steinhoff [mailto:community-noreply@qnx.com]
> *Sent:* Thursday, June 21, 2012 4:20 PM
> *To:* general-community@community.qnx.com
> <mailto:general-community@community.qnx.com>;
> *Cc:* srilakshmi; srilakshmi
> *Subject:* Re: PCI Express
>
> srilakshmi wrote:
>
> How to enable the interrupt line?
>
>
> Your basically problem is that the board (FPGA core?) doesn't
> initialize at hardware level the PCI interface.
> The configuration data of the PCI interfaces are normaly provided by a
> serial ROM.
> Please checkout why the PCI interface isn't initialized!
>
> Nothing can be done with an uninitialized PCI interface ...
>
> --Armin
>
>
>
>
>
>
> Please provide me sample code or document...
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06/16/2012 10:09 AM
post93714
|
Srilakshmi,
is the PCI interface realized as a core of the FPGA ?
If yes, do you have the VHDL code of that core?
Or is the PCI interface based on one of these standard chips ? (PLX xxx a.s.o)
Could you post the output of "pci -vvv" ?
What is the functionalty of your board ?
--Armin
http://www.steinhoff-automation.com
srilakshmi wrote:
> We are able to transfer TLP with 1byte of data for Memory write transaction.
> You please help me to send more bytes of data through PCI express from Intel
> to FPGA.
>
> Thanks& Regards
> Srilakshmi
>
> -----Original Message-----
> From: Hugh Brown [mailto:community-noreply@qnx.com]
> Sent: Tuesday, June 05, 2012 5:06 PM
> To: general-community@community.qnx.com
> Subject: Re: PCI Express
>
> As I have said before, I don't know how your FPGA works, so you will have
> to contact whoever designed your FPGA.
>
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06/22/2012 2:57 PM
post93840
|
Are there any plans to implement PCIe support for ARM based platforms?
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06/22/2012 4:46 PM
post93846
|
There is no standard PCIe interface for ARM, so you will have to be more
specific as to what platform you are targeting.
--
Hugh Brown
QNX Software Systems Limited
1001 Farrar Rd.,
Ottawa. ON. K2K 0B3.
Telephone: 613-591-0931
On 12-06-22 2:57 PM, "Bratislav Matic" <community-noreply@qnx.com> wrote:
>Are there any plans to implement PCIe support for ARM based platforms?
>
>
>
>_______________________________________________
>
>General
>http://community.qnx.com/sf/go/post93840
>To cancel your subscription to this discussion, please e-mail
>general-community-unsubscribe@community.qnx.com
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06/30/2012 6:41 AM
post93959
|
Through attachment I am sending output of pci -vvv command.
Would you please help me how to generate interrupts from Intel to master
FPGA through PCI.
Thanks & Regards
Srilakshmi
-----Original Message-----
From: Hugh Brown [mailto:community-noreply@qnx.com]
Sent: Saturday, June 23, 2012 2:10 AM
To: general-community@community.qnx.com
Subject: Re: PCI Express
There is no standard PCIe interface for ARM, so you will have to be more
specific as to what platform you are targeting.
--
Hugh Brown
QNX Software Systems Limited
1001 Farrar Rd.,
Ottawa. ON. K2K 0B3.
Telephone: 613-591-0931
On 12-06-22 2:57 PM, "Bratislav Matic" <community-noreply@qnx.com> wrote:
>Are there any plans to implement PCIe support for ARM based platforms?
>
>
>
>_______________________________________________
>
>General
>http://community.qnx.com/sf/go/post93840
>To cancel your subscription to this discussion, please e-mail
>general-community-unsubscribe@community.qnx.com
_______________________________________________
General
http://community.qnx.com/sf/go/post93846
To cancel your subscription to this discussion, please e-mail
general-community-unsubscribe@community.qnx.com
-----
No virus found in this message.
Checked by AVG - www.avg.com
Version: 2012.0.2177 / Virus Database: 2437/5097 - Release Date: 06/27/12
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07/01/2012 9:38 AM
post93960
|
Wow,
is this a restart of the whole thread ??
Please send me the output of the attached utility lspci created by "lspci -vvvxx" and "lcpci -tv".
It's a port from Linux to QNX 6 ... it doesn't use any QNX specific code :)
Did you download and study the code examples provided be QSS(L) ??
--Armin
> Through attachment I am sending output of pci -vvv command.
> Would you please help me how to generate interrupts from Intel to master
> FPGA through PCI.
>
> Thanks & Regards
> Srilakshmi
>
> -----Original Message-----
> From: Hugh Brown [mailto:community-noreply@qnx.com]
> Sent: Saturday, June 23, 2012 2:10 AM
> To: general-community@community.qnx.com
> Subject: Re: PCI Express
>
> There is no standard PCIe interface for ARM, so you will have to be more
> specific as to what platform you are targeting.
>
> --
> Hugh Brown
> QNX Software Systems Limited
> 1001 Farrar Rd.,
> Ottawa. ON. K2K 0B3.
> Telephone: 613-591-0931
>
>
>
>
>
>
>
> On 12-06-22 2:57 PM, "Bratislav Matic" <community-noreply@qnx.com> wrote:
>
> >Are there any plans to implement PCIe support for ARM based platforms?
> >
> >
> >
> >_______________________________________________
> >
> >General
> >http://community.qnx.com/sf/go/post93840
> >To cancel your subscription to this discussion, please e-mail
> >general-community-unsubscribe@community.qnx.com
>
>
>
>
>
> _______________________________________________
>
> General
> http://community.qnx.com/sf/go/post93846
> To cancel your subscription to this discussion, please e-mail
> general-community-unsubscribe@community.qnx.com
>
> -----
> No virus found in this message.
> Checked by AVG - www.avg.com
> Version: 2012.0.2177 / Virus Database: 2437/5097 - Release Date: 06/27/12
>
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07/01/2012 1:14 PM
post93961
|
> Through attachment I am sending output of pci -vvv command.
> Would you please help me how to generate interrupts from Intel to
> master FPGA through PCI.
>
Are you understanding what is being said over and over. This is a QNX6 forum, most of the questions you asked have
NOTHING do to with QNX. Your questions show a total lack of understanding of the PCI bus and of the device you are
working with. You need to do some reading or asks on different forum.
To contradict what I just said: the Intel cannot send an interrupt signal, there is no interrupt line GOING to the PCI.
If you want to trigger an interrupt internal to the card you would have to write into a register or IO on the card.
Again THIS HAS NOTHING TO DO WITH PCI OR QNX.
> Thanks & Regards
> Srilakshmi
>
> -----Original Message-----
> From: Hugh Brown [mailto:community-noreply@qnx.com]
> Sent: Saturday, June 23, 2012 2:10 AM
> To: general-community@community.qnx.com
> Subject: Re: PCI Express
>
> There is no standard PCIe interface for ARM, so you will have to be
> more specific as to what platform you are targeting.
>
> --
> Hugh Brown
> QNX Software Systems Limited
> 1001 Farrar Rd.,
> Ottawa. ON. K2K 0B3.
> Telephone: 613-591-0931
>
>
>
>
>
>
>
> On 12-06-22 2:57 PM, "Bratislav Matic" <community-noreply@qnx.com> wrote:
>
> >Are there any plans to implement PCIe support for ARM based platforms?
> >
> >
> >
> >_______________________________________________
> >
> >General
> >http://community.qnx.com/sf/go/post93840
> >To cancel your subscription to this discussion, please e-mail
> >general-community-unsubscribe@community.qnx.com
>
>
>
>
>
> _______________________________________________
>
> General
> http://community.qnx.com/sf/go/post93846
> To cancel your subscription to this discussion, please e-mail
> general-community-unsubscribe@community.qnx.com
>
> -----
> No virus found in this message.
> Checked by AVG - www.avg.com
> Version: 2012.0.2177 / Virus Database: 2437/5097 - Release Date:
> 06/27/12
>
_______________________________________________
General
http://community.qnx.com/sf/go/post93960
To cancel your subscription to this discussion, please e-mail general-community-unsubscribe@community.qnx.com
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