The handling of page tables is different for ARMv4/v5 and ARMv6/v7:

- ARMv4/v5 uses the MMU FCSE which has all address spaces in a single
   4GB space, using MVA adjusted by the FCSE PID to provide the illusion
   of separate address spaces.
   This single 4GB space is accessed (by h/w) via TTBR0, and the memmgr
   has internal mappings 0xff80000-0xffbfffff used to manipulate the L2
   tables in that space.
   A context switch just updates the FCSE PID register.

- ARMv6/v7 uses two separate translation spaces:
   . TTBR0 is used for virtual addresses > 0x80000000 (system addresses)
   . TTBR1 is used for virtual addresses < 0x80000000 (user addresses)
   This is configured by startup via the TTBCR register.
   A context switch updates TTBR1 to the one for the user address space

   The 0xff80000-0ffbfffff is used to manipulate page tables accessed
   via the TTBR0 mappings (so in reality the first 2MB of this is unused).

   The 0xfc00000-0xfc1ffff is used to manipulate page tables accessed
   via the TTBR1 mappings. These mappings change on a context switch.

One day I might get
	Sunil.

Xiongwei Huang wrote:
> Hi all
>      I look at the /usr/include/arm/mmu.h
>      I dong understand about the follow commentary
> 
>  * The virtual address space contains the following reserved regions:
>  *      ff800000-ffbfffff       maps page tables that map 00000000-ffffffff
>  *      ffff0000-ffff0fff       trap vector table for processors with 
> vector adjust
> 
> and
> 
>  * For ARMv6 processors, there are some additions:
>  *
>  *      fc000000-fc1fffff       maps page tables for user address space 
> on ARMv6
>  *      fc200000-fc3fffff       reserved (mapped by user "page 
> directory" page
>  *      ff000000-ff7fffff       used for message passing
>  *      ffc00000-ffc3ffff       used for cache colour operations
> 
> why the page table map to 2 different address ?
> Is there anything special for user address space ?
> what is the different between FF800000 AND FC000000 ?
> 
> thanks and regards
> 
> 
> 
> _______________________________________________
> 
> OSTech
> http://community.qnx.com/sf/go/post84449
>