MSB | 32 | SOVH | Summary integer overflow high. Set whenever an instruction (except mtspr) sets OVH. SOVH remains set until it is cleared by an mtspr instruction. |
| 33 | OVH | Integer overflow high. An overflow occurred in the upper half of the register while executing an SPE integer instruction. |
| 34 | FGH | Embedded floating-point guard bit high. Floating-point guard bit from the upper half. The value is undefined if the processor takes a floating-point exception due to input error, floating-point overflow, or floating-point underflow. |
| 35 | FXH | Embedded floating-point sticky bit high. Floating bit from the upper half. The value is undefined if the processor takes a floating-point exception due to input error, floating-point overflow or floating-point underflow. |
| 36 | FINVH | Embedded floating-point invalid operation error high. Set when an input value on the high side is a NaN, Inf, or Denorm. Also set on a divide if both the dividend and divisor are zero. |
| 37 | FDBZH | Embedded floating-point divide-by-zero error high. Set if the dividend is non-zero and the divisor is zero. |
| 38 | FUNFH | Embedded floating-point underflow error high. |
| 39 | FOVFH | Embedded floating-point overflow error high. |
| 40 | | Reserved, should be cleared. |
| 41 | | Reserved, should be cleared. |
| 42 | FINXS | Embedded floating-point inexact sticky. FINXS = FINXS | FGH | FXH | FG | FX. |
| 43 | FINVS | Embedded floating-point invalid operation sticky. Location for software to use when implementing true IEEE floating point. |
| 44 | FDBZS | Embedded floating-point divide-by-zero sticky. FDBZS = FDBZS | FDBZH | FDBZ |
| 45 | FUNFS | Embedded floating-point underflow sticky. Storage location for software to use when implementing true IEEE floating point. |
| 46 | FOVFS | Embedded floating-point overflow sticky. Storage location for software to use when implementing true IEEE floating point. |
| 47 | MODE | Embedded floating-point mode (read-only on e500) |
| 48 | SOV | Integer summary overflow. Set whenever an SPE instruction (except mtspr) sets OV. SOV remains set until it is cleared by mtspr[SPEFSCR]. |
| 49 | OV | Integer overflow. An overflow occurred in the lower half of the register while a SPE integer instruction is being executed. |
| 50 | FG | Embedded floating-point guard bit. Floating-point guard bit from the lower half. The value is undefined if the processor takes a floating-point exception due to input error, floating-point overflow, or floating-point underflow. |
| 51 | FX | Embedded floating-point sticky bit. Floating bit from the lower half. The value is undefined if the processor takes a floating-point exception due to input error, floating-point overflow or floating-point underflow. |
| 52 | FINV | Embedded floating-point invalid operation error. Set when an input value on the high side is a NaN, Inf, or Denorm. Also set on a divide if both the dividend and divisor are zero. |
| 53 | FDBZ | Embedded floating-point divide-by-zero error. Set if the dividend is non-zero and the divisor is zero. |
| 54 | FUNF | Embedded floating-point underflow error |
| 55 | FOVF | Embedded floating-point overflow error |
| 56 | | Reserved, should be cleared. |
| 57 | FINXE | Embedded floating-point inexact enable |
| 58 | FINVE | Embedded floating-point invalid operation/input error exception enable.
0 | Exception disabled |
1 | Exception enabled. a floating-point data exception is taken if FINX or FINXH is set by a floating-point instruction. |
|
| 59 | FDBZE | Embedded floating-point divide-by-zero exception enable
0 | Exception disabled |
1 | Exception enabled. a floating-point data exception is taken if FDBZ or FDBZH is set by a floating-point instruction. |
|
| 60 | FUNFE | Embedded floating-point underflow exception enable
0 | Exception disabled |
1 | Exception enabled. a floating-point data exception is taken if FUNF or FUNFH is set by a floating-point instruction. |
|
| 61 | FOVFE | Embedded floating-point overflow exception enable
0 | Exception disabled |
1 | Exception enabled. a floating-point data exception is taken if FOVF or FOVFH is set by a floating-point instruction. |
|
| 62-63 | FRMC | Embedded floating-point rounding mode control
00 | Round to nearest |
01 | Round toward zero |
10 | Round toward +infinity |
11 | Round toward -infinity |
|