Mar 08 11:46:26.018 pci_server.3 0 -----ONLINE----- Mar 08 11:46:26.018 pci_server.3 pci_log* 0 INFO ,1,0,3 [3:1]: SLOG module load successful for pid 3 (pci-server) Mar 08 11:46:26.018 pci_server.3 pci_log 0 INFO ,1,-10,3 [3:1]: Mar 08 11:46:26.018 pci_server.3 pci_log 0 INFO ,1,-10,3 [3:1]: + PCI Server v2.0 init start + Mar 08 11:46:26.018 pci_server.3 pci_log 0 INFO ,1,0,3 [3:1]: Setting address space enable to ALL Mar 08 11:46:26.018 pci_server.3 pci_log 0 INFO ,1,0,3 [3:1]: ++ Starting enumeration only ++ Mar 08 11:46:26.018 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 0, limit=255, config=false,ari=false) Mar 08 11:46:26.018 pci_server.3 pci_log 0 INFO ,1,0,3 [3:1]: Attempt module load of /lib/dll/pci/pci_hw-Intel_x86.so Mar 08 11:46:26.018 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: RSRCDB: +++ Adding type 4 resource +++ Mar 08 11:46:26.018 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: RSRCDB: type 4 (PCI Mem ASpace), a0000 to fffff, flags: a004 Mar 08 11:46:26.018 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: RSRCDB: +++ Resources added successfully +++ Mar 08 11:46:26.018 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: RSRCDB: +++ Adding type 4 resource +++ Mar 08 11:46:26.018 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: RSRCDB: type 4 (PCI Mem ASpace), 35a00000 to ffffffff, flags: a004 Mar 08 11:46:26.018 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: RSRCDB: +++ Resources added successfully +++ Mar 08 11:46:26.018 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: RSRCDB: +++ Adding type 4 resource +++ Mar 08 11:46:26.018 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: RSRCDB: type 4 (PCI IO ASpace), 0 to ffff, flags: a004 Mar 08 11:46:26.018 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: RSRCDB: +++ Resources added successfully +++ Mar 08 11:46:26.018 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: RSRCDB: +++ Adding type 1 resources +++ Mar 08 11:46:26.018 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: RSRCDB: type 1 (PCI MSG Vectors), ae to fe, flags: a001 Mar 08 11:46:26.018 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: RSRCDB: +++ Resources added successfully +++ Mar 08 11:46:26.018 pci_server.3 pci_log 0 INFO ,1,0,3 [3:1]: Module is compatible with Server ver 2.0 Mar 08 11:46:26.018 pci_server.3 pci_log 0 INFO ,1,0,3 [3:1]: Module is compatible with Library ver 2.0 Mar 08 11:46:26.018 pci_server.3 pci_log 0 INFO ,1,0,3 [3:1]: Module /lib/dll/pci/pci_hw-Intel_x86.so, v2.0 loaded successfully Mar 08 11:46:26.019 pci_server.3..0 0 -----ONLINE----- Mar 08 11:46:26.019 pci_server.3 pci_log 0 INFO ,1,0,3 [3:1]: Attempt module load of /lib/dll/pci/pci_debug2.so Mar 08 11:46:26.019 pci_server.3 pci_log 0 INFO ,1,0,3 [3:1]: Module /lib/dll/pci/pci_debug2.so, v2.0 loaded successfully Mar 08 11:46:26.019 pci_server.3..0 pci_dbg* 0 DEBUG,1,1,3 [3:1]: find_ecam_base(): trying offset 0x60 for vid/did 8086/3e30 Mar 08 11:46:26.019 pci_server.3..0 pci_dbg 0 DEBUG,1,1,3 [3:1]: find_ecam_base(): found ecam base 0xe0000000 Mar 08 11:46:26.019 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: Found device B0:D0:F0 Mar 08 11:46:26.019 pci_server.3..0 pci_dbg 0 DEBUG,1,1,3 [3:1]: **** B0:D0:F0 has ccode 6,0,0 hdrType: 0 Mar 08 11:46:26.019 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: process_cs_overrides(B0:D0:F0), 0 slots Mar 08 11:46:26.019 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: disable_interrupts(B0:D0:F0) Mar 08 11:46:26.019 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: Found device B0:D1:F0 Mar 08 11:46:26.019 pci_server.3..0 pci_dbg 0 DEBUG,1,1,3 [3:1]: **** B0:D1:F0 has ccode 6,4,0 hdrType: 1 Mar 08 11:46:26.019 pci_server.3 pci_log 0 INFO ,1,0,3 [3:1]: Capability modules will be searched for in directory /lib/dll/pci Mar 08 11:46:26.019 pci_server.3 pci_log 0 INFO ,1,0,3 [3:1]: Attempt module load of /lib/dll/pci/pci_cap-0x10-80861901.so Mar 08 11:46:26.019 pci_server.3 pci_log 0 ERROR,0,0,3 [3:1]: dlopen_mod(), dlopen() error: Library cannot be found Mar 08 11:46:26.019 pci_server.3 pci_log 0 INFO ,1,0,3 [3:1]: Re-attempt module load of /lib/dll/pci/pci_cap-0x10.so Mar 08 11:46:26.019 pci_server.3 pci_log 0 INFO ,1,0,3 [3:1]: Module is compatible with Server ver 2.0 Mar 08 11:46:26.019 pci_server.3 pci_log 0 INFO ,1,0,3 [3:1]: Module is compatible with Library ver 2.0 Mar 08 11:46:26.019 pci_server.3 pci_log 0 INFO ,1,0,3 [3:1]: Module /lib/dll/pci/pci_cap-0x10.so, v2.0 loaded successfully Mar 08 11:46:26.019 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: B0:D1:F0 - Check for /lib/dll/pci/pci_cap-0x10-80861901.so ... not found Mar 08 11:46:26.019 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: B0:D1:F0 - Found /lib/dll/pci/pci_cap-0x10.so Mar 08 11:46:26.019 pci_server.3 pci_log 0 INFO ,1,0,3 [3:1]: bridge B0:D1:F0 has 1 slot numbered 1 Mar 08 11:46:26.019 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: process_cs_overrides(B0:D1:F0), 1 slots Mar 08 11:46:26.019 pci_server.3..0 pci_dbg 0 DEBUG,1,0,3 [3:1]: Added entries for 1 slots Mar 08 11:46:26.019 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:1]: bridge B0:D1:F0 parent bridge is B0:D0:F0 Mar 08 11:46:26.019 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: B0:D1:F0 - Check for /lib/dll/pci/pci_cap-0x10-80861901.so ... not found Mar 08 11:46:26.019 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: B0:D1:F0 - Found /lib/dll/pci/pci_cap-0x10.so Mar 08 11:46:26.019 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:1]: B0:D1:F0 adds 0/0/0 to bridge B0:D1:F0 for a total of 0/0/0 Mar 08 11:46:26.019 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:1]: cached_param_set_pri_busnum(807a8f0, 0, T) Mar 08 11:46:26.019 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:1]: cached_param_set_sec_busnum(807a8f0, 1, T) Mar 08 11:46:26.019 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:1]: cached_param_set_sub_busnum(807a8f0, 1, T) Mar 08 11:46:26.019 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 1, limit=255, config=false,ari=false) Mar 08 11:46:26.019 pci_server.3..0 pci_dbg 0 DEBUG,1,1,3 [3:1]: Lookup of server sym find_parent_bridge ok Mar 08 11:46:26.019 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: Found device B1:D0:F0 Mar 08 11:46:26.019 pci_server.3..0 pci_dbg 0 DEBUG,1,1,3 [3:1]: **** B1:D0:F0 has ccode ff,0,0 hdrType: 0 Mar 08 11:46:26.019 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: B1:D0:F0 - Check for /lib/dll/pci/pci_cap-0x10-1bee001e.so ... not found Mar 08 11:46:26.019 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: B1:D0:F0 - Found /lib/dll/pci/pci_cap-0x10.so Mar 08 11:46:26.019 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:1]: device B1:D0:F0 parent bridge is B0:D1:F0 Mar 08 11:46:26.019 pci_server.3 pci_log 0 INFO ,1,0,3 [3:1]: B1:D0:F0 in chassis/slot 0/1 Mar 08 11:46:26.019 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:1]: B1:D0:F0 adds 0/10000/0 to bridge B0:D1:F0 for a total of 0/10000/0 Mar 08 11:46:26.019 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: disable_interrupts(B1:D0:F0) Mar 08 11:46:26.019 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: disable_interrupts(B0:D1:F0) Mar 08 11:46:26.019 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: Found device B0:D18:F0 Mar 08 11:46:26.019 pci_server.3..0 pci_dbg 0 DEBUG,1,1,3 [3:1]: **** B0:D18:F0 has ccode 11,80,0 hdrType: 0 Mar 08 11:46:26.019 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:1]: device B0:D18:F0 parent bridge is B0:D0:F0 Mar 08 11:46:26.019 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:1]: B0:D18:F0 adds 0/1000/0 to bridge B0:D0:F0 for a total of 0/1000/0 Mar 08 11:46:26.019 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: disable_interrupts(B0:D18:F0) Mar 08 11:46:26.019 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: Found device B0:D20:F0 Mar 08 11:46:26.019 pci_server.3..0 pci_dbg 0 DEBUG,1,1,3 [3:1]: **** B0:D20:F0 has ccode c,3,30 hdrType: 0 Mar 08 11:46:26.020 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:1]: device B0:D20:F0 parent bridge is B0:D0:F0 Mar 08 11:46:26.020 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:1]: B0:D20:F0 adds 0/10000/0 to bridge B0:D0:F0 for a total of 0/11000/0 Mar 08 11:46:26.020 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: disable_interrupts(B0:D20:F0) Mar 08 11:46:26.020 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: Found device B0:D20:F2 Mar 08 11:46:26.020 pci_server.3..0 pci_dbg 0 DEBUG,1,1,3 [3:1]: **** B0:D20:F2 has ccode 5,0,0 hdrType: 0 Mar 08 11:46:26.020 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:1]: device B0:D20:F2 parent bridge is B0:D0:F0 Mar 08 11:46:26.020 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:1]: B0:D20:F2 adds 0/3000/0 to bridge B0:D0:F0 for a total of 0/14000/0 Mar 08 11:46:26.020 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: disable_interrupts(B0:D20:F2) Mar 08 11:46:26.020 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: Found device B0:D22:F0 Mar 08 11:46:26.020 pci_server.3..0 pci_dbg 0 DEBUG,1,1,3 [3:1]: **** B0:D22:F0 has ccode 7,80,0 hdrType: 0 Mar 08 11:46:26.020 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:1]: device B0:D22:F0 parent bridge is B0:D0:F0 Mar 08 11:46:26.020 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:1]: B0:D22:F0 adds 0/1000/0 to bridge B0:D0:F0 for a total of 0/15000/0 Mar 08 11:46:26.020 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: disable_interrupts(B0:D22:F0) Mar 08 11:46:26.020 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: Found device B0:D23:F0 Mar 08 11:46:26.020 pci_server.3..0 pci_dbg 0 DEBUG,1,1,3 [3:1]: **** B0:D23:F0 has ccode 1,6,1 hdrType: 0 Mar 08 11:46:26.020 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:1]: device B0:D23:F0 parent bridge is B0:D0:F0 Mar 08 11:46:26.020 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:1]: B0:D23:F0 adds 0/2900/40 to bridge B0:D0:F0 for a total of 0/17900/40 Mar 08 11:46:26.020 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: disable_interrupts(B0:D23:F0) Mar 08 11:46:26.020 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: Found device B0:D27:F0 Mar 08 11:46:26.020 pci_server.3..0 pci_dbg 0 DEBUG,1,1,3 [3:1]: **** B0:D27:F0 has ccode 6,4,0 hdrType: 1 Mar 08 11:46:26.020 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: B0:D27:F0 - Check for /lib/dll/pci/pci_cap-0x10-8086a340.so ... not found Mar 08 11:46:26.020 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: B0:D27:F0 - Found /lib/dll/pci/pci_cap-0x10.so Mar 08 11:46:26.020 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: process_cs_overrides(B0:D27:F0), 0 slots Mar 08 11:46:26.020 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:1]: bridge B0:D27:F0 parent bridge is B0:D0:F0 Mar 08 11:46:26.020 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: B0:D27:F0 - Check for /lib/dll/pci/pci_cap-0x10-8086a340.so ... not found Mar 08 11:46:26.020 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: B0:D27:F0 - Found /lib/dll/pci/pci_cap-0x10.so Mar 08 11:46:26.020 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:1]: B0:D27:F0 adds 0/0/0 to bridge B0:D27:F0 for a total of 0/0/0 Mar 08 11:46:26.020 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:1]: cached_param_set_pri_busnum(8079648, 0, T) Mar 08 11:46:26.020 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:1]: cached_param_set_sec_busnum(8079648, 2, T) Mar 08 11:46:26.020 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:1]: cached_param_set_sub_busnum(8079648, 2, T) Mar 08 11:46:26.020 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 2, limit=255, config=false,ari=false) Mar 08 11:46:26.020 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: disable_interrupts(B0:D27:F0) Mar 08 11:46:26.020 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: Found device B0:D27:F4 Mar 08 11:46:26.020 pci_server.3..0 pci_dbg 0 DEBUG,1,1,3 [3:1]: **** B0:D27:F4 has ccode 6,4,0 hdrType: 1 Mar 08 11:46:26.020 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: B0:D27:F4 - Check for /lib/dll/pci/pci_cap-0x10-8086a32c.so ... not found Mar 08 11:46:26.020 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: B0:D27:F4 - Found /lib/dll/pci/pci_cap-0x10.so Mar 08 11:46:26.020 pci_server.3 pci_log 0 INFO ,1,0,3 [3:1]: bridge B0:D27:F4 has 1 slot numbered 24 Mar 08 11:46:26.020 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: process_cs_overrides(B0:D27:F4), 1 slots Mar 08 11:46:26.020 pci_server.3..0 pci_dbg 0 DEBUG,1,0,3 [3:1]: Added entries for 1 slots Mar 08 11:46:26.020 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:1]: bridge B0:D27:F4 parent bridge is B0:D0:F0 Mar 08 11:46:26.020 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: B0:D27:F4 - Check for /lib/dll/pci/pci_cap-0x10-8086a32c.so ... not found Mar 08 11:46:26.020 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: B0:D27:F4 - Found /lib/dll/pci/pci_cap-0x10.so Mar 08 11:46:26.020 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:1]: B0:D27:F4 adds 0/0/0 to bridge B0:D27:F4 for a total of 0/0/0 Mar 08 11:46:26.020 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:1]: cached_param_set_pri_busnum(80792c0, 0, T) Mar 08 11:46:26.020 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:1]: cached_param_set_sec_busnum(80792c0, 3, T) Mar 08 11:46:26.020 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:1]: cached_param_set_sub_busnum(80792c0, 3, T) Mar 08 11:46:26.020 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 3, limit=255, config=false,ari=false) Mar 08 11:46:26.020 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: Found device B3:D0:F0 Mar 08 11:46:26.020 pci_server.3..0 pci_dbg 0 DEBUG,1,1,3 [3:1]: **** B3:D0:F0 has ccode 3,0,0 hdrType: 0 Mar 08 11:46:26.020 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: B3:D0:F0 - Check for /lib/dll/pci/pci_cap-0x10-10de128b.so ... not found Mar 08 11:46:26.020 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: B3:D0:F0 - Found /lib/dll/pci/pci_cap-0x10.so Mar 08 11:46:26.020 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:1]: device B3:D0:F0 parent bridge is B0:D27:F4 Mar 08 11:46:26.020 pci_server.3 pci_log 0 INFO ,1,0,3 [3:1]: B3:D0:F0 in chassis/slot 0/24 Mar 08 11:46:26.020 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:1]: B3:D0:F0 adds a000000/1080000/80 to bridge B0:D27:F4 for a total of a000000/1080000/80 Mar 08 11:46:26.020 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: disable_interrupts(B3:D0:F0) Mar 08 11:46:26.020 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: Found device B3:D0:F1 Mar 08 11:46:26.020 pci_server.3..0 pci_dbg 0 DEBUG,1,1,3 [3:1]: **** B3:D0:F1 has ccode 4,3,0 hdrType: 0 Mar 08 11:46:26.020 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: B3:D0:F1 - Check for /lib/dll/pci/pci_cap-0x10-10de0e0f.so ... not found Mar 08 11:46:26.021 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: B3:D0:F1 - Found /lib/dll/pci/pci_cap-0x10.so Mar 08 11:46:26.021 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:1]: device B3:D0:F1 parent bridge is B0:D27:F4 Mar 08 11:46:26.021 pci_server.3 pci_log 0 INFO ,1,0,3 [3:1]: B3:D0:F1 in chassis/slot 0/24 hierarchy Mar 08 11:46:26.021 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:1]: B3:D0:F1 adds 0/4000/0 to bridge B0:D27:F4 for a total of a000000/1084000/80 Mar 08 11:46:26.021 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: disable_interrupts(B3:D0:F1) Mar 08 11:46:26.021 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: disable_interrupts(B0:D27:F4) Mar 08 11:46:26.021 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: Found device B0:D28:F0 Mar 08 11:46:26.021 pci_server.3..0 pci_dbg 0 DEBUG,1,1,3 [3:1]: **** B0:D28:F0 has ccode 6,4,0 hdrType: 1 Mar 08 11:46:26.021 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: B0:D28:F0 - Check for /lib/dll/pci/pci_cap-0x10-8086a338.so ... not found Mar 08 11:46:26.021 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: B0:D28:F0 - Found /lib/dll/pci/pci_cap-0x10.so Mar 08 11:46:26.021 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: process_cs_overrides(B0:D28:F0), 0 slots Mar 08 11:46:26.021 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:1]: bridge B0:D28:F0 parent bridge is B0:D0:F0 Mar 08 11:46:26.021 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: B0:D28:F0 - Check for /lib/dll/pci/pci_cap-0x10-8086a338.so ... not found Mar 08 11:46:26.021 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: B0:D28:F0 - Found /lib/dll/pci/pci_cap-0x10.so Mar 08 11:46:26.021 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:1]: B0:D28:F0 adds 0/0/0 to bridge B0:D28:F0 for a total of 0/0/0 Mar 08 11:46:26.021 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:1]: cached_param_set_pri_busnum(80789b8, 0, T) Mar 08 11:46:26.021 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:1]: cached_param_set_sec_busnum(80789b8, 4, T) Mar 08 11:46:26.021 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:1]: cached_param_set_sub_busnum(80789b8, 4, T) Mar 08 11:46:26.021 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 4, limit=255, config=false,ari=false) Mar 08 11:46:26.021 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: disable_interrupts(B0:D28:F0) Mar 08 11:46:26.021 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: Found device B0:D28:F2 Mar 08 11:46:26.021 pci_server.3..0 pci_dbg 0 DEBUG,1,1,3 [3:1]: **** B0:D28:F2 has ccode 6,4,0 hdrType: 1 Mar 08 11:46:26.021 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: B0:D28:F2 - Check for /lib/dll/pci/pci_cap-0x10-8086a33a.so ... not found Mar 08 11:46:26.021 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: B0:D28:F2 - Found /lib/dll/pci/pci_cap-0x10.so Mar 08 11:46:26.021 pci_server.3 pci_log 0 INFO ,1,0,3 [3:1]: bridge B0:D28:F2 has 1 slot numbered 6 Mar 08 11:46:26.021 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: process_cs_overrides(B0:D28:F2), 1 slots Mar 08 11:46:26.021 pci_server.3..0 pci_dbg 0 DEBUG,1,0,3 [3:1]: Added entries for 1 slots Mar 08 11:46:26.021 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:1]: bridge B0:D28:F2 parent bridge is B0:D0:F0 Mar 08 11:46:26.021 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: B0:D28:F2 - Check for /lib/dll/pci/pci_cap-0x10-8086a33a.so ... not found Mar 08 11:46:26.021 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: B0:D28:F2 - Found /lib/dll/pci/pci_cap-0x10.so Mar 08 11:46:26.021 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:1]: B0:D28:F2 adds 0/0/0 to bridge B0:D28:F2 for a total of 0/0/0 Mar 08 11:46:26.021 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:1]: cached_param_set_pri_busnum(8078630, 0, T) Mar 08 11:46:26.021 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:1]: cached_param_set_sec_busnum(8078630, 5, T) Mar 08 11:46:26.021 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:1]: cached_param_set_sub_busnum(8078630, 5, T) Mar 08 11:46:26.021 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 5, limit=255, config=false,ari=false) Mar 08 11:46:26.021 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: Found device B5:D0:F0 Mar 08 11:46:26.021 pci_server.3..0 pci_dbg 0 DEBUG,1,1,3 [3:1]: **** B5:D0:F0 has ccode 2,0,0 hdrType: 0 Mar 08 11:46:26.021 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: B5:D0:F0 - Check for /lib/dll/pci/pci_cap-0x10-10ec8168.so ... not found Mar 08 11:46:26.021 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: B5:D0:F0 - Found /lib/dll/pci/pci_cap-0x10.so Mar 08 11:46:26.021 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:1]: device B5:D0:F0 parent bridge is B0:D28:F2 Mar 08 11:46:26.021 pci_server.3 pci_log 0 INFO ,1,0,3 [3:1]: B5:D0:F0 in chassis/slot 0/6 Mar 08 11:46:26.021 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:1]: B5:D0:F0 adds 0/5000/100 to bridge B0:D28:F2 for a total of 0/5000/100 Mar 08 11:46:26.021 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: disable_interrupts(B5:D0:F0) Mar 08 11:46:26.021 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: disable_interrupts(B0:D28:F2) Mar 08 11:46:26.021 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: Found device B0:D28:F4 Mar 08 11:46:26.021 pci_server.3..0 pci_dbg 0 DEBUG,1,1,3 [3:1]: **** B0:D28:F4 has ccode 6,4,0 hdrType: 1 Mar 08 11:46:26.021 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: B0:D28:F4 - Check for /lib/dll/pci/pci_cap-0x10-8086a33c.so ... not found Mar 08 11:46:26.021 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: B0:D28:F4 - Found /lib/dll/pci/pci_cap-0x10.so Mar 08 11:46:26.021 pci_server.3 pci_log 0 INFO ,1,0,3 [3:1]: bridge B0:D28:F4 has 1 slot numbered 8 Mar 08 11:46:26.021 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: process_cs_overrides(B0:D28:F4), 1 slots Mar 08 11:46:26.021 pci_server.3..0 pci_dbg 0 DEBUG,1,0,3 [3:1]: Added entries for 1 slots Mar 08 11:46:26.021 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:1]: bridge B0:D28:F4 parent bridge is B0:D0:F0 Mar 08 11:46:26.021 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: B0:D28:F4 - Check for /lib/dll/pci/pci_cap-0x10-8086a33c.so ... not found Mar 08 11:46:26.021 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: B0:D28:F4 - Found /lib/dll/pci/pci_cap-0x10.so Mar 08 11:46:26.021 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:1]: B0:D28:F4 adds 0/0/0 to bridge B0:D28:F4 for a total of 0/0/0 Mar 08 11:46:26.021 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:1]: cached_param_set_pri_busnum(8077f90, 0, T) Mar 08 11:46:26.021 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:1]: cached_param_set_sec_busnum(8077f90, 6, T) Mar 08 11:46:26.021 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:1]: cached_param_set_sub_busnum(8077f90, 6, T) Mar 08 11:46:26.021 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 6, limit=255, config=false,ari=false) Mar 08 11:46:26.021 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: Found device B6:D0:F0 Mar 08 11:46:26.021 pci_server.3..0 pci_dbg 0 DEBUG,1,1,3 [3:1]: **** B6:D0:F0 has ccode 11,80,0 hdrType: 0 Mar 08 11:46:26.022 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: B6:D0:F0 - Check for /lib/dll/pci/pci_cap-0x10-1093c4c4.so ... not found Mar 08 11:46:26.022 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: B6:D0:F0 - Found /lib/dll/pci/pci_cap-0x10.so Mar 08 11:46:26.022 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:1]: device B6:D0:F0 parent bridge is B0:D28:F4 Mar 08 11:46:26.022 pci_server.3 pci_log 0 INFO ,1,0,3 [3:1]: B6:D0:F0 in chassis/slot 0/8 Mar 08 11:46:26.022 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:1]: B6:D0:F0 adds 0/40000/0 to bridge B0:D28:F4 for a total of 0/40000/0 Mar 08 11:46:26.022 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: disable_interrupts(B6:D0:F0) Mar 08 11:46:26.022 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: disable_interrupts(B0:D28:F4) Mar 08 11:46:26.022 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: Found device B0:D29:F0 Mar 08 11:46:26.022 pci_server.3..0 pci_dbg 0 DEBUG,1,1,3 [3:1]: **** B0:D29:F0 has ccode 6,4,0 hdrType: 1 Mar 08 11:46:26.022 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: B0:D29:F0 - Check for /lib/dll/pci/pci_cap-0x10-8086a330.so ... not found Mar 08 11:46:26.022 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: B0:D29:F0 - Found /lib/dll/pci/pci_cap-0x10.so Mar 08 11:46:26.022 pci_server.3 pci_log 0 INFO ,1,0,3 [3:1]: bridge B0:D29:F0 has 1 slot numbered 12 Mar 08 11:46:26.022 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: process_cs_overrides(B0:D29:F0), 1 slots Mar 08 11:46:26.022 pci_server.3..0 pci_dbg 0 DEBUG,1,0,3 [3:1]: Added entries for 1 slots Mar 08 11:46:26.022 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:1]: bridge B0:D29:F0 parent bridge is B0:D0:F0 Mar 08 11:46:26.022 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: B0:D29:F0 - Check for /lib/dll/pci/pci_cap-0x10-8086a330.so ... not found Mar 08 11:46:26.022 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: B0:D29:F0 - Found /lib/dll/pci/pci_cap-0x10.so Mar 08 11:46:26.022 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:1]: B0:D29:F0 adds 0/0/0 to bridge B0:D29:F0 for a total of 0/0/0 Mar 08 11:46:26.022 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:1]: cached_param_set_pri_busnum(80778f0, 0, T) Mar 08 11:46:26.022 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:1]: cached_param_set_sec_busnum(80778f0, 7, T) Mar 08 11:46:26.022 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:1]: cached_param_set_sub_busnum(80778f0, 7, T) Mar 08 11:46:26.022 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 7, limit=255, config=false,ari=false) Mar 08 11:46:26.022 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: Found device B7:D0:F0 Mar 08 11:46:26.022 pci_server.3..0 pci_dbg 0 DEBUG,1,1,3 [3:1]: **** B7:D0:F0 has ccode 1,8,2 hdrType: 0 Mar 08 11:46:26.022 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: B7:D0:F0 - Check for /lib/dll/pci/pci_cap-0x10-144da808.so ... not found Mar 08 11:46:26.022 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: B7:D0:F0 - Found /lib/dll/pci/pci_cap-0x10.so Mar 08 11:46:26.022 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:1]: device B7:D0:F0 parent bridge is B0:D29:F0 Mar 08 11:46:26.022 pci_server.3 pci_log 0 INFO ,1,0,3 [3:1]: B7:D0:F0 in chassis/slot 0/12 Mar 08 11:46:26.022 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:1]: B7:D0:F0 adds 0/4000/0 to bridge B0:D29:F0 for a total of 0/4000/0 Mar 08 11:46:26.022 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: disable_interrupts(B7:D0:F0) Mar 08 11:46:26.022 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: disable_interrupts(B0:D29:F0) Mar 08 11:46:26.022 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: Found device B0:D31:F0 Mar 08 11:46:26.022 pci_server.3..0 pci_dbg 0 DEBUG,1,1,3 [3:1]: **** B0:D31:F0 has ccode 6,1,0 hdrType: 0 Mar 08 11:46:26.022 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:1]: device B0:D31:F0 parent bridge is B0:D0:F0 Mar 08 11:46:26.022 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:1]: B0:D31:F0 adds 0/0/0 to bridge B0:D0:F0 for a total of 0/17900/40 Mar 08 11:46:26.022 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: disable_interrupts(B0:D31:F0) Mar 08 11:46:26.022 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: Found device B0:D31:F4 Mar 08 11:46:26.022 pci_server.3..0 pci_dbg 0 DEBUG,1,1,3 [3:1]: **** B0:D31:F4 has ccode c,5,0 hdrType: 0 Mar 08 11:46:26.022 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:1]: device B0:D31:F4 parent bridge is B0:D0:F0 Mar 08 11:46:26.022 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:1]: B0:D31:F4 adds 0/100/20 to bridge B0:D0:F0 for a total of 0/17a00/60 Mar 08 11:46:26.022 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: disable_interrupts(B0:D31:F4) Mar 08 11:46:26.022 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: Found device B0:D31:F5 Mar 08 11:46:26.022 pci_server.3..0 pci_dbg 0 DEBUG,1,1,3 [3:1]: **** B0:D31:F5 has ccode c,80,0 hdrType: 0 Mar 08 11:46:26.022 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:1]: device B0:D31:F5 parent bridge is B0:D0:F0 Mar 08 11:46:26.022 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:1]: B0:D31:F5 adds 0/1000/0 to bridge B0:D0:F0 for a total of 0/18a00/60 Mar 08 11:46:26.022 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: disable_interrupts(B0:D31:F5) Mar 08 11:46:26.022 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 8, limit=255, config=false,ari=false) Mar 08 11:46:26.023 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 9, limit=255, config=false,ari=false) Mar 08 11:46:26.023 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 10, limit=255, config=false,ari=false) Mar 08 11:46:26.023 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 11, limit=255, config=false,ari=false) Mar 08 11:46:26.024 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 12, limit=255, config=false,ari=false) Mar 08 11:46:26.024 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 13, limit=255, config=false,ari=false) Mar 08 11:46:26.024 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 14, limit=255, config=false,ari=false) Mar 08 11:46:26.026 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 15, limit=255, config=false,ari=false) Mar 08 11:46:26.026 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 16, limit=255, config=false,ari=false) Mar 08 11:46:26.026 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 17, limit=255, config=false,ari=false) Mar 08 11:46:26.026 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 18, limit=255, config=false,ari=false) Mar 08 11:46:26.026 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 19, limit=255, config=false,ari=false) Mar 08 11:46:26.026 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 20, limit=255, config=false,ari=false) Mar 08 11:46:26.026 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 21, limit=255, config=false,ari=false) Mar 08 11:46:26.027 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 22, limit=255, config=false,ari=false) Mar 08 11:46:26.027 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 23, limit=255, config=false,ari=false) Mar 08 11:46:26.027 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 24, limit=255, config=false,ari=false) Mar 08 11:46:26.028 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 25, limit=255, config=false,ari=false) Mar 08 11:46:26.028 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 26, limit=255, config=false,ari=false) Mar 08 11:46:26.028 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 27, limit=255, config=false,ari=false) Mar 08 11:46:26.029 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 28, limit=255, config=false,ari=false) Mar 08 11:46:26.029 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 29, limit=255, config=false,ari=false) Mar 08 11:46:26.029 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 30, limit=255, config=false,ari=false) Mar 08 11:46:26.030 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 31, limit=255, config=false,ari=false) Mar 08 11:46:26.030 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 32, limit=255, config=false,ari=false) Mar 08 11:46:26.030 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 33, limit=255, config=false,ari=false) Mar 08 11:46:26.031 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 34, limit=255, config=false,ari=false) Mar 08 11:46:26.031 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 35, limit=255, config=false,ari=false) Mar 08 11:46:26.031 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 36, limit=255, config=false,ari=false) Mar 08 11:46:26.031 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 37, limit=255, config=false,ari=false) Mar 08 11:46:26.032 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 38, limit=255, config=false,ari=false) Mar 08 11:46:26.032 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 39, limit=255, config=false,ari=false) Mar 08 11:46:26.032 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 40, limit=255, config=false,ari=false) Mar 08 11:46:26.033 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 41, limit=255, config=false,ari=false) Mar 08 11:46:26.033 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 42, limit=255, config=false,ari=false) Mar 08 11:46:26.033 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 43, limit=255, config=false,ari=false) Mar 08 11:46:26.034 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 44, limit=255, config=false,ari=false) Mar 08 11:46:26.034 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 45, limit=255, config=false,ari=false) Mar 08 11:46:26.034 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 46, limit=255, config=false,ari=false) Mar 08 11:46:26.035 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 47, limit=255, config=false,ari=false) Mar 08 11:46:26.035 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 48, limit=255, config=false,ari=false) Mar 08 11:46:26.035 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 49, limit=255, config=false,ari=false) Mar 08 11:46:26.037 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 50, limit=255, config=false,ari=false) Mar 08 11:46:26.037 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 51, limit=255, config=false,ari=false) Mar 08 11:46:26.037 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 52, limit=255, config=false,ari=false) Mar 08 11:46:26.037 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 53, limit=255, config=false,ari=false) Mar 08 11:46:26.037 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 54, limit=255, config=false,ari=false) Mar 08 11:46:26.037 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 55, limit=255, config=false,ari=false) Mar 08 11:46:26.037 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 56, limit=255, config=false,ari=false) Mar 08 11:46:26.038 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 57, limit=255, config=false,ari=false) Mar 08 11:46:26.038 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 58, limit=255, config=false,ari=false) Mar 08 11:46:26.038 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 59, limit=255, config=false,ari=false) Mar 08 11:46:26.039 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 60, limit=255, config=false,ari=false) Mar 08 11:46:26.039 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 61, limit=255, config=false,ari=false) Mar 08 11:46:26.039 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 62, limit=255, config=false,ari=false) Mar 08 11:46:26.040 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 63, limit=255, config=false,ari=false) Mar 08 11:46:26.040 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 64, limit=255, config=false,ari=false) Mar 08 11:46:26.040 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 65, limit=255, config=false,ari=false) Mar 08 11:46:26.041 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 66, limit=255, config=false,ari=false) Mar 08 11:46:26.041 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 67, limit=255, config=false,ari=false) Mar 08 11:46:26.041 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 68, limit=255, config=false,ari=false) Mar 08 11:46:26.041 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 69, limit=255, config=false,ari=false) Mar 08 11:46:26.042 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 70, limit=255, config=false,ari=false) Mar 08 11:46:26.042 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 71, limit=255, config=false,ari=false) Mar 08 11:46:26.042 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 72, limit=255, config=false,ari=false) Mar 08 11:46:26.043 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 73, limit=255, config=false,ari=false) Mar 08 11:46:26.043 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 74, limit=255, config=false,ari=false) Mar 08 11:46:26.043 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 75, limit=255, config=false,ari=false) Mar 08 11:46:26.044 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 76, limit=255, config=false,ari=false) Mar 08 11:46:26.044 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 77, limit=255, config=false,ari=false) Mar 08 11:46:26.044 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 78, limit=255, config=false,ari=false) Mar 08 11:46:26.045 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 79, limit=255, config=false,ari=false) Mar 08 11:46:26.045 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 80, limit=255, config=false,ari=false) Mar 08 11:46:26.045 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 81, limit=255, config=false,ari=false) Mar 08 11:46:26.046 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 82, limit=255, config=false,ari=false) Mar 08 11:46:26.046 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 83, limit=255, config=false,ari=false) Mar 08 11:46:26.046 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 84, limit=255, config=false,ari=false) Mar 08 11:46:26.048 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 85, limit=255, config=false,ari=false) Mar 08 11:46:26.048 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 86, limit=255, config=false,ari=false) Mar 08 11:46:26.048 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 87, limit=255, config=false,ari=false) Mar 08 11:46:26.048 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 88, limit=255, config=false,ari=false) Mar 08 11:46:26.048 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 89, limit=255, config=false,ari=false) Mar 08 11:46:26.048 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 90, limit=255, config=false,ari=false) Mar 08 11:46:26.048 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 91, limit=255, config=false,ari=false) Mar 08 11:46:26.049 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 92, limit=255, config=false,ari=false) Mar 08 11:46:26.049 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 93, limit=255, config=false,ari=false) Mar 08 11:46:26.049 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 94, limit=255, config=false,ari=false) Mar 08 11:46:26.050 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 95, limit=255, config=false,ari=false) Mar 08 11:46:26.050 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 96, limit=255, config=false,ari=false) Mar 08 11:46:26.050 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 97, limit=255, config=false,ari=false) Mar 08 11:46:26.051 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 98, limit=255, config=false,ari=false) Mar 08 11:46:26.051 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 99, limit=255, config=false,ari=false) Mar 08 11:46:26.051 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 100, limit=255, config=false,ari=false) Mar 08 11:46:26.052 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 101, limit=255, config=false,ari=false) Mar 08 11:46:26.052 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 102, limit=255, config=false,ari=false) Mar 08 11:46:26.052 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 103, limit=255, config=false,ari=false) Mar 08 11:46:26.052 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 104, limit=255, config=false,ari=false) Mar 08 11:46:26.053 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 105, limit=255, config=false,ari=false) Mar 08 11:46:26.053 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 106, limit=255, config=false,ari=false) Mar 08 11:46:26.053 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 107, limit=255, config=false,ari=false) Mar 08 11:46:26.054 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 108, limit=255, config=false,ari=false) Mar 08 11:46:26.054 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 109, limit=255, config=false,ari=false) Mar 08 11:46:26.054 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 110, limit=255, config=false,ari=false) Mar 08 11:46:26.055 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 111, limit=255, config=false,ari=false) Mar 08 11:46:26.055 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 112, limit=255, config=false,ari=false) Mar 08 11:46:26.055 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 113, limit=255, config=false,ari=false) Mar 08 11:46:26.056 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 114, limit=255, config=false,ari=false) Mar 08 11:46:26.056 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 115, limit=255, config=false,ari=false) Mar 08 11:46:26.056 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 116, limit=255, config=false,ari=false) Mar 08 11:46:26.057 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 117, limit=255, config=false,ari=false) Mar 08 11:46:26.057 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 118, limit=255, config=false,ari=false) Mar 08 11:46:26.057 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 119, limit=255, config=false,ari=false) Mar 08 11:46:26.057 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 120, limit=255, config=false,ari=false) Mar 08 11:46:26.059 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 121, limit=255, config=false,ari=false) Mar 08 11:46:26.059 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 122, limit=255, config=false,ari=false) Mar 08 11:46:26.059 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 123, limit=255, config=false,ari=false) Mar 08 11:46:26.059 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 124, limit=255, config=false,ari=false) Mar 08 11:46:26.059 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 125, limit=255, config=false,ari=false) Mar 08 11:46:26.059 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 126, limit=255, config=false,ari=false) Mar 08 11:46:26.060 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 127, limit=255, config=false,ari=false) Mar 08 11:46:26.060 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 128, limit=255, config=false,ari=false) Mar 08 11:46:26.060 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 129, limit=255, config=false,ari=false) Mar 08 11:46:26.061 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 130, limit=255, config=false,ari=false) Mar 08 11:46:26.061 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 131, limit=255, config=false,ari=false) Mar 08 11:46:26.061 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 132, limit=255, config=false,ari=false) Mar 08 11:46:26.062 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 133, limit=255, config=false,ari=false) Mar 08 11:46:26.062 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 134, limit=255, config=false,ari=false) Mar 08 11:46:26.062 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 135, limit=255, config=false,ari=false) Mar 08 11:46:26.062 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 136, limit=255, config=false,ari=false) Mar 08 11:46:26.063 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 137, limit=255, config=false,ari=false) Mar 08 11:46:26.063 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 138, limit=255, config=false,ari=false) Mar 08 11:46:26.063 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 139, limit=255, config=false,ari=false) Mar 08 11:46:26.064 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 140, limit=255, config=false,ari=false) Mar 08 11:46:26.064 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 141, limit=255, config=false,ari=false) Mar 08 11:46:26.064 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 142, limit=255, config=false,ari=false) Mar 08 11:46:26.065 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 143, limit=255, config=false,ari=false) Mar 08 11:46:26.065 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 144, limit=255, config=false,ari=false) Mar 08 11:46:26.065 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 145, limit=255, config=false,ari=false) Mar 08 11:46:26.066 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 146, limit=255, config=false,ari=false) Mar 08 11:46:26.066 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 147, limit=255, config=false,ari=false) Mar 08 11:46:26.066 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 148, limit=255, config=false,ari=false) Mar 08 11:46:26.067 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 149, limit=255, config=false,ari=false) Mar 08 11:46:26.067 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 150, limit=255, config=false,ari=false) Mar 08 11:46:26.067 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 151, limit=255, config=false,ari=false) Mar 08 11:46:26.067 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 152, limit=255, config=false,ari=false) Mar 08 11:46:26.068 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 153, limit=255, config=false,ari=false) Mar 08 11:46:26.068 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 154, limit=255, config=false,ari=false) Mar 08 11:46:26.068 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 155, limit=255, config=false,ari=false) Mar 08 11:46:26.069 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 156, limit=255, config=false,ari=false) Mar 08 11:46:26.069 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 157, limit=255, config=false,ari=false) Mar 08 11:46:26.069 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 158, limit=255, config=false,ari=false) Mar 08 11:46:26.070 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 159, limit=255, config=false,ari=false) Mar 08 11:46:26.070 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 160, limit=255, config=false,ari=false) Mar 08 11:46:26.070 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 161, limit=255, config=false,ari=false) Mar 08 11:46:26.071 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 162, limit=255, config=false,ari=false) Mar 08 11:46:26.071 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 163, limit=255, config=false,ari=false) Mar 08 11:46:26.071 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 164, limit=255, config=false,ari=false) Mar 08 11:46:26.072 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 165, limit=255, config=false,ari=false) Mar 08 11:46:26.072 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 166, limit=255, config=false,ari=false) Mar 08 11:46:26.072 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 167, limit=255, config=false,ari=false) Mar 08 11:46:26.072 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 168, limit=255, config=false,ari=false) Mar 08 11:46:26.073 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 169, limit=255, config=false,ari=false) Mar 08 11:46:26.073 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 170, limit=255, config=false,ari=false) Mar 08 11:46:26.073 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 171, limit=255, config=false,ari=false) Mar 08 11:46:26.074 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 172, limit=255, config=false,ari=false) Mar 08 11:46:26.074 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 173, limit=255, config=false,ari=false) Mar 08 11:46:26.074 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 174, limit=255, config=false,ari=false) Mar 08 11:46:26.075 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 175, limit=255, config=false,ari=false) Mar 08 11:46:26.075 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 176, limit=255, config=false,ari=false) Mar 08 11:46:26.075 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 177, limit=255, config=false,ari=false) Mar 08 11:46:26.076 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 178, limit=255, config=false,ari=false) Mar 08 11:46:26.076 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 179, limit=255, config=false,ari=false) Mar 08 11:46:26.076 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 180, limit=255, config=false,ari=false) Mar 08 11:46:26.077 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 181, limit=255, config=false,ari=false) Mar 08 11:46:26.077 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 182, limit=255, config=false,ari=false) Mar 08 11:46:26.077 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 183, limit=255, config=false,ari=false) Mar 08 11:46:26.077 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 184, limit=255, config=false,ari=false) Mar 08 11:46:26.078 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 185, limit=255, config=false,ari=false) Mar 08 11:46:26.078 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 186, limit=255, config=false,ari=false) Mar 08 11:46:26.078 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 187, limit=255, config=false,ari=false) Mar 08 11:46:26.080 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 188, limit=255, config=false,ari=false) Mar 08 11:46:26.080 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 189, limit=255, config=false,ari=false) Mar 08 11:46:26.080 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 190, limit=255, config=false,ari=false) Mar 08 11:46:26.080 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 191, limit=255, config=false,ari=false) Mar 08 11:46:26.080 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 192, limit=255, config=false,ari=false) Mar 08 11:46:26.080 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 193, limit=255, config=false,ari=false) Mar 08 11:46:26.081 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 194, limit=255, config=false,ari=false) Mar 08 11:46:26.081 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 195, limit=255, config=false,ari=false) Mar 08 11:46:26.081 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 196, limit=255, config=false,ari=false) Mar 08 11:46:26.082 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 197, limit=255, config=false,ari=false) Mar 08 11:46:26.082 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 198, limit=255, config=false,ari=false) Mar 08 11:46:26.082 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 199, limit=255, config=false,ari=false) Mar 08 11:46:26.082 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 200, limit=255, config=false,ari=false) Mar 08 11:46:26.083 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 201, limit=255, config=false,ari=false) Mar 08 11:46:26.083 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 202, limit=255, config=false,ari=false) Mar 08 11:46:26.083 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 203, limit=255, config=false,ari=false) Mar 08 11:46:26.084 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 204, limit=255, config=false,ari=false) Mar 08 11:46:26.084 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 205, limit=255, config=false,ari=false) Mar 08 11:46:26.084 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 206, limit=255, config=false,ari=false) Mar 08 11:46:26.085 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 207, limit=255, config=false,ari=false) Mar 08 11:46:26.085 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 208, limit=255, config=false,ari=false) Mar 08 11:46:26.085 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 209, limit=255, config=false,ari=false) Mar 08 11:46:26.086 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 210, limit=255, config=false,ari=false) Mar 08 11:46:26.086 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 211, limit=255, config=false,ari=false) Mar 08 11:46:26.086 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 212, limit=255, config=false,ari=false) Mar 08 11:46:26.087 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 213, limit=255, config=false,ari=false) Mar 08 11:46:26.087 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 214, limit=255, config=false,ari=false) Mar 08 11:46:26.087 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 215, limit=255, config=false,ari=false) Mar 08 11:46:26.088 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 216, limit=255, config=false,ari=false) Mar 08 11:46:26.088 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 217, limit=255, config=false,ari=false) Mar 08 11:46:26.088 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 218, limit=255, config=false,ari=false) Mar 08 11:46:26.088 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 219, limit=255, config=false,ari=false) Mar 08 11:46:26.089 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 220, limit=255, config=false,ari=false) Mar 08 11:46:26.089 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 221, limit=255, config=false,ari=false) Mar 08 11:46:26.089 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 222, limit=255, config=false,ari=false) Mar 08 11:46:26.091 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 223, limit=255, config=false,ari=false) Mar 08 11:46:26.091 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 224, limit=255, config=false,ari=false) Mar 08 11:46:26.091 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 225, limit=255, config=false,ari=false) Mar 08 11:46:26.091 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 226, limit=255, config=false,ari=false) Mar 08 11:46:26.091 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 227, limit=255, config=false,ari=false) Mar 08 11:46:26.091 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 228, limit=255, config=false,ari=false) Mar 08 11:46:26.092 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 229, limit=255, config=false,ari=false) Mar 08 11:46:26.092 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 230, limit=255, config=false,ari=false) Mar 08 11:46:26.092 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 231, limit=255, config=false,ari=false) Mar 08 11:46:26.093 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 232, limit=255, config=false,ari=false) Mar 08 11:46:26.093 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 233, limit=255, config=false,ari=false) Mar 08 11:46:26.093 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 234, limit=255, config=false,ari=false) Mar 08 11:46:26.093 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 235, limit=255, config=false,ari=false) Mar 08 11:46:26.094 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 236, limit=255, config=false,ari=false) Mar 08 11:46:26.094 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 237, limit=255, config=false,ari=false) Mar 08 11:46:26.094 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 238, limit=255, config=false,ari=false) Mar 08 11:46:26.095 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 239, limit=255, config=false,ari=false) Mar 08 11:46:26.095 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 240, limit=255, config=false,ari=false) Mar 08 11:46:26.095 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 241, limit=255, config=false,ari=false) Mar 08 11:46:26.096 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 242, limit=255, config=false,ari=false) Mar 08 11:46:26.096 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 243, limit=255, config=false,ari=false) Mar 08 11:46:26.096 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 244, limit=255, config=false,ari=false) Mar 08 11:46:26.097 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 245, limit=255, config=false,ari=false) Mar 08 11:46:26.097 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 246, limit=255, config=false,ari=false) Mar 08 11:46:26.097 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 247, limit=255, config=false,ari=false) Mar 08 11:46:26.098 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 248, limit=255, config=false,ari=false) Mar 08 11:46:26.098 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 249, limit=255, config=false,ari=false) Mar 08 11:46:26.098 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 250, limit=255, config=false,ari=false) Mar 08 11:46:26.098 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 251, limit=255, config=false,ari=false) Mar 08 11:46:26.099 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 252, limit=255, config=false,ari=false) Mar 08 11:46:26.099 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 253, limit=255, config=false,ari=false) Mar 08 11:46:26.099 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 254, limit=255, config=false,ari=false) Mar 08 11:46:26.100 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: enumerate_bus(bus 255, limit=255, config=false,ari=false) Mar 08 11:46:26.100 pci_server.3 pci_log 0 INFO ,1,0,3 [3:1]: pci_max_bus = 7 Mar 08 11:46:26.100 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:1]: correct_as_requirements(B0:D1:F0), size and alignment corrections size pfmem 0 --> 0, mem 10000 --> 100000, io 0 --> 0 align pfmem 0 --> 0, mem 100000 --> 100000, io 0 --> 0 Mar 08 11:46:26.100 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:1]: correct_as_requirements(B0:D1:F0), parent B0:D0:F0 size corrections size pfmem 0 --> 0, mem 18a00 --> 118a00, io 60 --> 60 align pfmem 0/32bit --> 0/32bit, mem 10000/32bit --> 100000/32bit, io 20/16 --> 20/16bit Mar 08 11:46:26.100 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:1]: correct_as_requirements(B0:D27:F0), size and alignment corrections size pfmem 0 --> 0, mem 0 --> 0, io 0 --> 0 align pfmem 0 --> 0, mem 0 --> 0, io 0 --> 0 Mar 08 11:46:26.100 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:1]: correct_as_requirements(B0:D27:F0), parent B0:D0:F0 size corrections size pfmem 0 --> 0, mem 118a00 --> 118a00, io 60 --> 60 align pfmem 0/32bit --> 0/32bit, mem 100000/32bit --> 100000/32bit, io 20/16 --> 20/16bit Mar 08 11:46:26.100 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:1]: correct_as_requirements(B0:D27:F4), size and alignment corrections size pfmem a000000 --> a000000, mem 1084000 --> 1100000, io 80 --> 1000 align pfmem 8000000 --> 8000000, mem 1000000 --> 1000000, io 1000 --> 1000 Mar 08 11:46:26.100 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:1]: correct_as_requirements(B0:D27:F4), parent B0:D0:F0 size corrections size pfmem 0 --> a000000, mem 118a00 --> 1218a00, io 60 --> 1060 align pfmem 0/32bit --> 8000000/32bit, mem 100000/32bit --> 1000000/32bit, io 20/16 --> 1000/16bit Mar 08 11:46:26.100 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:1]: correct_as_requirements(B0:D28:F0), size and alignment corrections size pfmem 0 --> 0, mem 0 --> 0, io 0 --> 0 align pfmem 0 --> 0, mem 0 --> 0, io 0 --> 0 Mar 08 11:46:26.100 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:1]: correct_as_requirements(B0:D28:F0), parent B0:D0:F0 size corrections size pfmem a000000 --> a000000, mem 1218a00 --> 1218a00, io 1060 --> 1060 align pfmem 8000000/32bit --> 8000000/32bit, mem 1000000/32bit --> 1000000/32bit, io 1000/16 --> 1000/16bit Mar 08 11:46:26.100 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:1]: correct_as_requirements(B0:D28:F2), size and alignment corrections size pfmem 0 --> 0, mem 5000 --> 100000, io 100 --> 1000 align pfmem 0 --> 0, mem 100000 --> 100000, io 1000 --> 1000 Mar 08 11:46:26.100 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:1]: correct_as_requirements(B0:D28:F2), parent B0:D0:F0 size corrections size pfmem a000000 --> a000000, mem 1218a00 --> 1318a00, io 1060 --> 2060 align pfmem 8000000/32bit --> 8000000/32bit, mem 1000000/32bit --> 1000000/32bit, io 1000/16 --> 1000/16bit Mar 08 11:46:26.100 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:1]: correct_as_requirements(B0:D28:F4), size and alignment corrections size pfmem 0 --> 0, mem 40000 --> 100000, io 0 --> 0 align pfmem 0 --> 0, mem 100000 --> 100000, io 0 --> 0 Mar 08 11:46:26.100 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:1]: correct_as_requirements(B0:D28:F4), parent B0:D0:F0 size corrections size pfmem a000000 --> a000000, mem 1318a00 --> 1418a00, io 2060 --> 2060 align pfmem 8000000/32bit --> 8000000/32bit, mem 1000000/32bit --> 1000000/32bit, io 1000/16 --> 1000/16bit Mar 08 11:46:26.100 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:1]: correct_as_requirements(B0:D29:F0), size and alignment corrections size pfmem 0 --> 0, mem 4000 --> 100000, io 0 --> 0 align pfmem 0 --> 0, mem 100000 --> 100000, io 0 --> 0 Mar 08 11:46:26.100 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:1]: correct_as_requirements(B0:D29:F0), parent B0:D0:F0 size corrections size pfmem a000000 --> a000000, mem 1418a00 --> 1518a00, io 2060 --> 2060 align pfmem 8000000/32bit --> 8000000/32bit, mem 1000000/32bit --> 1000000/32bit, io 1000/16 --> 1000/16bit Mar 08 11:46:26.100 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:1]: correct_as_requirements(B0:D0:F0), size and alignment corrections size pfmem a000000 --> a000000, mem 1518a00 --> 1600000, io 2060 --> 3000 align pfmem 8000000 --> 8000000, mem 1000000 --> 1000000, io 1000 --> 1000 Mar 08 11:46:26.100 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: AS reservation req for B0:D1:F0 (4b400000/100000, align: 100000, attr: 4000 ... Ok) Mar 08 11:46:26.100 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: alloc_as() MEM from 4b400000 to 4b4fffff (100000), attr 4014 OK [PCI_ERR_OK] Mar 08 11:46:26.100 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: AS reservation req for B0:D27:F4 (40000000/8000000, align: 8000000, attr: 18000 ... Ok) Mar 08 11:46:26.100 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: alloc_as() PFMEM from 40000000 to 47ffffff (8000000), attr 1801b OK [PCI_ERR_OK] Mar 08 11:46:26.100 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: AS reservation req for B0:D27:F4 (48000000/3100000, align: 1000000, attr: 4000 ... Ok) Mar 08 11:46:26.100 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: alloc_as() MEM from 48000000 to 4b0fffff (3100000), attr 4018 OK [PCI_ERR_OK] Mar 08 11:46:26.100 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: AS reservation req for B0:D27:F4 (4000/1000, align: 1000, attr: 0 ... Ok) Mar 08 11:46:26.100 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: alloc_as() IO from 4000 to 4fff (1000), attr c OK [PCI_ERR_OK] Mar 08 11:46:26.100 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: AS reservation req for B0:D28:F2 (4b300000/100000, align: 100000, attr: 8000 ... Ok) Mar 08 11:46:26.100 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: alloc_as() MEM from 4b300000 to 4b3fffff (100000), attr 8014 OK [PCI_ERR_OK] Mar 08 11:46:26.100 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: AS reservation req for B0:D28:F2 (3000/1000, align: 1000, attr: 0 ... Ok) Mar 08 11:46:26.100 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: alloc_as() IO from 3000 to 3fff (1000), attr c OK [PCI_ERR_OK] Mar 08 11:46:26.100 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: AS reservation req for B0:D28:F4 (4b200000/100000, align: 100000, attr: 4000 ... Ok) Mar 08 11:46:26.100 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: alloc_as() MEM from 4b200000 to 4b2fffff (100000), attr 4014 OK [PCI_ERR_OK] Mar 08 11:46:26.100 pci_server.3 pci_log 0 INFO ,1,2,3 [3:1]: AS reservation req for B0:D29:F0 (4b100000/100000, align: 100000, attr: 8000 ... Ok) Mar 08 11:46:26.100 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: alloc_as() MEM from 4b100000 to 4b1fffff (100000), attr 8014 OK [PCI_ERR_OK] Mar 08 11:46:26.100 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: Enabling address spaces for devices which are disabled Mar 08 11:46:26.100 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: Updating address space enables from 0x2 to 0x0 for B0:D0:F0, OK [PCI_ERR_OK] Mar 08 11:46:26.100 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: Updating address space enables from 0x0 to 0x2 for B0:D22:F0, OK [PCI_ERR_OK] Mar 08 11:46:26.100 pci_server.3 pci_log 0 INFO ,1,1,3 [3:1]: enumerate_bus_hierarchy(), OK [PCI_ERR_OK] Mar 08 11:46:26.100 pci_server.3 pci_log 0 INFO ,1,0,3 [3:1]: ++ enumeration only complete, status OK [PCI_ERR_OK] ++ Mar 08 11:46:26.100 pci_server.3 pci_log 0 INFO ,1,0,3 [3:1]: ++ Server Module Load start ++ Mar 08 11:46:26.100 pci_server.3 pci_log 0 INFO ,1,0,3 [3:1]: ++ Server Module Load end ++ Mar 08 11:46:26.100 pci_server.3 pci_log 0 INFO ,1,-10,3 [3:1]: + PCI Server v2.0 init complete, OK [PCI_ERR_OK] + Mar 08 11:46:26.100 pci_server.3 pci_log 0 INFO ,1,-10,3 [3:1]: Mar 08 11:46:26.153 pci_server.3 pci_log 0 INFO ,1,0,3 [3:2]: Attempt module load of /lib/dll/pci/pci_cap-0x11-10ec8168.so Mar 08 11:46:26.153 pci_server.3 pci_log 0 ERROR,0,0,3 [3:2]: dlopen_mod(), dlopen() error: Library cannot be found Mar 08 11:46:26.153 pci_server.3 pci_log 0 INFO ,1,0,3 [3:2]: Re-attempt module load of /lib/dll/pci/pci_cap-0x11.so Mar 08 11:46:26.154 pci_server.3 pci_log 0 INFO ,1,0,3 [3:2]: Module is compatible with Server ver 2.0 Mar 08 11:46:26.154 pci_server.3 pci_log 0 INFO ,1,0,3 [3:2]: Module is compatible with Library ver 2.0 Mar 08 11:46:26.154 pci_server.3 pci_log 0 INFO ,1,0,3 [3:2]: Module /lib/dll/pci/pci_cap-0x11.so, v2.0 loaded successfully Mar 08 11:46:26.154 pci_server.3 pci_log 0 INFO ,1,1,3 [3:2]: B5:D0:F0 - Check for /lib/dll/pci/pci_cap-0x11-10ec8168.so ... not found Mar 08 11:46:26.154 pci_server.3 pci_log 0 INFO ,1,1,3 [3:2]: B5:D0:F0 - Found /lib/dll/pci/pci_cap-0x11.so Mar 08 11:46:26.154 pci_server.3..0 pci_dbg 0 DEBUG,1,0,3 [3:2]: _cap_msix_get_nirq(806e528) returns 4 Mar 08 11:46:26.154 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:2]: Using lapic asinfo entry 0xfee00000 Mar 08 11:46:26.154 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:2]: init_lapic_addr(), use 0xfee00000 for lapic_addr[0] Mar 08 11:46:26.154 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:2]: init_lapic_addr(), use 0xfee00000 for lapic_addr[1] Mar 08 11:46:26.154 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:2]: init_lapic_addr(), use 0xfee00000 for lapic_addr[2] Mar 08 11:46:26.154 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:2]: init_lapic_addr(), use 0xfee00000 for lapic_addr[3] Mar 08 11:46:26.154 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:2]: init_lapic_addr(), use 0xfee00000 for lapic_addr[4] Mar 08 11:46:26.154 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:2]: init_lapic_addr(), use 0xfee00000 for lapic_addr[5] Mar 08 11:46:26.154 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:2]: init_lapic_addr(), use 0xfee00000 for lapic_addr[6] Mar 08 11:46:26.154 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:2]: init_lapic_addr(), use 0xfee00000 for lapic_addr[7] Mar 08 11:46:26.154 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:2]: init_lapic_addr(), use 0xfee00000 for lapic_addr[8] Mar 08 11:46:26.154 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:2]: init_lapic_addr(), use 0xfee00000 for lapic_addr[9] Mar 08 11:46:26.154 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:2]: init_lapic_addr(), use 0xfee00000 for lapic_addr[10] Mar 08 11:46:26.154 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:2]: init_lapic_addr(), use 0xfee00000 for lapic_addr[11] Mar 08 11:46:26.154 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:2]: init_lapic_addr(), use 0xfee00000 for lapic_addr[12] Mar 08 11:46:26.154 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:2]: init_lapic_addr(), use 0xfee00000 for lapic_addr[13] Mar 08 11:46:26.154 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:2]: init_lapic_addr(), use 0xfee00000 for lapic_addr[14] Mar 08 11:46:26.154 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:2]: init_lapic_addr(), use 0xfee00000 for lapic_addr[15] Mar 08 11:46:26.154 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:2]: init_lapic_addr(), use 0xfee00000 for lapic_addr[16] Mar 08 11:46:26.154 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:2]: init_lapic_addr(), use 0xfee00000 for lapic_addr[17] Mar 08 11:46:26.154 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:2]: init_lapic_addr(), use 0xfee00000 for lapic_addr[18] Mar 08 11:46:26.154 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:2]: init_lapic_addr(), use 0xfee00000 for lapic_addr[19] Mar 08 11:46:26.154 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:2]: init_lapic_addr(), use 0xfee00000 for lapic_addr[20] Mar 08 11:46:26.154 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:2]: init_lapic_addr(), use 0xfee00000 for lapic_addr[21] Mar 08 11:46:26.154 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:2]: init_lapic_addr(), use 0xfee00000 for lapic_addr[22] Mar 08 11:46:26.154 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:2]: init_lapic_addr(), use 0xfee00000 for lapic_addr[23] Mar 08 11:46:26.154 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:2]: init_lapic_addr(), use 0xfee00000 for lapic_addr[24] Mar 08 11:46:26.154 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:2]: init_lapic_addr(), use 0xfee00000 for lapic_addr[25] Mar 08 11:46:26.154 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:2]: init_lapic_addr(), use 0xfee00000 for lapic_addr[26] Mar 08 11:46:26.154 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:2]: init_lapic_addr(), use 0xfee00000 for lapic_addr[27] Mar 08 11:46:26.154 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:2]: init_lapic_addr(), use 0xfee00000 for lapic_addr[28] Mar 08 11:46:26.154 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:2]: init_lapic_addr(), use 0xfee00000 for lapic_addr[29] Mar 08 11:46:26.154 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:2]: init_lapic_addr(), use 0xfee00000 for lapic_addr[30] Mar 08 11:46:26.154 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:2]: init_lapic_addr(), use 0xfee00000 for lapic_addr[31] Mar 08 11:46:26.154 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:2]: init_lapic_addr(), use 0xfee00000 for lapic_addr[32] Mar 08 11:46:26.154 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:2]: init_lapic_addr(), use 0xfee00000 for lapic_addr[33] Mar 08 11:46:26.154 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:2]: init_lapic_addr(), use 0xfee00000 for lapic_addr[34] Mar 08 11:46:26.154 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:2]: init_lapic_addr(), use 0xfee00000 for lapic_addr[35] Mar 08 11:46:26.154 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:2]: init_lapic_addr(), use 0xfee00000 for lapic_addr[36] Mar 08 11:46:26.154 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:2]: init_lapic_addr(), use 0xfee00000 for lapic_addr[37] Mar 08 11:46:26.154 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:2]: init_lapic_addr(), use 0xfee00000 for lapic_addr[38] Mar 08 11:46:26.154 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:2]: init_lapic_addr(), use 0xfee00000 for lapic_addr[39] Mar 08 11:46:26.154 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:2]: init_lapic_addr(), use 0xfee00000 for lapic_addr[40] Mar 08 11:46:26.154 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:2]: init_lapic_addr(), use 0xfee00000 for lapic_addr[41] Mar 08 11:46:26.154 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:2]: init_lapic_addr(), use 0xfee00000 for lapic_addr[42] Mar 08 11:46:26.154 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:2]: init_lapic_addr(), use 0xfee00000 for lapic_addr[43] Mar 08 11:46:26.154 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:2]: init_lapic_addr(), use 0xfee00000 for lapic_addr[44] Mar 08 11:46:26.154 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:2]: init_lapic_addr(), use 0xfee00000 for lapic_addr[45] Mar 08 11:46:26.154 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:2]: init_lapic_addr(), use 0xfee00000 for lapic_addr[46] Mar 08 11:46:26.154 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:2]: init_lapic_addr(), use 0xfee00000 for lapic_addr[47] Mar 08 11:46:26.154 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:2]: init_lapic_addr(), use 0xfee00000 for lapic_addr[48] Mar 08 11:46:26.154 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:2]: init_lapic_addr(), use 0xfee00000 for lapic_addr[49] Mar 08 11:46:26.154 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:2]: init_lapic_addr(), use 0xfee00000 for lapic_addr[50] Mar 08 11:46:26.154 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:2]: init_lapic_addr(), use 0xfee00000 for lapic_addr[51] Mar 08 11:46:26.154 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:2]: init_lapic_addr(), use 0xfee00000 for lapic_addr[52] Mar 08 11:46:26.154 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:2]: init_lapic_addr(), use 0xfee00000 for lapic_addr[53] Mar 08 11:46:26.154 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:2]: init_lapic_addr(), use 0xfee00000 for lapic_addr[54] Mar 08 11:46:26.154 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:2]: init_lapic_addr(), use 0xfee00000 for lapic_addr[55] Mar 08 11:46:26.154 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:2]: init_lapic_addr(), use 0xfee00000 for lapic_addr[56] Mar 08 11:46:26.154 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:2]: init_lapic_addr(), use 0xfee00000 for lapic_addr[57] Mar 08 11:46:26.154 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:2]: init_lapic_addr(), use 0xfee00000 for lapic_addr[58] Mar 08 11:46:26.154 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:2]: init_lapic_addr(), use 0xfee00000 for lapic_addr[59] Mar 08 11:46:26.154 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:2]: init_lapic_addr(), use 0xfee00000 for lapic_addr[60] Mar 08 11:46:26.154 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:2]: init_lapic_addr(), use 0xfee00000 for lapic_addr[61] Mar 08 11:46:26.154 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:2]: init_lapic_addr(), use 0xfee00000 for lapic_addr[62] Mar 08 11:46:26.154 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:2]: init_lapic_addr(), use 0xfee00000 for lapic_addr[63] Mar 08 11:46:26.154 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:2]: find_dest_coreid(0x0, 0x0) core ID is 0x0 Mar 08 11:46:26.154 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:2]: init_msi_addr() MSI address portion of MSI vector is 0xfee00000 Mar 08 11:46:26.154 pci_server.3 pci_log 0 INFO ,1,2,3 [3:2]: hw_alloc_irq(B5:D0:F0, 0, 0x0, 1, 806b0b0) OK [PCI_ERR_OK] Mar 08 11:46:26.154 pci_server.3..0 pci_dbg 0 DEBUG,1,1,3 [3:2]: Lookup of server sym bdf_assign_irqs ok Mar 08 11:46:26.154 pci_server.3..0 pci_dbg 0 DEBUG,1,0,3 [3:2]: _cap_msix_get_nirq(806e528) returns 4 Mar 08 11:46:26.154 pci_server.3..0 pci_dbg 0 DEBUG,1,1,3 [3:2]: Lookup of server sym bdf_get_bar_ba ok Mar 08 11:46:26.154 pci_server.3..0 pci_dbg 0 DEBUG,1,1,3 [3:2]: MSI-X vector table (4 vectors, sz=0x1000) at 4b300000 mapped to 30000000 for server and pid 167946 Mar 08 11:46:26.154 pci_server.3..0 pci_dbg 0 DEBUG,1,0,3 [3:2]: _cap_msix_get_nirq(806e528) returns 4 Mar 08 11:46:26.154 pci_server.3..0 pci_dbg 0 DEBUG,1,1,3 [3:2]: MSI-X PBA (4 vectors, sz=0x1000) at 4b300800 mapped to 30002800 for server and pid 167946 Mar 08 11:46:27.291 pci_server.3 pci_log 0 INFO ,1,0,3 [3:2]: Attempt module load of /lib/dll/pci/pci_cap-0x05-8086a36d.so Mar 08 11:46:27.291 pci_server.3 pci_log 0 ERROR,0,0,3 [3:2]: dlopen_mod(), dlopen() error: Library cannot be found Mar 08 11:46:27.291 pci_server.3 pci_log 0 INFO ,1,0,3 [3:2]: Re-attempt module load of /lib/dll/pci/pci_cap-0x05.so Mar 08 11:46:27.291 pci_server.3 pci_log 0 INFO ,1,0,3 [3:2]: Module is compatible with Server ver 2.0 Mar 08 11:46:27.291 pci_server.3 pci_log 0 INFO ,1,0,3 [3:2]: Module is compatible with Library ver 2.0 Mar 08 11:46:27.291 pci_server.3 pci_log 0 INFO ,1,0,3 [3:2]: Module /lib/dll/pci/pci_cap-0x05.so, v2.0 loaded successfully Mar 08 11:46:27.291 pci_server.3 pci_log 0 INFO ,1,1,3 [3:2]: B0:D20:F0 - Check for /lib/dll/pci/pci_cap-0x05-8086a36d.so ... not found Mar 08 11:46:27.291 pci_server.3 pci_log 0 INFO ,1,1,3 [3:2]: B0:D20:F0 - Found /lib/dll/pci/pci_cap-0x05.so Mar 08 11:46:27.291 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:2]: find_dest_coreid(0x0, 0x0) core ID is 0x0 Mar 08 11:46:27.291 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:2]: init_msi_addr() MSI address portion of MSI vector is 0xfee00000 Mar 08 11:46:27.291 pci_server.3 pci_log 0 INFO ,1,2,3 [3:2]: hw_alloc_irq(B0:D20:F0, 0, 0x1, 1, 806b0d0) OK [PCI_ERR_OK] Mar 08 11:46:27.291 pci_server.3..0 pci_dbg 0 DEBUG,1,1,3 [3:2]: Lookup of server sym bdf_assign_irqs ok Mar 08 11:46:27.291 pci_server.3..0 pci_dbg 0 DEBUG,1,0,3 [3:2]: _mod_msi_enable_cap(53ec5357, 100, 80710c8), OK [PCI_ERR_OK] Mar 08 11:47:49.746 pci_server.3 pci_log 0 INFO ,1,1,3 [3:2]: B0:D23:F0 - Check for /lib/dll/pci/pci_cap-0x05-8086a352.so ... not found Mar 08 11:47:49.746 pci_server.3 pci_log 0 INFO ,1,1,3 [3:2]: B0:D23:F0 - Found /lib/dll/pci/pci_cap-0x05.so Mar 08 11:47:49.746 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:2]: find_dest_coreid(0x0, 0x0) core ID is 0x0 Mar 08 11:47:49.746 pci_server.3..0 pci_dbg 0 DEBUG,1,2,3 [3:2]: init_msi_addr() MSI address portion of MSI vector is 0xfee00000 Mar 08 11:47:49.746 pci_server.3 pci_log 0 INFO ,1,2,3 [3:2]: hw_alloc_irq(B0:D23:F0, 0, 0x1, 1, 806b0f0) OK [PCI_ERR_OK] Mar 08 11:47:49.746 pci_server.3..0 pci_dbg 0 DEBUG,1,0,3 [3:2]: _mod_msi_enable_cap(53f45357, 100, 8071130), OK [PCI_ERR_OK] # ./drun dryscan.ss # Mar 08 11:50:58.957 pci_server.3..0 pci_dbg 0 DEBUG,1,0,3 [3:2]: intpin_to_pirq(): Determine B1:D0:F0 PIRQ ... Mar 08 11:50:58.957 pci_server.3..0 pci_dbg 0 DEBUG,1,0,3 [3:2]: intpin_to_pirq(): B1:D0:F0 swizzle intpin A --> intpin A Mar 08 11:50:58.957 pci_server.3..0 pci_dbg 0 DEBUG,1,0,3 [3:2]: intpin_to_pirq(): B0:D1:F0 swizzle intpin A --> intpin B Mar 08 11:50:58.957 pci_server.3..0 pci_dbg 0 DEBUG,1,0,3 [3:2]: intpin_to_pirq(): B1:D0:F0 on PIRQ B Mar 08 11:50:58.957 pci_server.3..0 pci_dbg 0 DEBUG,1,1,3 [3:2]: B1:D0:F0 INTA --> PIRQB Mar 08 11:50:58.957 pci_server.3..0 pci_dbg 0 DEBUG,1,1,3 [3:2]: PIRQB --> IRQ 0 Mar 08 11:50:58.957 pci_server.3 pci_log 0 INFO ,1,2,3 [3:2]: hw_alloc_irq(B1:D0:F0, 1, 0x0, 1, 806b110) OK [PCI_ERR_OK] Mar 08 11:50:58.957 pci_server.3 pci_log 0 INFO ,1,2,3 [3:2]: hw_free_irq(B1:D0:F0, 1, 1, 806b110) OK [PCI_ERR_OK] Mar 08 11:50:58.957 pci_server.3..0 pci_dbg 0 DEBUG,1,0,3 [3:2]: intpin_to_pirq(): Determine B1:D0:F0 PIRQ ... Mar 08 11:50:58.957 pci_server.3..0 pci_dbg 0 DEBUG,1,0,3 [3:2]: intpin_to_pirq(): B1:D0:F0 swizzle intpin A --> intpin A Mar 08 11:50:58.957 pci_server.3..0 pci_dbg 0 DEBUG,1,0,3 [3:2]: intpin_to_pirq(): B0:D1:F0 swizzle intpin A --> intpin B Mar 08 11:50:58.957 pci_server.3..0 pci_dbg 0 DEBUG,1,0,3 [3:2]: intpin_to_pirq(): B1:D0:F0 on PIRQ B Mar 08 11:50:58.957 pci_server.3..0 pci_dbg 0 DEBUG,1,1,3 [3:2]: B1:D0:F0 INTA --> PIRQB Mar 08 11:50:58.957 pci_server.3..0 pci_dbg 0 DEBUG,1,1,3 [3:2]: PIRQB --> IRQ 0 Mar 08 11:50:58.957 pci_server.3 pci_log 0 INFO ,1,2,3 [3:2]: hw_alloc_irq(B1:D0:F0, 1, 0x0, 1, 806b110) OK [PCI_ERR_OK] # #