Hugh,

Hugh Brown wrote:
Armin,

In your previous e-mail, the device doesn't have a capability 5 as it doesn't support MSI.

OK ... I have to check this with the manufacturer of the board.

The capabilities structure is a linked list, so you cannot miss a capability.

When the local APIC is enabled it gives you 8 more IRQ interrupts and we number these from 16 to 23, so the interrupt that you see below is not an MSI interrupt, but a normal IRQ. We number MSI/X interrupts from 0x100 upwards, but the PCI interrupt line register only contains 8 bits, so you will see the interrupt line register set to 0x00 for interrupt 0x100 and to 0x01 for interrupt 0x101 etc. The correct interrupt is sent to the driver in the interrupt attach structure as this value is 32-bits.

Many thanks for the clarification.

Regards

--Armin


Hugh.

-- 
Hugh Brown
QNX Software Systems Limited
1001 Farrar Rd.,
Ottawa. ON. K2K 0B3.
Telephone: 613-591-0931



From: Armin Steinhoff <community-noreply@qnx.com>
Reply-To: "general-community@community.qnx.com" <general-community@community.qnx.com>
Date: Wednesday, 4 July, 2012 6:56 PM
To: "general-community@community.qnx.com" <general-community@community.qnx.com>
Cc: Info System - IS Notifications <is-notifications@qnx.com>, Info System - IS Notifications <is-notifications@qnx.com>, Info System - IS Notifications <is-notifications@qnx.com>, Info System - IS Notifications <is-notifications@qnx.com>
Subject: Re: PCI Express

Hugh,

I have hier the same PCI Express board placed in an other slot. There are not the MSI capabilitie set,
but a MSI interrupt of 18 has been assigned. The crazy point is: the board is working in default mode with that IRQ!

09:04.0 Unassigned class [ff00]: PLX Technology, Inc. Device 86e1 (rev ac)
    Subsystem: SOFTING GmBH Device 002b
    Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
    Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
    Latency: 32, Cache Line Size: 64 bytes
    Interrupt: pin A routed to IRQ 18
    Region 0: Memory at 55480000 (32-bit, non-prefetchable)
    Region 1: I/O ports at 3000
    Region 2: Memory at 55400000 (32-bit, non-prefetchable)
    Capabilities: [40] Power Management version 0    <<<<=== no MSI caps !
        Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
        Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
    Capabilities: [48] CompactPCI hot-swap <?> <<<=== wrong!
    Capabilities: [4c] Vital Product Data
        Not readable
00: b5 10 e1 86 17 00 b0 02 ac 00 00 ff 10 20 00 00     <<< dump of the config space
10: 00 00 48 55 01 30 00 00 00 00 40 55 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 a0 14 2b 00
30: 00 00 00 00 40 00 00 00 00 00 00 00 12 01 00 00

Regards

--Armin



Hugh Brown wrote:
If you run 'pci -v' you will see all of the capabilities for all of the devices. The MSI or MSIX interrupt is only assigned once a pci_attach_device() has been performed, so if there is no driver running against a MSI or MSIX capable device, you will see the standard IRQ interrupt. See the attached pci.txt file where the gigabit Ethernet device has been assigned MSIX interrupts.

-- 
Hugh Brown
QNX Software Systems Limited
1001 Farrar Rd.,
Ottawa. ON. K2K 0B3.
Telephone: 613-591-0931



From: Armin Steinhoff <community-noreply@qnx.com>
Reply-To: "general-community@community.qnx.com" <general-community@community.qnx.com>
Date: Wednesday, 4 July, 2012 2:33 PM
To: "general-community@community.qnx.com" <general-community@community.qnx.com>
Cc: Info System - IS Notifications <is-notifications@qnx.com>, Info System - IS Notifications <is-notifications@qnx.com>, Info System - IS Notifications <is-notifications@qnx.com>, Info System - IS Notifications <is-notifications@qnx.com>
Subject: Re: PCI Express

Hugh Brown wrote:
The PCI server enables either the MSI or MSIX capability depending on
which is selected and also assigns MSI/X IRQ numbers to the device. Is
this what you are talking about?
Yes and No.
>From the example provided by the pci_attach_device documentation:

if (pci_read_config8 (bus, devfn, cap_ptr, 1, &cap))  <<<--- that means the OS must set the capabilities before
                                                                                 <<<--- but in the dumps of pci or lspci  I saw
                                                                                 <<<--- never entries of the MSI capabilities of PCIe devices
    return (-1);
if (cap == PCI_CAP_MSI)

The assigned IRQ seems alway connected to an INTx line ... which is the default non MSI mapping.

Regards

--Armin