Class = Memory (RAM) Vendor ID = 10eeh, Xilinx Corporation Device ID = 9h, Unknown Unknown PCI index = 0h Class Codes = 050000h Revision ID = 0h Bus number = 2 Device number = 0 Function num = 0 Status Reg = 10h Command Reg = 7h I/O space access enabled Memory space access enabled Bus Master enabled Special Cycle operations ignored Memory Write and Invalidate disabled Palette Snooping disabled Parity Error Response disabled Data/Address stepping disabled SERR# driver disabled Fast back-to-back transactions to different agents disabled PCI INTx enabled Header type = 0h Single-function BIST = 0h Build-in-self-test not supported Latency Timer = 0h Cache Line Size= 8h un-cacheable BAR - 0 [Mem] = fd7ff000h 32bit length 1024 enabled BAR - 1 [Mem] = fd000000h 32bit length 4194304 enabled BAR - 2 [Mem] = fd7fe000h 32bit length 128 enabled Subsystem Vendor ID = 10eeh Subsystem ID = 9h Max Lat = 0ns Min Gnt = 0ns PCI Int Pin = INT A Interrupt line = 10 CPU Interrupt = ah Capabilities Pointer = 40h Capability ID = 1h - Power Management Capabilities = 7e03h - 8h Capability ID = 5h - Message Signaled Interrupts Capabilities = 82h - 0h Capability ID = 10h - PCI Express Capabilities = 1h - 8fc2h Device Dependent Registers: 0x040: 0148 037e 0800 0000 0558 8200 0000 0000 0x050: 0000 0000 0000 0000 1000 0100 c28f 0000 0x060: 1028 0000 11f4 0300 0000 1100 0000 0000 0x070: 0000 0000 0000 0000 0000 0000 0000 0000 ... 0x0f0: 0000 0000 0000 0000 0000 0000 0000 0000