But at FPGA side they receiving data through this code

From: Armin Steinhoff [mailto:community-noreply@qnx.com]
Sent: Thursday, June 21, 2012 5:08 PM
To: general-community@community.qnx.com
Cc: srilakshmi; srilakshmi
Subject: Re: PCI Express

srilakshmi wrote:

When I am executing above attached code I am getting configuration data..

Yes ... but you are reading configuration data from an uninitialzed device which provides invalid data.
Just some comments about your code:

pci_read_config32(2,0,0x04,10,&buf); --> why not are inf.BusNumber and inf. DevFunc not used ?

You have to check the memory type by PCI_IS_MEM() before you use PCI_MEM_ADDR( )
It's not a good idea to map an IO address into normal memory.

If you have a support contract ... go back to QNX 6.4.1.

--Armin

From: Armin Steinhoff [mailto:community-noreply@qnx.com]
Sent: Thursday, June 21, 2012 4:20 PM
To: general-community@community.qnx.com
Cc: srilakshmi; srilakshmi
Subject: Re: PCI Express

srilakshmi wrote:

How to enable the interrupt line?

Your basically problem is that the board (FPGA core?) doesn't initialize at hardware level the PCI interface.
The configuration data of the PCI interfaces are normaly provided by a serial ROM.
Please checkout why the PCI interface isn't initialized!

Nothing can be done with an uninitialized PCI interface ...

--Armin

Please provide me sample code or document or explanaion

From: Armin Steinhoff [mailto:community-noreply@qnx.com]
Sent: Thursday, June 21, 2012 2:08 PM
To: general-community@community.qnx.com
Cc: srilakshmi; srilakshmi
Subject: Re: PCI Express

srilakshmi wrote:

Through the attached file I am sending the output of pci -vvv.

My project board contains both Intel chip and FPGA chip on same board.

through PCI express slot we are connecting Xilinx board. Through PCIe we are

communicating with each other. And the result is checking at FPGA side by

Chipscope software.

Ok ... and this is a board from Xilinx with the vendor ID 10EEh ??

This board seems to be completely disabled ...
No I/O memory, no memory, no connection to an interrupt line.
Also the memory of 128 bytes referenced by BAR[0] is disabled !

Please see the marks at the printouts of the "pci" command:

Vendor ID      = 10eeh, Xilinx Corporation
Device ID      = 7h, Unknown Unknown
PCI index      = 0h
Class Codes    = 050000h
Revision ID    = 0h
Bus number     = 2
Device number = 0
Function num   = 0
Status Reg     = 10h
Command Reg    = 0h
    I/O space access disabled                    <<<============ !!!
    Memory space access disabled            <<<============ !!!
    Bus Master disabled
    Special Cycle operations ignored
    Memory Write and Invalidate disabled <<<============ !!!
    Palette Snooping disabled
    Parity Error Response disabled
    Data/Address stepping disabled
    SERR# driver disabled
    Fast back-to-back transactions to different agents disabled
    PCI INTx enabled
Header type    = 0h Single-function
BIST           = 0h Build-in-self-test not supported
Latency Timer = 0h
Cache Line Size= 0h
BAR - 0 [Mem] = 0h 32bit length 128 disabled <<<========= !!!
Subsystem Vendor ID = 10eeh
Subsystem ID        = 7h
Max Lat        = 0ns
Min Gnt        = 0ns
PCI Int Pin    = INT A
Interrupt line = no connection <<<========== !!!

And the previous which you have sent to me is not working because

pci_dev_info predefined structure doesn't contain members like HeaderType,

CpuBmstrTranslation, CpuIsaTranslation, CpuMemTranslation, NumIrq,

info.MsiDefs[i].count

The example code previously posted by Hugh Brown is for QNX 6.5.
Are you working with QNX 6.4.x ??

Best Regards

--Armin

http://www.steinhoff-automation.com

Srilakshmi

-----Original Message-----

From: Armin Steinhoff [mailto:community-noreply@qnx.com]

Sent: Wednesday, June 20, 2012 11:59 PM

To: general-community@community.qnx.com

Cc: srilakshmi; srilakshmi

Subject: Re: PCI Express

srilakshmi wrote:

How to recognize interrupts coming from FPGA through PCI?

is this a board with a PCI interface together with separate FPGA chip??

Or is the PCI interface realized as a core of the FPGA?

Could you post the output of "pci -vvv" ?

Please provide me

document or code regarding this.

_______________________________________________

General

http://community.qnx.com/sf/go/post93788

To cancel your subscription to this discussion, please e-mail

general-community-unsubscribe@community.qnx.com

-----

No virus found in this message.

Checked by AVG - www.avg.com

Version: 2012.0.2177 / Virus Database: 2437/5081 - Release Date: 06/20/12

_______________________________________________

General

http://community.qnx.com/sf/go/post93792

To cancel your subscription to this discussion, please e-mail general-community-unsubscribe@community.qnx.com

No virus found in this message.
Checked by AVG - www.avg.com
Version: 2012.0.2177 / Virus Database: 2437/5082 - Release Date: 06/20/12