Note - this feature is intended for very specific use cases and may cause unexpected behaviour when used otherwise - please consult with us if you intend to try it

'For MIPS and PPC Book E family chips, when a TLB miss occurs, the CPU throws and exception and software is responsible for transferring the proper page table entry into the TLB to allow the memory reference to complete. If you've got an area of memory that you reference a lot, you'd like to be able 'lock', or wire those entries into the TLB so you don't get any miss exceptions.

We added some code that sits on top of the variable page size support to allow people to do this. What you have to do is use the SHMCTL_HIGHUSAGE flag of the shm_ctl() function. When the page table manipulation code sees this flag on a mapping request, it arranges the entry to be loaded into the TLB and also sets up the address space switch code (by replacing the value in the memmgr.aspace function with the address of the wire_aspace function) to start saving/restoring the wired entries for the process.

This feature was only implemented for MIPS and PowerPC architectures.