Forum Topic - how to enable SSE and SSE2 instruction sets in GCC or QCC when compiling? : (3 Items)
   
how to enable SSE and SSE2 instruction sets in GCC or QCC when compiling?  
how to enable SSE and SSE2 instruction sets  in GCC or  QCC  when  compiling? 

I have already found the following code in OPENCV source code . How can I make them  be valid?


#if defined __SSE2__ || defined _M_X64  || (defined _M_IX86_FP && _M_IX86_FP >= 2)
#  include "emmintrin.h"
#  define CV_SSE 1
#  define CV_SSE2 1
#  if defined __SSE3__ || (defined _MSC_VER && _MSC_VER >= 1500)
#    include "pmmintrin.h"
#    define CV_SSE3 1
#  endif
#  if defined __SSSE3__  || (defined _MSC_VER && _MSC_VER >= 1500)
#    include "tmmintrin.h"
#    define CV_SSSE3 1
#  endif
#  if defined __SSE4_1__ || (defined _MSC_VER && _MSC_VER >= 1500)
#    include <smmintrin.h>
#    define CV_SSE4_1 1
#  endif
#  if defined __SSE4_2__ || (defined _MSC_VER && _MSC_VER >= 1500)
#    include <nmmintrin.h>
#    define CV_SSE4_2 1
#  endif
#  if defined __AVX__ || (defined _MSC_FULL_VER && _MSC_FULL_VER >= 160040219)
// MS Visual Studio 2010 (2012?) has no macro pre-defined to identify the use of /arch:AVX
// See: http://connect.microsoft.com/VisualStudio/feedback/details/605858/arch-avx-should-define-a-predefined-macro-in-
x64-and-set-a-unique-value-for-m-ix86-fp-in-win32
#    include <immintrin.h>
#    define CV_AVX 1
#    if defined(_XCR_XFEATURE_ENABLED_MASK)
#      define __xgetbv() _xgetbv(_XCR_XFEATURE_ENABLED_MASK)
#    else
#      define __xgetbv() 0
#    endif
#  endif
#endif


#if (defined WIN32 || defined _WIN32) && defined(_M_ARM)
# include <Intrin.h>
# include "arm_neon.h"
# define CV_NEON 1
# define CPU_HAS_NEON_FEATURE (true)
#elif defined(__ARM_NEON__)
#  include <arm_neon.h>
#  define CV_NEON 1
#  define CPU_HAS_NEON_FEATURE (true)
#endif

#ifndef CV_SSE
#  define CV_SSE 0
#endif
#ifndef CV_SSE2
#  define CV_SSE2 0
#endif
#ifndef CV_SSE3
#  define CV_SSE3 0
#endif
#ifndef CV_SSSE3
#  define CV_SSSE3 0
#endif
#ifndef CV_SSE4_1
#  define CV_SSE4_1 0
#endif
#ifndef CV_SSE4_2
#  define CV_SSE4_2 0
#endif
#ifndef CV_AVX
#  define CV_AVX 0
#endif
#ifndef CV_NEON
#  define CV_NEON 0
#endif
Re: how to enable SSE and SSE2 instruction sets in GCC or QCC when compiling?  
See post106962 - depending on the NTO compiler you are using it might 
not yet have support for sse4.

On 13-11-22 07:54 AM, robort smith wrote:
> how to enable SSE and SSE2 instruction sets  in GCC or  QCC  when  compiling?
>
> I have already found the following code in OPENCV source code . How can I make them  be valid?

Re: how to enable SSE and SSE2 instruction sets in GCC or QCC when compiling?  
See post106962 - depending on the NTO compiler you are using it might
not yet have support for sse4.

On 13-11-22 07:54 AM, robort smith wrote:
> how to enable SSE and SSE2 instruction sets  in GCC or  QCC  when  compiling?
>
> I have already found the following code in OPENCV source code . How can I make them  be valid?