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Forum Topic - etfs driver - requirements for NAND devices and adopting driver: (3 Items)

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Martin Reichherzer(deleted)

10/12/2011 8:56 AM

post89328

etfs driver - requirements for NAND devices and adopting driver

Hello,

I'm in search for information that helps me to select a apropriate NAND device for a new design. We would like to have a
 NAND size of at least 16Gbit/2GB.
Processors we are planning to use are:
- i.Mx53: there is a QNX driver in the i.MX53EVK BSP (for 2048Byte + 64Byte page size)
-P2020: there is also a driver available but only for 512Byte page size. According to the QNX help article about system 
limits there is no ECC support for 512 Byte size. Is this right?

Regarding the newer Micron NAND devices, all seem to have a page size of 2048byte + 96byte (not 64byte). What would be 
necessary to get those devices running with the drivers mentioned above. Is there documentation available regarding 
those adoptions? Is there a documentation for lib-etfs?

Thanks
Martin

Martin Reichherzer(deleted)

10/12/2011 9:39 AM

post89331

Re: etfs driver - requirements for NAND devices and adopting driver

Sorry got it wrong (2048byte + 64 byte is correct).
But nearly all the bigger NAND devices e.g. from Micron (>=16Gbit) have a page size of 4096byte + 224byte. The question 
remains the same what must be done to get those running?

Martin

David Sarrazin

10/13/2011 11:45 AM

post89376

Re: etfs driver - requirements for NAND devices and adopting driver

Martin,

You'll need to modify the "struct spare" in hardware/etfs/nand2048/<boardname>/devio.h

That structure has to match the layout of the spare area that is dicated by the hardware.  The structure normally will 
contain things like the base etfs_trans (fid, seqno,cluster), plus a CRC or ECC.   The default 64-byte structure is only
 for use with software 1-bit ECC, so the fields have been packed without regard for the hardware layout.  If your device
 supports hardware ECC (anything stronger than 1-bit will require hardware support), then you'll need to modify the 
structure layout to put the ECC fields at the offsets that the hardware describes for that controller.

Once that is done, devio_readtrans(), devio_readcluster(), devio_postcluster() have to be modified to work with the new 
structure.  

> Sorry got it wrong (2048byte + 64 byte is correct).
> But nearly all the bigger NAND devices e.g. from Micron (>=16Gbit) have a page
>  size of 4096byte + 224byte. The question remains the same what must be done 
> to get those running?
> 
> Martin

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