Hi QNX,

          QNX IDE 6.5SP1,  Xilinx zc702 BSP

I am working on zynq gpio interrupt for both MIO and EMIO. My C application program is able to toggle MIO or EMIO pin, 
and get interrupt from MIO gpio pin correctly. However, EMIO gpio pin had trouble to receive interrupt call.

Xilinx Zynq gpio is divided into 4 banks. and all banks shares the same interrupt according to init_intrinfo.c, 

     Bank0 (MIO  32 pins) from  [0,31]      ~~~ I tested MIO_0 pin
     Bank1 (MIO  22 pins) from  [32,53]
     Bank2 (EMIO 32 pins) from [54, 85]  ~~~ I tested EMIO_54 pin
     bank3 (EMIO 32 pins) from [86, 117]

I sense that callout_interrupt_xzynq_gpio.S may assume that every bank had 32 pins, which is not reflecting the glitch 
from Bank2 to Bank3. Therefore, all the EMIO interrupts are misfired. 

Attach the callout.S and init_intrinfo.c, 

please advise, thanks in advance,

Mike