Hi all

I still wonder about on Arm smp platform , Do QNX need a memory barrier ?

On x86 platform, this is the code 

# define __inline_InterruptEnable()				\
	((void)({									\
			__asm__ __volatile__ (				\
				  "sti"							\
				  : : : "memory");				\
		}))

but on Arm platform , seems no memory barrier 

static __inline__ void __attribute__((__unused__))
	__inline_InterruptEnable(void)
{
	if (__cpu_flags & __ARM_CPU_FLAG_V6) {
		__asm__ __volatile__("cpsie	i");
	} else {
		unsigned	__tmp;

		__asm__ __volatile__(
		  "mrs	%0, cpsr;"
		  "bic	%0, %0, #0x80;"
		  "msr	cpsr, %0;"
		  : "=r" (__tmp)
		);
	}
}

only in this will have the dmb instruction

static __inline__ void __attribute__((__unused__))
	__inline_InterruptLock(struct intrspin *__spin)
{
	__inline_InterruptDisable();
	if (__cpu_flags & __ARM_CPU_FLAG_SMP) {
		volatile unsigned	val;
		unsigned			tmp;
		__asm__ __volatile__(
			  "0:	ldrex	%0, [%3];"
			  "		teq		%0, #0;"
			  "		wfene;"
			  "		strexeq	%1, %2, [%3];"
			  "		teqeq	%1, #0;"
			  "		bne		0b;"
			  : "=&r" (val), "=&r"(tmp)
			  : "r" (1), "r" (&__spin->value)
		);
		if (__cpu_flags & __ARM_CPU_FLAG_V7) {
			__asm__ __volatile__("dmb");
		} else {
			__asm__ __volatile__("mcr	p15, 0, %0, c7, c10, 4" : : "r"(0));
		}
	}
}

Is there any special reason for this ?

And on Linux platform ,when enable irq ,always have a memory barrier 

http://lxr.linux.no/linux+v3.8.6/arch/arm/include/asm/irqflags.h

Why QNX dont need this ?

Thanks and regards