http://community.qnx.com/sf/discussion/do/listTopics/projects.bsp/discussion.bsp Posts for QNX BSPs http://community.qnx.com/sf/go/post102444 The BIOS information is written by the BIOS itself and not by a utility or startup. As far as I know you need to scan for the SMBIOS anchor and use that to figure out where the tables are stored to read the BIOS data - Which smbios code are you referring to? Wed, 19 Jun 2013 16:47:56 GMT http://community.qnx.com/sf/go/post102444 Gervais Mulongoy 2013-06-19T16:47:56Z http://community.qnx.com/sf/go/post102443 I tried this in QNX650. > Hi, > > Which utility or startup program writes the BIOS information into /dev/mem? > and how to make it work? > > I tried to read BIOS date from /dev/mem using smbios code. But its says...no > SMIBIOS or DMI entry found. > > Please help me. > > Thank you > Regards > anand Wed, 19 Jun 2013 16:20:21 GMT http://community.qnx.com/sf/go/post102443 anand babu 2013-06-19T16:20:21Z http://community.qnx.com/sf/go/post102442 Hi, Which utility or startup program writes the BIOS information into /dev/mem? and how to make it work? I tried to read BIOS date from /dev/mem using smbios code. But its says...no SMIBIOS or DMI entry found. Please help me. Thank you Regards anand Wed, 19 Jun 2013 16:19:16 GMT http://community.qnx.com/sf/go/post102442 anand babu 2013-06-19T16:19:16Z http://community.qnx.com/sf/go/post102351 Hello, I was having exactly the same problem, despite following the instructions in the MPC Data Quick Start guide, including manually running tar on the CompMgr patch. But in fact a colleague had previously been provided with a solution from QNX, which is to install the following two libraries that are missing: libkeymap.a in folder QNX650/target/qnx6/armle-v7/lib libinput.a in folder QNX650/target/qnx6/armlet-v7/usr/lib Hope this helps others. Sandy Mon, 17 Jun 2013 14:58:46 GMT http://community.qnx.com/sf/go/post102351 Sandy Kellagher 2013-06-17T14:58:46Z http://community.qnx.com/sf/go/post102340 its solved now, it was environment variable problem. thanks everyone for support. Mon, 17 Jun 2013 05:41:27 GMT http://community.qnx.com/sf/go/post102340 Shamim Mohammad 2013-06-17T05:41:27Z http://community.qnx.com/sf/go/post102336 Mr. Altan, Can we kindly ask you to connect with us? Here is my e-mail adress : s-sunger@target.com.tr Looking forward to hearing you. Best regards, Sat, 15 Jun 2013 16:06:58 GMT http://community.qnx.com/sf/go/post102336 Seyfettin Sünger 2013-06-15T16:06:58Z http://community.qnx.com/sf/go/post102325 In my Windows XP environment (with QNX Momentics 6.5.0 installed, and the 6.5.0 SP1 patch applied), I've just downloaded the BSP, and I was able to successfully build it both at the command line, and by importing it into the IDE and building it. It built to completion in both cases. My suspicion is that your QNX Momentics 6.5.0 SP1 environment might be corrupted somehow, or perhaps your PATH isn't correct. I notice that your 6.5.0 installation is at c:\FOR_GF\QNX650SP1\.... the normal (default) installation path is c:\QNX650\; perhaps the path in your environment doesn't correspond to this custom installation? ------------------------------------- Dave Green QNX Software Systems Limited dgreen@qnx.com On 13-06-14 11:25 AM, "Shamim Mohammad" <community-noreply@qnx.com> wrote: >this library is available at >C:\FOR_GF\QNX650SP1\target\qnx6\armle-v7\usr\lib. > >do i need to copy libdrvrS.a at >/usr/qnx650/target/qnx6/armle-v7/usr/lib/? > >if this is the case does it mean this path >/usr/qnx650/target/qnx6/armle-v7/usr/lib/ is hardcoded some where in make >file? > > > >_______________________________________________ > >QNX BSPs >http://community.qnx.com/sf/go/post102321 >To cancel your subscription to this discussion, please e-mail >general-bsp-unsubscribe@community.qnx.com Fri, 14 Jun 2013 15:49:57 GMT http://community.qnx.com/sf/go/post102325 David Green 2013-06-14T15:49:57Z http://community.qnx.com/sf/go/post102321 this library is available at C:\FOR_GF\QNX650SP1\target\qnx6\armle-v7\usr\lib. do i need to copy libdrvrS.a at /usr/qnx650/target/qnx6/armle-v7/usr/lib/? if this is the case does it mean this path /usr/qnx650/target/qnx6/armle-v7/usr/lib/ is hardcoded some where in make file? Fri, 14 Jun 2013 15:25:48 GMT http://community.qnx.com/sf/go/post102321 Shamim Mohammad 2013-06-14T15:25:48Z http://community.qnx.com/sf/go/post102314 Please double check if you have the libdrvrS.a in the folder: /usr/qnx650/target/qnx6/armle-v7/usr/lib/ Fri, 14 Jun 2013 14:05:49 GMT http://community.qnx.com/sf/go/post102314 Zhen Wang 2013-06-14T14:05:49Z http://community.qnx.com/sf/go/post102311 I am still getting same compilation error. make[7]: *** No rule to make target `libdrvrS.a', needed by `C:/Users/shamim/De ktop/bsps/mx51/src/lib/dma/sdma/imx51/arm/so.le/libdma-sdma-imx51.so'. Stop. make[7]: Leaving directory `C:/Users/shamim/Desktop/bsps/mx51/src/lib/dma/sdma/ mx51/arm/so.le' make[6]: *** [install] Error 2 make[6]: Leaving directory `C:/Users/shamim/Desktop/bsps/mx51/src/lib/dma/sdma/ mx51/arm' make[5]: *** [install] Error 2 make[5]: Leaving directory `C:/Users/shamim/Desktop/bsps/mx51/src/lib/dma/sdma/ mx51' make[4]: *** [install] Error 2 make[4]: Leaving directory `C:/Users/shamim/Desktop/bsps/mx51/src/lib/dma/sdma' make[3]: *** [install] Error 2 make[3]: Leaving directory `C:/Users/shamim/Desktop/bsps/mx51/src/lib/dma' make[2]: *** [install] Error 2 make[2]: Leaving directory `C:/Users/shamim/Desktop/bsps/mx51/src/lib' make[1]: *** [install] Error 2 make[1]: Leaving directory `C:/Users/shamim/Desktop/bsps/mx51/src' make: *** [install] Error 2 Fri, 14 Jun 2013 13:53:48 GMT http://community.qnx.com/sf/go/post102311 Shamim Mohammad 2013-06-14T13:53:48Z http://community.qnx.com/sf/go/post102309 Thanks David we have tried the steps you mentioned, we got the following errors: We have attached the image of the error: C:/FOR_GF/QNX650SP1/host/win32/x86/usr/bin/qcc -Vgcc_ntoarm -c -O -Wc,-Wall -DND EBUG -I. -I/cygdrive/c/Users/ugesh/Desktop/bsps/mx51/src/lib/dma/sdma/imx51/ar m/dll.le.imx51.sdma -I/cygdrive/c/Users/ugesh/Desktop/bsps/mx51/src/lib/dma/sdma /imx51/arm/a.le -I/cygdrive/c/Users/ugesh/Desktop/bsps/mx51/src/lib/dma/sdma/imx 51/arm -I/cygdrive/c/Users/ugesh/Desktop/bsps/mx51/src/lib/dma/sdma/imx51 -I/cyg drive/c/Users/ugesh/Desktop/bsps/mx51/src/lib/dma/sdma -I/cygdrive/c/Users/ugesh /Desktop/bsps/mx51/src/lib/dma -I/cygdrive/c/Users/ugesh/Desktop/bsps/mx51/src/l ib/dma/public -I/cygdrive/c/Users/ugesh/Desktop/bsps/mx51/src/lib/dma/../../../i nstall/usr/include -IC:/FOR_GF/QNX650SP1/target/qnx6/usr/include -EL -DVARIANT_a -DVARIANT_le -DVARIANT_imx51 -DVARIANT_sdma -DBUILDENV_qss /cygdrive/c/Users/ugesh/Desktop/bsps/mx51/src/lib/dma/sdma/api.c cc1: error: /cygdrive/c/Users/ugesh/Desktop/bsps/mx51/src/lib/dma/sdma/api.c: No such file or directory cc: C:/FOR_GF/QNX650SP1/host/win32/x86/usr/lib/gcc/arm-unknown-nto-qnx6.5.0/4.4. 2/cc1 caught signal 1 C:/FOR_GF/QNX650SP1/target/qnx6/usr/include/mk/qrules.mk:59: recipe for target ` api.o' failed make[7]: *** [api.o] Error 1 make[7]: Leaving directory `/cygdrive/c/Users/ugesh/Desktop/bsps/mx51/src/lib/dm a/sdma/imx51/arm/a.le' recurse.mk:98: recipe for target `install' failed make[6]: *** [install] Error 2 make[6]: Leaving directory `/cygdrive/c/Users/ugesh/Desktop/bsps/mx51/src/lib/dm a/sdma/imx51/arm' recurse.mk:98: recipe for target `install' failed make[5]: *** [install] Error 2 make[5]: Leaving directory `/cygdrive/c/Users/ugesh/Desktop/bsps/mx51/src/lib/dm a/sdma/imx51' recurse.mk:98: recipe for target `install' failed make[4]: *** [install] Error 2 make[4]: Leaving directory `/cygdrive/c/Users/ugesh/Desktop/bsps/mx51/src/lib/dm a/sdma' recurse.mk:98: recipe for target `install' failed make[3]: *** [install] Error 2 make[3]: Leaving directory `/cygdrive/c/Users/ugesh/Desktop/bsps/mx51/src/lib/dm a' recurse.mk:98: recipe for target `install' failed make[2]: *** [install] Error 2 make[2]: Leaving directory `/cygdrive/c/Users/ugesh/Desktop/bsps/mx51/src/lib' recurse.mk:98: recipe for target `install' failed make[1]: *** [install] Error 2 make[1]: Leaving directory `/cygdrive/c/Users/ugesh/Desktop/bsps/mx51/src' Makefile:33: recipe for target `install' failed make: *** [install] Error 2 I runned it Windows command prompt and in cygwin but got the same error Fri, 14 Jun 2013 13:44:57 GMT http://community.qnx.com/sf/go/post102309 ugesh gurram 2013-06-14T13:44:57Z http://community.qnx.com/sf/go/post102305 Thanks David Green, Can you please explain the following Question because what in the link you provided is a generic bootup sequence? 1) What is the bootup sequence of QNX, does it changes with board on which it will be flashed? Fri, 14 Jun 2013 13:02:58 GMT http://community.qnx.com/sf/go/post102305 ugesh gurram 2013-06-14T13:02:58Z http://community.qnx.com/sf/go/post102304 Does the BSP build for you at the command line? # mkdir bsps # cd bsps # mkdir mx51 # cd mx51 # cp /downloads/BSP_freescale-imx51-evk_br-650_be-650sp1_SVN700054_JBN10.zip . # unzip BSP_freescale-imx51-evk_br-650_be-650sp1_SVN700054_JBN10.zip # make ------------------------------------- Dave Green QNX Software Systems Limited dgreen@qnx.com On 13-06-14 8:38 AM, "Shamim Mohammad" <community-noreply@qnx.com> wrote: >Hi David, > >I have followed following steps: Please let me know if I am making any >mistake to build the BSP. > >Step 1. Download Freescale i.MX51 EVK BSP for QNX Momentics 6.5.0 SP1 >from QNX BSP directory. > >Step 2. Imported To QNX650SP1 environment as QNX Source Package and BSP. > >Step 3. Right click on imported project source and click build project to >build the BSP. > > > Same steps I have followed for other QNX650SP1 BSP, like omap 5432 and >omap panda and it compiles properly. > > > > >_______________________________________________ > >QNX BSPs >http://community.qnx.com/sf/go/post102300 >To cancel your subscription to this discussion, please e-mail >general-bsp-unsubscribe@community.qnx.com Fri, 14 Jun 2013 12:57:32 GMT http://community.qnx.com/sf/go/post102304 David Green 2013-06-14T12:57:32Z http://community.qnx.com/sf/go/post102303 All of the information you're requesting (and more) can be found in the 'Building Embedded Systems' documentation that I referenced earlier. I suggest you look there for answers to your questions. Regards, Dave Fri, 14 Jun 2013 12:54:12 GMT http://community.qnx.com/sf/go/post102303 David Green 2013-06-14T12:54:12Z http://community.qnx.com/sf/go/post102302 Hi, Even I am facing the same problem while building for i.MX51(BSP_freescale-imx51-evk_br-650_be-650sp1_SVN700054_JBN10) with QNX 6.5.0 SP1. I have given a trial and error method for the other thing like "when building i.MX51(bsp-nto650-freescale-i.mx51-evk-trunk) with QNX 6.5.0(not SP1) it is building properly". Only for SP1 I am facing the problem Fri, 14 Jun 2013 12:51:41 GMT http://community.qnx.com/sf/go/post102302 ugesh gurram 2013-06-14T12:51:41Z http://community.qnx.com/sf/go/post102300 Hi David, I have followed following steps: Please let me know if I am making any mistake to build the BSP. Step 1. Download Freescale i.MX51 EVK BSP for QNX Momentics 6.5.0 SP1 from QNX BSP directory. Step 2. Imported To QNX650SP1 environment as QNX Source Package and BSP. Step 3. Right click on imported project source and click build project to build the BSP. Same steps I have followed for other QNX650SP1 BSP, like omap 5432 and omap panda and it compiles properly. Fri, 14 Jun 2013 12:38:41 GMT http://community.qnx.com/sf/go/post102300 Shamim Mohammad 2013-06-14T12:38:41Z http://community.qnx.com/sf/go/post102299 Thanks for reply Mr. David Green, 1) If you u-boot is not a part of QNX BSP, then how do we change from "u-boot" to "IPL" and vice-versa and also which bootloader is better for configuring/tweaking the bootloader for a partiular hardware? 2) What is the bootup sequence of QNX, does it changes with board on which it will be flashed? 3) By default, how can we find out what bootloader the QNX is using? 4) Can we run any small aplication on this BSP, if you where can I find it? Fri, 14 Jun 2013 12:36:08 GMT http://community.qnx.com/sf/go/post102299 ugesh gurram 2013-06-14T12:36:08Z http://community.qnx.com/sf/go/post102297 I've just downloaded and built the i.MX51 BSP on a 'clean' 6.5.0 SP1 self-hosted system, and it built without any errors. libdrvrS.a ships with QNX Momentics 6.5.0 SP1, and can be found under: /usr/qnx650/target/qnx6/armle-v7/usr/lib/ Please describe the exact steps you are doing to build the BSP. Fri, 14 Jun 2013 12:15:31 GMT http://community.qnx.com/sf/go/post102297 David Green 2013-06-14T12:15:31Z http://community.qnx.com/sf/go/post102296 Yes, you can use either u-boot or IPL to boot a target board with QNX. u-boot is not a QNX product, but we will normally distribute u-boot binaries with our BSPs, so that the customer doesn't need to go looking for it elsewhere, and to ensure that the customer has the same u-boot version that we used to test and validate the BSP with. Hardware vendors often don't make it easy to find the right u-boot for their boards. The QNX IPL (Initial Program Loader) code ships with most of our BSPs. IPL is designed to replace u-boot, but doesn't necessarily contain all of the same functionality as u-boot. Normally it contains minimal hardware initialization and memory controller initialization, and then presents a few different boot options to the user (i.e. boot from NOR flash, or NAND flash, or serial download, or SD/MMC, depending on the capabilities of the hardware). Customers use it when they want to have the system boot in as short a time as possible, or if they want to have more control over other aspects of the boot sequence. It's generally easier to customize the IPL code to make the system boot exactly how you want, rather than modifying and re-building u-boot. You can find more information on QNX IPL in our Building Embedded Systems documentation, here: http://www.qnx.com/developers/docs/6.5.0/index.jsp?topic=%2Fcom.qnx.doc.neu trino_building%2Fload_process.html Regards, ------------------------------------- Dave Green QNX Software Systems Limited dgreen@qnx.com On 13-06-14 7:20 AM, "ugesh gurram" <community-noreply@qnx.com> wrote: >Hi All, > I have a few doubts regarding the bootloader. >1)Is Bootloader a part of BSP? >2) If so I have read like u-boot(Universal boorloader) is not a part of >BSP but IPL is a part of BSP and they are saying that we can boot either >from u-boot or IPL? >3) Which bootloader does QNX uses exactly and where can we find the >code/documentation for this? >4) What is the bootup sequence of QNX, does it changes with board on >which it will be flashed? > > Please help me in understanding the bootloader in QNX. > > > >_______________________________________________ > >QNX BSPs >http://community.qnx.com/sf/go/post102295 >To cancel your subscription to this discussion, please e-mail >general-bsp-unsubscribe@community.qnx.com Fri, 14 Jun 2013 12:05:32 GMT http://community.qnx.com/sf/go/post102296 David Green 2013-06-14T12:05:32Z http://community.qnx.com/sf/go/post102295 Hi All, I have a few doubts regarding the bootloader. 1)Is Bootloader a part of BSP? 2) If so I have read like u-boot(Universal boorloader) is not a part of BSP but IPL is a part of BSP and they are saying that we can boot either from u-boot or IPL? 3) Which bootloader does QNX uses exactly and where can we find the code/documentation for this? 4) What is the bootup sequence of QNX, does it changes with board on which it will be flashed? Please help me in understanding the bootloader in QNX. Fri, 14 Jun 2013 11:20:57 GMT http://community.qnx.com/sf/go/post102295 ugesh gurram 2013-06-14T11:20:57Z http://community.qnx.com/sf/go/post102290 Thanks for reply Mr. Zhen Wang. Yes I am using QNX650SP1 BSP and I am compiling in QNX650 SP1 environment only. after exploring more on it, Ii found that if I remove SDMA and deva folders from src/hardware then compilation is through with below two warnings. Warning: Host file 'deva-ctrl-mx-mx51evk.so' missing. Warning: Host file 'libdma-sdma-imx51.so' missing. Please let me know if compile this with Sdma and deva drivers. Fri, 14 Jun 2013 05:32:49 GMT http://community.qnx.com/sf/go/post102290 Shamim Mohammad 2013-06-14T05:32:49Z http://community.qnx.com/sf/go/post102270 Hi; The attached document shows the output of booting of QNX 6.5.0 with SP1 for OMAP3730 BSP. The ethernet device cannot be connected. sloginfo output is also included in the documet. I tried many things in order to solve problem but I can't fgure it out. What can be the problem, any suggestions? Thank you. Thu, 13 Jun 2013 16:24:53 GMT http://community.qnx.com/sf/go/post102270 Önder Altan 2013-06-13T16:24:53Z http://community.qnx.com/sf/go/post102262 I understand the issue, but this is a work-around needed for 6.5.0-based kernels. I will include this note in the user guide as a reference. Currently, there are no plans to include this as a kernel module. Thu, 13 Jun 2013 14:41:50 GMT http://community.qnx.com/sf/go/post102262 Payam Moradshahi 2013-06-13T14:41:50Z http://community.qnx.com/sf/go/post102261 I understand these user threads are doing WFI - which should be done in the kernel. However, as you have heard a few times, these threads are very intrusive to system profiling and difficult to explain them to a customer - short of telling him the kernel has a defect. Thu, 13 Jun 2013 14:31:00 GMT http://community.qnx.com/sf/go/post102261 Dennis Kellly 2013-06-13T14:31:00Z http://community.qnx.com/sf/go/post102260 The idle threads are needed for any 6.5.0-based kernel, due to an issue with kernel's idle thread in SMP mode. Rest assured they are doing nothing but issuing "wfi" (which is what the idle threads of SMP kernel should've been doing in the first place). They will be removed in the future releases. Thu, 13 Jun 2013 14:24:07 GMT http://community.qnx.com/sf/go/post102260 Payam Moradshahi 2013-06-13T14:24:07Z http://community.qnx.com/sf/go/post102259 Which BSP are you using? If It is the QNX650SP1 BSP. You should build it in QNX650 SP1 enviornment. Thu, 13 Jun 2013 14:10:59 GMT http://community.qnx.com/sf/go/post102259 Zhen Wang 2013-06-13T14:10:59Z http://community.qnx.com/sf/go/post102252 The 100% CPU cycle is normal. We will add it to the user guide. The dvfs manager is essentially creating its own "idle" threads at priority 1 and issuing WFI. With regards to your other issues, can you please start the manager with extra verbosity (maybe 4) and send me the sloginfo before and after you start your program. Thanks, Payam Thu, 13 Jun 2013 13:30:35 GMT http://community.qnx.com/sf/go/post102252 Payam Moradshahi 2013-06-13T13:30:35Z http://community.qnx.com/sf/go/post102239 Hi All, I am getting below compilation error for i.Mx51 BSP. Its giving error for library `libdrvrS.a but this library is not available in downloaded BSP. please help me to solve this error. /bsp-freescale-imx51-evk-src/src/lib/dma/sdma/sync.c make[7]: Leaving directory `D:/POC/bsp-freescale-imx51-evk-src/src/lib/dma/sdma/imx51/arm/so.le' make[7]: *** No rule to make target `libdrvrS.a', needed by `D:/POC/bsp-freescale-imx51-evk-src/src/lib/dma/sdma/imx51/arm/so.le/libdma-sdma-imx51.so'. Stop. make[6]: *** [install] Error 2 make[6]: Leaving directory `D:/POC/bsp-freescale-imx51-evk-src/src/lib/dma/sdma/imx51/arm' make[5]: Leaving directory `D:/POC/bsp-freescale-imx51-evk-src/src/lib/dma/sdma/imx51' make[5]: *** [install] Error 2 make[4]: *** [install] Error 2 make[4]: Leaving directory `D:/POC/bsp-freescale-imx51-evk-src/src/lib/dma/sdma' make[3]: *** [install] Error 2 make[3]: Leaving directory `D:/POC/bsp-freescale-imx51-evk-src/src/lib/dma' make[2]: *** [install] Error 2 make[2]: Leaving directory `D:/POC/bsp-freescale-imx51-evk-src/src/lib' make[1]: *** [install] Error 2 Thu, 13 Jun 2013 10:10:40 GMT http://community.qnx.com/sf/go/post102239 Shamim Mohammad 2013-06-13T10:10:40Z http://community.qnx.com/sf/go/post102235 Hi all, I tested the DVFS driver for imx6 chip on a SabreLite card. I saw in the system ressources view of momentics that DVFSmgr-imx6 driver used 100% of my CPU. And when I launch an exemple of the Qt framework (like deform) the application is very slow. Do you have any information about that? Thanks, Nicolas CUMIN Thu, 13 Jun 2013 09:01:58 GMT http://community.qnx.com/sf/go/post102235 nicolas cumin 2013-06-13T09:01:58Z http://community.qnx.com/sf/go/post102197 Is there any way to package dvfs as a kernel module (like aps) ? Then the idle threads would be kernel threads - not user threads - and all the accounting features would work normally. Wed, 12 Jun 2013 11:30:15 GMT http://community.qnx.com/sf/go/post102197 Dennis Kellly 2013-06-12T11:30:15Z http://community.qnx.com/sf/go/post102195 Good news! The pci_attach_device() will assign the correct addresses to the device, but when the application terminates or a pci_detach_device() function call is issued, the base address registers will be returned to their original values. If the pci_attach_device() call has the PCI_PERSIST flag set, then when the application terminates, the base address registers will retain their values and you will be able to see then with the pci command. On 2013-06-11 3:24 PM, "Sylvain Comtois" <community-noreply@qnx.com> wrote: >Hi Hugh, > > Ok, everything work's well. > > I update the boot image to start the pci-bios service with the -B >option. > I can use the original pci-bios provide with qnx 6.5.0 SP1. > I modified my code to add the pci_attach_device function but i don't >touch anything else. > > I still interest to know why when i use the pci -v command the >address of the bars are still incorrect until a start the pci_att command >you send to me. I will expect the address will be correct after we start >our application. It is possible to know exactly what the pci_att done ? > >Thank you for your help, Sylvain > > > > > > > > >_______________________________________________ > >QNX BSPs >http://community.qnx.com/sf/go/post102174 >To cancel your subscription to this discussion, please e-mail >general-bsp-unsubscribe@community.qnx.com Wed, 12 Jun 2013 11:24:50 GMT http://community.qnx.com/sf/go/post102195 Hugh Brown 2013-06-12T11:24:50Z http://community.qnx.com/sf/go/post102193 Hi all, i have just tested the dvfs manager for i.mx6. It works fine, do far. Are these idle threads inside dvfs really needed? Other tools, like top, do not know anything about the new dvfs idle-state and "top" as an example calculates the system-load without the need for private idle threads. Output from top for an idle system: 34 processes; 101 threads; CPU states: 99.8% user, 0.1% kernel CPU 0 Idle: 0.0% CPU 1 Idle: 0.0% CPU 2 Idle: 0.0% CPU 3 Idle: 0.0% Memory: 0 total, 849M avail, page size 4K PID TID PRI STATE HH:MM:SS CPU COMMAND 241695 5 1 Run 0:17:57 24.91% dvfsmgr-imx6 241695 3 1 Rdy 0:17:59 24.90% dvfsmgr-imx6 241695 4 1 Run 0:17:57 24.85% dvfsmgr-imx6 241695 2 1 Run 0:17:56 24.79% dvfsmgr-imx6 ... Min Max Average CPU 0 idle: 0% 0% 0% CPU 1 idle: 0% 0% 0% CPU 2 idle: 0% 0% 0% CPU 3 idle: 0% 0% 0% ... Regards Michael Wed, 12 Jun 2013 09:56:56 GMT http://community.qnx.com/sf/go/post102193 Michael Tasche 2013-06-12T09:56:56Z http://community.qnx.com/sf/go/post102192 Great. In the meantime, I've tried removing the cpu pseudo-op, and adding -me500v2 to the CCFLAGS in common.mk. Works. Ciao, Christoph > I've notified Freescale (the developer of this BSP), and we should have an > updated version posted shortly. > > Regards, > ------------------------------------- > Dave Green > QNX Software Systems Limited > dgreen@qnx.com > > > > > > On 13-06-11 11:22 AM, "Ryan Mansfield" <community-noreply@qnx.com> wrote: > > >On 13-06-11 11:18 AM, Christoph Nemmaier wrote: > >> Hi, > >> > >> Using QNX 6.5.0SP1 toolchain on Windows, compilation of > >>src/hardware/ipl/boards/p1010rdb/board.c fails with > >> > >> Assembler messages: > >> Error: unknown pseudo-op: `.cpu' > >> Error: Unrecognized opcode: `tlbwe' > >> > >> To compile the BSP, find the assembler called ntoppc-as.exe in > >>host\win32\x86\usr\bin. Along with it, there is ntoppc-as-2.22.exe, and, > >>from the original 6.5.0 installation, ntoppc-as-2.19.exe. > >> Replace ntoppc-as.exe by the 2.19 version, and the BSP will compile. > >>(Thanks to Sandra Taylor for pointing this out). > > > >The ppc .cpu directive was a QNX extension but it was long deprecated (~ > >6.4.x era), and was finally removed in binutils 2.22. The source should > >have been updated to use .march. > > > >Regards, > > > >Ryan Mansfield > > > > > > > > > > > >_______________________________________________ > > > >QNX BSPs > >http://community.qnx.com/sf/go/post102157 > >To cancel your subscription to this discussion, please e-mail > >general-bsp-unsubscribe@community.qnx.com > Wed, 12 Jun 2013 08:45:17 GMT http://community.qnx.com/sf/go/post102192 Christoph Nemmaier 2013-06-12T08:45:17Z http://community.qnx.com/sf/go/post102187 I also try 640*480 including in jade.conf. # 640x480 @ 60Hz (VGA) mode:htp=800,hsp=656,hsw=96,hdp=640,vtr=525,vsp=490,vsw=2,vdp=480,dcm=0x1900,refresh=60 And change the display.conf part in build like this: /etc/system/config/display.conf={ device \{ drivername=jade vid=0 did=0 deviceindex=0 modeopts=/etc/system/config/jade.conf display \{ xres=640 yres=480 refresh=60 pixel_format=argb1555 \} \} } But still had io-display: driver doesn't support, or not configured for "argb1555" at 640x480, 60Hz In your help said the resolution in display.conf only compare with chip.conf. As my understanding, the parameter like HTP, VSW, just is related to TFT-display, and I can not find anything about this in devg. Why does the driver have this error? Can you help me? Wed, 12 Jun 2013 05:24:16 GMT http://community.qnx.com/sf/go/post102187 Di Jin 2013-06-12T05:24:16Z http://community.qnx.com/sf/go/post102174 Hi Hugh, Ok, everything work's well. I update the boot image to start the pci-bios service with the -B option. I can use the original pci-bios provide with qnx 6.5.0 SP1. I modified my code to add the pci_attach_device function but i don't touch anything else. I still interest to know why when i use the pci -v command the address of the bars are still incorrect until a start the pci_att command you send to me. I will expect the address will be correct after we start our application. It is possible to know exactly what the pci_att done ? Thank you for your help, Sylvain Tue, 11 Jun 2013 19:24:55 GMT http://community.qnx.com/sf/go/post102174 Sylvain Comtois 2013-06-11T19:24:55Z http://community.qnx.com/sf/go/post102169 Yes, you are not performing a pci_attach_device() function call. This call sets up all the registers and enables the device. That is what my pci_att program does. After your pci_find_device() function call, add the pci_attach_device() function call and that will return all the base address registers for you in the structure. On 2013-06-11 1:44 PM, "Sylvain Comtois" <community-noreply@qnx.com> wrote: >Hi, > > I had effectively two pci-bios service running. > > To be sure my boot image use the pci-bios service you provide, i >rename it to pci-bios-qnx. I suppose that the diskboot utility start a >second pci-bios service. > > To be sure i made my boot image correctly, after i add the lines you >specified, i change the line pci-bios to \home\user\pci-bios in the >[data=copy] section of the build file. > > So now, i have more information return by the pci_att and the >sloginfo. Also, if i call the pci -vvv utility after i called the >pci_att, the I/O and Mem Space are now enable. > > I place all the outputs in attachment. > > Also my program is now working after the call of the pci_att utility. > > Do i miss something in my pci initialisation ? Here what i'm doing. > >------------------------ > >int PCIDevice::Open (int ProductId, int VendorId, int Order, unsigned int >MemorySize) >{ > > unsigned NbBus = 0; > unsigned Version = 0; > unsigned Hardware = 0; > unsigned BusNum = 0; > unsigned DevFuncNum = 0; > > unsigned Address = 0; > > unsigned int LocalSpaceSize; > > int Handle = pci_attach(0); > > LocalSpaceSize = MemorySize; > > /* Detection du BIOS PCI. */ > > if(pci_present(&NbBus, &Version, &Hardware) != PCI_SUCCESS) > return(PCI_BIOS_NOT_FOUND); > > > /* Detection de la carte PCI de GreenSpring. */ > > if(pci_find_device(ProductId, VendorId, Order, &BusNum, &DevFuncNum) >!= PCI_SUCCESS) > return(PCI_BOARD_NOT_FOUND); > > > /* Detection de la ligne d'interruption. */ > > if(pci_read_config8(BusNum, > DevFuncNum, > offsetof(struct _pci_config_regs , >Interrupt_Line), > 1, > (char *) &Irq) != PCI_SUCCESS) > return(PCI_READ_CONFIG_ERROR); > > > /* Lecture de l'adresse du local space. */ > > if(pci_read_config32(BusNum, > DevFuncNum, > offsetof(struct _pci_config_regs , >Base_Address_Regs) + 8, /*[2]*/ > 1, > (char *) &Address) != PCI_SUCCESS) > return(PCI_READ_CONFIG_ERROR); > > > LocalSpace = Address; > > > if(!PCI_IS_MEM(Address)) > return(PCI_NOT_IN_MEM); > > > /* Lecture de l'adresse des registres du PLX. */ > > if(pci_read_config32(BusNum, > DevFuncNum, > offsetof(struct _pci_config_regs , >Base_Address_Regs), /* [0] */ > 1, > (char *) &Address) != PCI_SUCCESS) > return(PCI_READ_CONFIG_ERROR); > > > RegisterSpace = Address; > > if(!PCI_IS_MEM(Address)) > return(PCI_NOT_IN_MEM); > > > /* Creation d'un pointeur utilisable par le programme pour le local >space. */ > > LocalSpacePtr = (unsigned char *) mmap_device_memory(0, > LocalSpaceSize, //SC il faut >peut être ajouter l'espace retiré par le masque 0xFFFFF000 > PROT_READ | PROT_WRITE, > MAP_SHARED, > LocalSpace & 0xFFFFF000); > > RealLocalSpacePtr = LocalSpacePtr + (LocalSpace & 0x00000FFF); > > > /* Creation d'un pointeur utilisable par le programme pour les >registres. */ > > RegisterSpacePtr = (unsigned char *) mmap_device_memory(0, > RegisterSpaceSize, //SC il >faut peut être ajouter l'espace retiré par le masque 0xFFFFF000 > PROT_READ | PROT_WRITE, > MAP_SHARED, > RegisterSpace & 0xFFFFF000); > > if((int) RegisterSpacePtr == -1) > { > munmap_device_memory(LocalSpacePtr, LocalSpaceSize); > return(PCI_MMAP_ERROR); > } > > RealRegisterSpacePtr = RegisterSpacePtr + (RegisterSpace & 0x00000FFF); > > return PCI_OK; >} > > > >------------------------ > >Thanks, Sylvain > > > > > >_______________________________________________ > >QNX BSPs >http://community.qnx.com/sf/go/post102168 >To cancel your subscription to this discussion, please e-mail >general-bsp-unsubscribe@community.qnx.com Tue, 11 Jun 2013 17:56:35 GMT http://community.qnx.com/sf/go/post102169 Hugh Brown 2013-06-11T17:56:35Z http://community.qnx.com/sf/go/post102168 Hi, I had effectively two pci-bios service running. To be sure my boot image use the pci-bios service you provide, i rename it to pci-bios-qnx. I suppose that the diskboot utility start a second pci-bios service. To be sure i made my boot image correctly, after i add the lines you specified, i change the line pci-bios to \home\user\pci-bios in the [data=copy] section of the build file. So now, i have more information return by the pci_att and the sloginfo. Also, if i call the pci -vvv utility after i called the pci_att, the I/O and Mem Space are now enable. I place all the outputs in attachment. Also my program is now working after the call of the pci_att utility. Do i miss something in my pci initialisation ? Here what i'm doing. ------------------------ int PCIDevice::Open (int ProductId, int VendorId, int Order, unsigned int MemorySize) { unsigned NbBus = 0; unsigned Version = 0; unsigned Hardware = 0; unsigned BusNum = 0; unsigned DevFuncNum = 0; unsigned Address = 0; unsigned int LocalSpaceSize; int Handle = pci_attach(0); LocalSpaceSize = MemorySize; /* Detection du BIOS PCI. */ if(pci_present(&NbBus, &Version, &Hardware) != PCI_SUCCESS) return(PCI_BIOS_NOT_FOUND); /* Detection de la carte PCI de GreenSpring. */ if(pci_find_device(ProductId, VendorId, Order, &BusNum, &DevFuncNum) != PCI_SUCCESS) return(PCI_BOARD_NOT_FOUND); /* Detection de la ligne d'interruption. */ if(pci_read_config8(BusNum, DevFuncNum, offsetof(struct _pci_config_regs , Interrupt_Line), 1, (char *) &Irq) != PCI_SUCCESS) return(PCI_READ_CONFIG_ERROR); /* Lecture de l'adresse du local space. */ if(pci_read_config32(BusNum, DevFuncNum, offsetof(struct _pci_config_regs , Base_Address_Regs) + 8, /*[2]*/ 1, (char *) &Address) != PCI_SUCCESS) return(PCI_READ_CONFIG_ERROR); LocalSpace = Address; if(!PCI_IS_MEM(Address)) return(PCI_NOT_IN_MEM); /* Lecture de l'adresse des registres du PLX. */ if(pci_read_config32(BusNum, DevFuncNum, offsetof(struct _pci_config_regs , Base_Address_Regs), /* [0] */ 1, (char *) &Address) != PCI_SUCCESS) return(PCI_READ_CONFIG_ERROR); RegisterSpace = Address; if(!PCI_IS_MEM(Address)) return(PCI_NOT_IN_MEM); /* Creation d'un pointeur utilisable par le programme pour le local space. */ LocalSpacePtr = (unsigned char *) mmap_device_memory(0, LocalSpaceSize, //SC il faut peut être ajouter l'espace retiré par le masque 0xFFFFF000 PROT_READ | PROT_WRITE, MAP_SHARED, LocalSpace & 0xFFFFF000); RealLocalSpacePtr = LocalSpacePtr + (LocalSpace & 0x00000FFF); /* Creation d'un pointeur utilisable par le programme pour les registres. */ RegisterSpacePtr = (unsigned char *) mmap_device_memory(0, RegisterSpaceSize, //SC il faut peut être ajouter l'espace retiré par le masque 0xFFFFF000 PROT_READ | PROT_WRITE, MAP_SHARED, RegisterSpace & 0xFFFFF000); if((int) RegisterSpacePtr == -1) { munmap_device_memory(LocalSpacePtr, LocalSpaceSize); return(PCI_MMAP_ERROR); } RealRegisterSpacePtr = RegisterSpacePtr + (RegisterSpace & 0x00000FFF); return PCI_OK; } ------------------------ Thanks, Sylvain Tue, 11 Jun 2013 17:44:38 GMT http://community.qnx.com/sf/go/post102168 Sylvain Comtois 2013-06-11T17:44:38Z http://community.qnx.com/sf/go/post102166 Does pidin show only one pci-bios running? On 2013-06-11 12:46 PM, "Sylvain Comtois" <community-noreply@qnx.com> wrote: >Hi, > > The sloginfo is empty. > >--------------------------------------------------- ># sloginfo -c >Time Sev Major Minor Args ># ./pci_att 0x10b5 0x1024 >Info size 240 > >Attach Vendor 0x10b5 - Device 0x1024 - Index 0 >Irq 0xff >Revision 0x1 >Subsystem Vendor 0x0 - Device 0x0 ># sloginfo >Time Sev Major Minor Args ># >------------------------------------------------------------ > >Sylvain > > > >_______________________________________________ > >QNX BSPs >http://community.qnx.com/sf/go/post102163 >To cancel your subscription to this discussion, please e-mail >general-bsp-unsubscribe@community.qnx.com Tue, 11 Jun 2013 16:49:58 GMT http://community.qnx.com/sf/go/post102166 Hugh Brown 2013-06-11T16:49:58Z http://community.qnx.com/sf/go/post102165 I've notified Freescale (the developer of this BSP), and we should have an updated version posted shortly. Regards, ------------------------------------- Dave Green QNX Software Systems Limited dgreen@qnx.com On 13-06-11 11:22 AM, "Ryan Mansfield" <community-noreply@qnx.com> wrote: >On 13-06-11 11:18 AM, Christoph Nemmaier wrote: >> Hi, >> >> Using QNX 6.5.0SP1 toolchain on Windows, compilation of >>src/hardware/ipl/boards/p1010rdb/board.c fails with >> >> Assembler messages: >> Error: unknown pseudo-op: `.cpu' >> Error: Unrecognized opcode: `tlbwe' >> >> To compile the BSP, find the assembler called ntoppc-as.exe in >>host\win32\x86\usr\bin. Along with it, there is ntoppc-as-2.22.exe, and, >>from the original 6.5.0 installation, ntoppc-as-2.19.exe. >> Replace ntoppc-as.exe by the 2.19 version, and the BSP will compile. >>(Thanks to Sandra Taylor for pointing this out). > >The ppc .cpu directive was a QNX extension but it was long deprecated (~ >6.4.x era), and was finally removed in binutils 2.22. The source should >have been updated to use .march. > >Regards, > >Ryan Mansfield > > > > > >_______________________________________________ > >QNX BSPs >http://community.qnx.com/sf/go/post102157 >To cancel your subscription to this discussion, please e-mail >general-bsp-unsubscribe@community.qnx.com Tue, 11 Jun 2013 16:48:54 GMT http://community.qnx.com/sf/go/post102165 David Green 2013-06-11T16:48:54Z http://community.qnx.com/sf/go/post102163 Hi, The sloginfo is empty. --------------------------------------------------- # sloginfo -c Time Sev Major Minor Args # ./pci_att 0x10b5 0x1024 Info size 240 Attach Vendor 0x10b5 - Device 0x1024 - Index 0 Irq 0xff Revision 0x1 Subsystem Vendor 0x0 - Device 0x0 # sloginfo Time Sev Major Minor Args # ------------------------------------------------------------ Sylvain Tue, 11 Jun 2013 16:46:55 GMT http://community.qnx.com/sf/go/post102163 Sylvain Comtois 2013-06-11T16:46:55Z http://community.qnx.com/sf/go/post102162 That is really weird, as the PCI server should output a message such as "PCI_attach_device: vendor 0x10b5 - device 0x1024", but there is no such message in the sloginfo output. I have just run the same program on my PC and that is the output that I get in sloginfo. Can you run 'sloginfo -c' and then run the pci_att program again and see what is in sloginfo? Thanks, Hugh. On 2013-06-11 11:36 AM, "Sylvain Comtois" <community-noreply@qnx.com> wrote: >Hi, > > Humm, it's what i had done. > > 1) Reboot the system with the boot image i made with the pci-bios >you provide. > 2) lauche the pci_att 0x10b5 0x1024 > 3) launch the sloginfo > > I do it again and place the result in attachment. > >Thank, Sylvain > > > >_______________________________________________ > >QNX BSPs >http://community.qnx.com/sf/go/post102160 >To cancel your subscription to this discussion, please e-mail >general-bsp-unsubscribe@community.qnx.com Tue, 11 Jun 2013 15:52:59 GMT http://community.qnx.com/sf/go/post102162 Hugh Brown 2013-06-11T15:52:59Z http://community.qnx.com/sf/go/post102160 Hi, Humm, it's what i had done. 1) Reboot the system with the boot image i made with the pci-bios you provide. 2) lauche the pci_att 0x10b5 0x1024 3) launch the sloginfo I do it again and place the result in attachment. Thank, Sylvain Tue, 11 Jun 2013 15:36:49 GMT http://community.qnx.com/sf/go/post102160 Sylvain Comtois 2013-06-11T15:36:49Z http://community.qnx.com/sf/go/post102158 Please can you run the sloginfo after running the pci_att and send me the sloginfo output? I should have mentioned that. Thanks, Hugh. On 2013-06-11 11:21 AM, "Sylvain Comtois" <community-noreply@qnx.com> wrote: >Hi, > > Here the pci_att and sloginfo output. > >Sylvain > > > > > >_______________________________________________ > >QNX BSPs >http://community.qnx.com/sf/go/post102156 >To cancel your subscription to this discussion, please e-mail >general-bsp-unsubscribe@community.qnx.com Tue, 11 Jun 2013 15:25:50 GMT http://community.qnx.com/sf/go/post102158 Hugh Brown 2013-06-11T15:25:50Z http://community.qnx.com/sf/go/post102157 On 13-06-11 11:18 AM, Christoph Nemmaier wrote: > Hi, > > Using QNX 6.5.0SP1 toolchain on Windows, compilation of src/hardware/ipl/boards/p1010rdb/board.c fails with > > Assembler messages: > Error: unknown pseudo-op: `.cpu' > Error: Unrecognized opcode: `tlbwe' > > To compile the BSP, find the assembler called ntoppc-as.exe in host\win32\x86\usr\bin. Along with it, there is ntoppc-as-2.22.exe, and, from the original 6.5.0 installation, ntoppc-as-2.19.exe. > Replace ntoppc-as.exe by the 2.19 version, and the BSP will compile. (Thanks to Sandra Taylor for pointing this out). The ppc .cpu directive was a QNX extension but it was long deprecated (~ 6.4.x era), and was finally removed in binutils 2.22. The source should have been updated to use .march. Regards, Ryan Mansfield Tue, 11 Jun 2013 15:22:14 GMT http://community.qnx.com/sf/go/post102157 Ryan Mansfield 2013-06-11T15:22:14Z http://community.qnx.com/sf/go/post102156 Hi, Here the pci_att and sloginfo output. Sylvain Tue, 11 Jun 2013 15:21:50 GMT http://community.qnx.com/sf/go/post102156 Sylvain Comtois 2013-06-11T15:21:50Z http://community.qnx.com/sf/go/post102155 Hi, Using QNX 6.5.0SP1 toolchain on Windows, compilation of src/hardware/ipl/boards/p1010rdb/board.c fails with Assembler messages: Error: unknown pseudo-op: `.cpu' Error: Unrecognized opcode: `tlbwe' To compile the BSP, find the assembler called ntoppc-as.exe in host\win32\x86\usr\bin. Along with it, there is ntoppc-as-2.22.exe, and, from the original 6.5.0 installation, ntoppc-as-2.19.exe. Replace ntoppc-as.exe by the 2.19 version, and the BSP will compile. (Thanks to Sandra Taylor for pointing this out). Christoph Tue, 11 Jun 2013 15:18:04 GMT http://community.qnx.com/sf/go/post102155 Christoph Nemmaier 2013-06-11T15:18:04Z http://community.qnx.com/sf/go/post102154 Thank you for that output. It appears that the BIOS is leaving this device disabled for some reason, so the PCI server leaves it that way until a pci_attach_device() function is issued. Please will you boot your system with the pci-bios that I sent you, then run the attached program as 'pci_att 0x10b5 0x1024' and send me the output from the program as well as the sloginfo output again. Thanks, Hugh. On 2013-06-11 10:51 AM, "Sylvain Comtois" <community-noreply@qnx.com> wrote: >Hi, > > This is the new sloginfo and pci -v output with the pci-bios service >you provide. > >Sylvain > > > >_______________________________________________ > >QNX BSPs >http://community.qnx.com/sf/go/post102152 >To cancel your subscription to this discussion, please e-mail >general-bsp-unsubscribe@community.qnx.com Tue, 11 Jun 2013 15:01:55 GMT http://community.qnx.com/sf/go/post102154 Hugh Brown 2013-06-11T15:01:55Z http://community.qnx.com/sf/go/post102152 Hi, This is the new sloginfo and pci -v output with the pci-bios service you provide. Sylvain Tue, 11 Jun 2013 14:51:51 GMT http://community.qnx.com/sf/go/post102152 Sylvain Comtois 2013-06-11T14:51:51Z http://community.qnx.com/sf/go/post102149 I think that 'devb-eide cam quiet' should work. On 2013-06-07 10:36 PM, "Allen Chen" <community-noreply@qnx.com> wrote: >Thank you. >Now it can speed up by 10s. But my pci driver pci_szk cannot be started. >It is ok after pci_szk was moved to /etc/rc.d/rc.local. >How to prevent devb-eide printing output message? > >于 2013/6/7 19:24, Hugh Brown 写道: >> After the procmgr_symlink line in the build file, add the following: >> >> seedres >> slogger -s128k >> pci-bios -B >> waitfor /dev/pci >> pci_szk >> waitfor /dev/szk >> devb-eide >> waitfor /dev/hd0 >> >> >> >> >> On 2013-06-06 11:27 PM, "Allen Chen" <community-noreply@qnx.com> wrote: >> >>> Hi, I have a moxa da-683 embedded computer. Neutrino 6.5.0 is >>> successfully installed on it via qnxsdp-6.5.0-201007091524-nto.iso. >>> Because it spends too much time at the steps of AHCI, EIDE and USB >>> scanning. I need to modify the build file and build custom OS image. >>> >>> Now I makes a copy of qnxbasesmp-apic.build from /boot/build, and >>>comment >>> lines for devb-ahci, devb-mvSata, umass-enum and etc. I want to start >>> such processes: >>> pci-bios -B >>> waitfor /dev/pci >>> pci_szk >>> waitfor /dev/szk >>> >>> But I don't know where these lines should be added. I try add a block >>> like this: >>> [+script] .script = { >>> pci-bios -B & >>> waitfor /dev/pci >>> pci_szk & >>> waitfor /dev/szk >>> } >>> However, after started, I found that there are two prcocesses of >>>pci_bios >>> running. Is process pci-bios (PID=4099) started by diskboot? Are there >>> any method to modify diskboot script? >>> >>> Next question, AHCI and USB scanning are skipped by commenting >>> devb-ahci, devb-mvSata, umass-enum lines in the build file, is this >>>metod >>> appropriate? >>> >>> Allen Chen >>> >>> >>> >>> _______________________________________________ >>> >>> QNX BSPs >>> http://community.qnx.com/sf/go/post102075 >>> To cancel your subscription to this discussion, please e-mail >>> general-bsp-unsubscribe@community.qnx.com >> >> >> >> >> _______________________________________________ >> >> QNX BSPs >> http://community.qnx.com/sf/go/post102081 >> To cancel your subscription to this discussion, please e-mail >>general-bsp-unsubscribe@community.qnx.com >> > > > > > >_______________________________________________ > >QNX BSPs >http://community.qnx.com/sf/go/post102102 >To cancel your subscription to this discussion, please e-mail >general-bsp-unsubscribe@community.qnx.com Tue, 11 Jun 2013 13:49:42 GMT http://community.qnx.com/sf/go/post102149 Hugh Brown 2013-06-11T13:49:42Z http://community.qnx.com/sf/go/post102147 Please can you rebuild your boot image with the attached pci-bios and the extra lines added to your build file, reboot the system and send me the sloginfo output again? Thanks, Hugh. On 2013-06-11 8:06 AM, "Sylvain Comtois" <community-noreply@qnx.com> wrote: >QNX Installations > > Installation Name: QNX Software Development Platform 6.5.0 > Version: 6.5.0 x86-only > Base Directory: /usr/qnx650/ > QNX_HOST: /usr/qnx650/host/qnx6/x86/ > QNX_TARGET: /usr/qnx650/target/qnx6/ > >Additional Packages > > Package Name: QNX Software Development Platform > Version: 6.5.0SP1 > Base: QNX SDP 6.5.0 > Installation Path: /usr/qnx650 > >Sylvain > > > >_______________________________________________ > >QNX BSPs >http://community.qnx.com/sf/go/post102146 >To cancel your subscription to this discussion, please e-mail >general-bsp-unsubscribe@community.qnx.com Tue, 11 Jun 2013 12:46:25 GMT http://community.qnx.com/sf/go/post102147 Hugh Brown 2013-06-11T12:46:25Z http://community.qnx.com/sf/go/post102146 QNX Installations Installation Name: QNX Software Development Platform 6.5.0 Version: 6.5.0 x86-only Base Directory: /usr/qnx650/ QNX_HOST: /usr/qnx650/host/qnx6/x86/ QNX_TARGET: /usr/qnx650/target/qnx6/ Additional Packages Package Name: QNX Software Development Platform Version: 6.5.0SP1 Base: QNX SDP 6.5.0 Installation Path: /usr/qnx650 Sylvain Tue, 11 Jun 2013 12:06:01 GMT http://community.qnx.com/sf/go/post102146 Sylvain Comtois 2013-06-11T12:06:01Z http://community.qnx.com/sf/go/post102145 What version of the O/S are you running? This problem was fixed some time ago. On 2013-06-10 1:49 PM, "Sylvain Comtois" <community-noreply@qnx.com> wrote: >Hi, > > I place the sloginfo log and the pci -v log in the file in attachment. > >Thank, Sylvain > > > >_______________________________________________ > >QNX BSPs >http://community.qnx.com/sf/go/post102127 >To cancel your subscription to this discussion, please e-mail >general-bsp-unsubscribe@community.qnx.com Tue, 11 Jun 2013 11:59:32 GMT http://community.qnx.com/sf/go/post102145 Hugh Brown 2013-06-11T11:59:32Z http://community.qnx.com/sf/go/post102143 Dear Sir, Now we use Fujitsu Jade MB86R03, and our TFT-display is 240 x 400. Does BSP support this resolution? We set the parameter in jade.conf, but the io-display is error. Our setting is mode:htp=262,hsp=250,hsw=1,hdp=240,vtr=528,vsp=403,vsw=1,vdp=400,dcm=0x5300,refresh=60 We are followed the TFT-display document. Thanks. Tue, 11 Jun 2013 11:24:19 GMT http://community.qnx.com/sf/go/post102143 Di Jin 2013-06-11T11:24:19Z http://community.qnx.com/sf/go/post102127 Hi, I place the sloginfo log and the pci -v log in the file in attachment. Thank, Sylvain Mon, 10 Jun 2013 17:49:35 GMT http://community.qnx.com/sf/go/post102127 Sylvain Comtois 2013-06-10T17:49:35Z http://community.qnx.com/sf/go/post102102 Thank you. Now it can speed up by 10s. But my pci driver pci_szk cannot be started. It is ok after pci_szk was moved to /etc/rc.d/rc.local. How to prevent devb-eide printing output message? 于 2013/6/7 19:24, Hugh Brown 写道: > After the procmgr_symlink line in the build file, add the following: > > seedres > slogger -s128k > pci-bios -B > waitfor /dev/pci > pci_szk > waitfor /dev/szk > devb-eide > waitfor /dev/hd0 > > > > > On 2013-06-06 11:27 PM, "Allen Chen" <community-noreply@qnx.com> wrote: > >> Hi, I have a moxa da-683 embedded computer. Neutrino 6.5.0 is >> successfully installed on it via qnxsdp-6.5.0-201007091524-nto.iso. >> Because it spends too much time at the steps of AHCI, EIDE and USB >> scanning. I need to modify the build file and build custom OS image. >> >> Now I makes a copy of qnxbasesmp-apic.build from /boot/build, and comment >> lines for devb-ahci, devb-mvSata, umass-enum and etc. I want to start >> such processes: >> pci-bios -B >> waitfor /dev/pci >> pci_szk >> waitfor /dev/szk >> >> But I don't know where these lines should be added. I try add a block >> like this: >> [+script] .script = { >> pci-bios -B & >> waitfor /dev/pci >> pci_szk & >> waitfor /dev/szk >> } >> However, after started, I found that there are two prcocesses of pci_bios >> running. Is process pci-bios (PID=4099) started by diskboot? Are there >> any method to modify diskboot script? >> >> Next question, AHCI and USB scanning are skipped by commenting >> devb-ahci, devb-mvSata, umass-enum lines in the build file, is this metod >> appropriate? >> >> Allen Chen >> >> >> >> _______________________________________________ >> >> QNX BSPs >> http://community.qnx.com/sf/go/post102075 >> To cancel your subscription to this discussion, please e-mail >> general-bsp-unsubscribe@community.qnx.com > > > > > _______________________________________________ > > QNX BSPs > http://community.qnx.com/sf/go/post102081 > To cancel your subscription to this discussion, please e-mail general-bsp-unsubscribe@community.qnx.com > Sat, 08 Jun 2013 02:36:44 GMT http://community.qnx.com/sf/go/post102102 Allen Chen 2013-06-08T02:36:44Z http://community.qnx.com/sf/go/post102096 Hi All, There is a new Xilinx Zynq702 QNX BSP Available. We are working to get the latest BSP posted to Foundary27. Until it is the BSP is posted one could can get access to the BSP by contacting the Adeneo Embedded Support Team at: support@Adeneo-Embedded.com Features Supported: Multi-Core: SMP and BMP QConn Serial Ethernet NOR Flash memory over QSPI SD Card CAN GPIO SPI I2C XADC FPGA OCM : Dynamic confguration DMA USB : Host and Device Issues resolved: In Release v0.0.5 The MAC Address is hard coded. Some Ethernet cards will not work with the current driver. This may prevent users from downloading an image from a TFTP server. Ethernet performance is slow when trans-ferring data from the board. In some cases, the board does not manageto switch between connections of different speeds. When booting from a SD Card, the SPI Driver outputs the following message nanospin calibrate failed: Bad file descrip-tor We can't erase the QSPI NOR flash from QNX In Release v0.1.0 System profling is not working properly In Release v0.2.0 USB sync may fail after a big data transfer (USB device mode). TFTP in IPL may hanged up Regards, Adeneo Embedded Support Team Fri, 07 Jun 2013 19:20:06 GMT http://community.qnx.com/sf/go/post102096 Tim Parks 2013-06-07T19:20:06Z http://community.qnx.com/sf/go/post102081 After the procmgr_symlink line in the build file, add the following: seedres slogger -s128k pci-bios -B waitfor /dev/pci pci_szk waitfor /dev/szk devb-eide waitfor /dev/hd0 On 2013-06-06 11:27 PM, "Allen Chen" <community-noreply@qnx.com> wrote: >Hi, I have a moxa da-683 embedded computer. Neutrino 6.5.0 is >successfully installed on it via qnxsdp-6.5.0-201007091524-nto.iso. >Because it spends too much time at the steps of AHCI, EIDE and USB >scanning. I need to modify the build file and build custom OS image. > >Now I makes a copy of qnxbasesmp-apic.build from /boot/build, and comment >lines for devb-ahci, devb-mvSata, umass-enum and etc. I want to start >such processes: > pci-bios -B > waitfor /dev/pci > pci_szk > waitfor /dev/szk > >But I don't know where these lines should be added. I try add a block >like this: >[+script] .script = { > pci-bios -B & > waitfor /dev/pci > pci_szk & > waitfor /dev/szk >} >However, after started, I found that there are two prcocesses of pci_bios >running. Is process pci-bios (PID=4099) started by diskboot? Are there >any method to modify diskboot script? > >Next question, AHCI and USB scanning are skipped by commenting >devb-ahci, devb-mvSata, umass-enum lines in the build file, is this metod >appropriate? > >Allen Chen > > > >_______________________________________________ > >QNX BSPs >http://community.qnx.com/sf/go/post102075 >To cancel your subscription to this discussion, please e-mail >general-bsp-unsubscribe@community.qnx.com Fri, 07 Jun 2013 11:24:52 GMT http://community.qnx.com/sf/go/post102081 Hugh Brown 2013-06-07T11:24:52Z http://community.qnx.com/sf/go/post102076 Hi, I'm working on Renasas board with - Quad core - ARM cortex A9 - NOR Flash S29GL01 (128MB) - Installed Neutrino 6.5.0 SP1. When I run system in one core (CPU0). I mounting devf-genneric is successful I can erase/write flash is normal. However, When I enable multiprocessor (smp) for system, i can't mount devf-generic My command is (with flash's address is 0x00000000) #devf-generic -s 0,128m Log error is #(devf f3s_flase_probe:275) Unable to properly identify any flash devices After that I read flash by read direct address and by trace 32. But they are not match. Does here anyone come with my problem before? Fri, 07 Jun 2013 06:26:05 GMT http://community.qnx.com/sf/go/post102076 Mr Sun 2013-06-07T06:26:05Z http://community.qnx.com/sf/go/post102075 Hi, I have a moxa da-683 embedded computer. Neutrino 6.5.0 is successfully installed on it via qnxsdp-6.5.0-201007091524-nto.iso. Because it spends too much time at the steps of AHCI, EIDE and USB scanning. I need to modify the build file and build custom OS image. Now I makes a copy of qnxbasesmp-apic.build from /boot/build, and comment lines for devb-ahci, devb-mvSata, umass-enum and etc. I want to start such processes: pci-bios -B waitfor /dev/pci pci_szk waitfor /dev/szk But I don't know where these lines should be added. I try add a block like this: [+script] .script = { pci-bios -B & waitfor /dev/pci pci_szk & waitfor /dev/szk } However, after started, I found that there are two prcocesses of pci_bios running. Is process pci-bios (PID=4099) started by diskboot? Are there any method to modify diskboot script? Next question, AHCI and USB scanning are skipped by commenting devb-ahci, devb-mvSata, umass-enum lines in the build file, is this metod appropriate? Allen Chen Fri, 07 Jun 2013 03:27:29 GMT http://community.qnx.com/sf/go/post102075 Allen Chen 2013-06-07T03:27:29Z http://community.qnx.com/sf/go/post102048 OK, so please modify your build file as follows and create a new boot image: After the procmgr_symlink line in the build file, add the following: seedres slogger -s1024k pci-bios -b15 -B -vvv waitfor /dev/pci Rebuild your boot image with this build file and reboot the system. Once the system is booted, please send me the full sloginfo output as well as the 'pci -v' output. Thanks, Hugh. On 2013-06-06 9:31 AM, "Sylvain Comtois" <community-noreply@qnx.com> wrote: >Hi Hugh, > > I disable some PCI devices in the BIOS so the bus number is now 7. I >also start the pci-bios service with the -b 15 and -B option and the Bars >of the acromag PCi carrier are still disabled. > >Thank you, Sylvain > > > >_______________________________________________ > >QNX BSPs >http://community.qnx.com/sf/go/post102046 >To cancel your subscription to this discussion, please e-mail >general-bsp-unsubscribe@community.qnx.com Thu, 06 Jun 2013 13:59:10 GMT http://community.qnx.com/sf/go/post102048 Hugh Brown 2013-06-06T13:59:10Z http://community.qnx.com/sf/go/post102047 You might want to take a look at the docs regarding mkifs and build files: http://www.qnx.com/developers/docs/6.4.1/neutrino/utilities/m/mkifs.html#XIPvsCopy Sounds like you have the first case (uip, uip -- run once). Thu, 06 Jun 2013 13:46:30 GMT http://community.qnx.com/sf/go/post102047 Gervais Mulongoy 2013-06-06T13:46:30Z http://community.qnx.com/sf/go/post102046 Hi Hugh, I disable some PCI devices in the BIOS so the bus number is now 7. I also start the pci-bios service with the -b 15 and -B option and the Bars of the acromag PCi carrier are still disabled. Thank you, Sylvain Thu, 06 Jun 2013 13:31:01 GMT http://community.qnx.com/sf/go/post102046 Sylvain Comtois 2013-06-06T13:31:01Z http://community.qnx.com/sf/go/post102044 Try starting the PCI server as 'pci-bios -b15 -B' and see if that works. The PCI server by default only scans 10 buses and your device is on bus 11. On 2013-06-05 1:32 PM, "Sylvain Comtois" <community-noreply@qnx.com> wrote: >Hi, > > I place in attachment the output of the pci utility with the four >following case. > >Working computer without the -B option in the pci-bios service. >Working computer with the -B option in the pci-bios service. >Non-working computer without the -B option in the pci-bios service. >Non-working computer with the -B option in the pci-bios service. > > I just notice that the PCI version of the motherboard (according to >the pci utility) for the non-working computer is 3.0 and 2.1 for the >working computer. The PCI version of the acromag pci board is 2.2. > >Thank you, Sylvain > > > >_______________________________________________ > >QNX BSPs >http://community.qnx.com/sf/go/post102032 >To cancel your subscription to this discussion, please e-mail >general-bsp-unsubscribe@community.qnx.com Thu, 06 Jun 2013 13:09:42 GMT http://community.qnx.com/sf/go/post102044 Hugh Brown 2013-06-06T13:09:42Z http://community.qnx.com/sf/go/post102034 My current bsp starts up devb-umass fine and I can plug and play usb devices perfectly. I have a script which formats usb devices and within the script it slays and restarts devb-umass a few times. This script runs fine under a different bsp but not under the photon bsp I am currently using. When I run it on this bsp I get this error. ldd:FATAL:Unresolved sumbol "usbd_chain_io" called from executable Like I said the devb-umass runs fine..the problem occurs when slaying it and attempting to restart it. Wed, 05 Jun 2013 18:56:36 GMT http://community.qnx.com/sf/go/post102034 Steve Cirner 2013-06-05T18:56:36Z http://community.qnx.com/sf/go/post102032 Hi, I place in attachment the output of the pci utility with the four following case. Working computer without the -B option in the pci-bios service. Working computer with the -B option in the pci-bios service. Non-working computer without the -B option in the pci-bios service. Non-working computer with the -B option in the pci-bios service. I just notice that the PCI version of the motherboard (according to the pci utility) for the non-working computer is 3.0 and 2.1 for the working computer. The PCI version of the acromag pci board is 2.2. Thank you, Sylvain Wed, 05 Jun 2013 17:32:46 GMT http://community.qnx.com/sf/go/post102032 Sylvain Comtois 2013-06-05T17:32:46Z http://community.qnx.com/sf/go/post101984 Please can you post the full 'pci -v' listing from your new machine as well as your old machine. On 2013-06-03 8:14 AM, "Sylvain Comtois" <community-noreply@qnx.com> wrote: >There is no Plug & Play option in the BIOS and we always try with the -B >option. > > > >_______________________________________________ > >QNX BSPs >http://community.qnx.com/sf/go/post101975 >To cancel your subscription to this discussion, please e-mail >general-bsp-unsubscribe@community.qnx.com Mon, 03 Jun 2013 14:27:08 GMT http://community.qnx.com/sf/go/post101984 Hugh Brown 2013-06-03T14:27:08Z http://community.qnx.com/sf/go/post101975 There is no Plug & Play option in the BIOS and we always try with the -B option. Mon, 03 Jun 2013 12:14:56 GMT http://community.qnx.com/sf/go/post101975 Sylvain Comtois 2013-06-03T12:14:56Z http://community.qnx.com/sf/go/post101972 Hello, I've been trying to configure GPIO Pin(6,14) -> SWMUX_NANDF_CS1 ( #defined to 167 in mx6x_iomux.h ) as input source for interrupts. #define TEST_PAD_CFG (PAD_CTL_PUE_PULL | PAD_CTL_PUS_100K_PD | \ PAD_CTL_SPEED_MEDIUM | PAD_CTL_DSE_40_OHM | \ PAD_CTL_HYS_ENABLE) pinmux_set_swmux(SWMUX_NANDF_CS1, MUX_CTL_MUX_MODE_ALT5); pinmux_set_padcfg(SWMUX_NANDF_CS1, TEST_PAD_CFG); gpio_select_input( 6, 14 ); gpio_set_irq_mode( 6, 14, GPIO_IRQ_EDGE_FALL ); 1) How does 6,14 map to 167? According to conversion formula it must be ( 6 - 1 ) * 32 + 14 = 164!! 2) How do i connnect the ISR routine and what ISR number would be generated for 6,14? 3) Does QNX provide some API similar to gpio_set_value in linux for toggling pins? I do see the following code in my init_intinfo.c file. Currently this does not make a lot of sense to me especially the call out functions. Any help in this regard will be appreciated. const static struct startup_intrinfo gpio6intrs[] = { /* GPIO 6 interrupt */ { 1000+(32*5), // vector base 32, // number of vectors OMAP44XX_GPIO6_MPU_IRQ, // cascade vector 0, // CPU vector base 0, // CPU vector stride 0, // flags { 0, 0, &interrupt_id_omap4_gpio }, { INTR_GENFLAG_LOAD_INTRMASK, 0, &interrupt_eoi_omap4_gpio }, &interrupt_mask_omap4_gpio, // mask callout &interrupt_unmask_omap4_gpio, // unmask callout 0, // config callout &omap4430_gpio6_base, } }; Mon, 03 Jun 2013 04:57:54 GMT http://community.qnx.com/sf/go/post101972 seshadri padmanabha 2013-06-03T04:57:54Z http://community.qnx.com/sf/go/post101940 I understand now. Being a newbie, I try to port the driver as learn Neutrino programming. Thanks all of you. I really feel QNX is great as well as this community! 于 2013/5/31 20:40, Mario Charest 写道: > >> -----Message d'origine----- >> De : Allen Chen [mailto:community-noreply@qnx.com] >> Envoyé : 30 mai 2013 21:10 >> À : general-bsp@community.qnx.com >> Objet : Re: PCI continuous access causes QNX reboot or crash >> >> Sorry, the mapped device memory address is 96500000h 0x800 in length. >> >> Here is the pci-bios -vvv output result: >> >> MEM 96500800 80 >> IO 1000 80 >> MEM 96500000 800 >> MEM 96500800 80 - Flags 82 >> MEM 96500000 800 - Flags 82 >> >> I use the following codes to map the device memory 2. >> >> uint32_t iosize = 0x80; >> uint64_t ioport = PCI_IO_ADDR(inf.PciBaseAddress[2]); >> iobase = (uintptr_t)mmap_device_memory(NULL, iosize, PROT_READ | >> PROT_WRITE | PROT_NOCACHE, 0, ioport); >> >> for (i = 0; i < 8; i++) { >> out8((iobase + 1 + i), wbuf[i]); >> } > You have mixed up IO access and memory access. You should you PCI_MEM_ADDR not PCI_IO_ADDR and mmap_device_memory doesn't return an ioport but a pointer. > >> 于 2013/5/31 0:03, Mario Charest 写道: >>>> -----Message d'origine----- >>>> De : Allen Chen [mailto:community-noreply@qnx.com] >>>> Envoyé : 30 mai 2013 12:00 >>>> À : general-bsp >>>> Objet : PCI continuous access causes QNX reboot or crash >>>> >>>> I write a PCI card testing program, which attaches the device, map >>>> device memory, read/write bytes, unmap memory and detach the device, >>>> exits at last. I make about 15 times of continuous executing the >>>> program. Neutrino will crash or automatically reboot. >>> Your program is probably writting in memory area that it should not, or >> your hardware is causing some memory corruption. >>>> One time I snapped the screen. The picture is in attachment. Please >>>> view it and give me some advices to find the reason. >>>> Thank you in advance. >>>> Allen Chen >>>> >>>> >>>> >>>> _______________________________________________ >>>> >>>> QNX BSPs >>>> http://community.qnx.com/sf/go/post101888 >>>> To cancel your subscription to this discussion, please e-mail >>>> general-bsp- unsubscribe@community.qnx.com >>> >>> >>> _______________________________________________ >>> >>> QNX BSPs >>> http://community.qnx.com/sf/go/post101889 >>> To cancel your subscription to this discussion, please e-mail >>> general-bsp-unsubscribe@community.qnx.com >> >> >> >> >> _______________________________________________ >> >> QNX BSPs >> http://community.qnx.com/sf/go/post101912 >> To cancel your subscription to this discussion, please e-mail general-bsp- >> unsubscribe@community.qnx.com > > > > _______________________________________________ > > QNX BSPs > http://community.qnx.com/sf/go/post101929 > To cancel your subscription to this discussion, please e-mail general-bsp-unsubscribe@community.qnx.com Fri, 31 May 2013 13:38:43 GMT http://community.qnx.com/sf/go/post101940 Allen Chen 2013-05-31T13:38:43Z http://community.qnx.com/sf/go/post101929 > -----Message d'origine----- > De : Allen Chen [mailto:community-noreply@qnx.com] > Envoyé : 30 mai 2013 21:10 > À : general-bsp@community.qnx.com > Objet : Re: PCI continuous access causes QNX reboot or crash > > Sorry, the mapped device memory address is 96500000h 0x800 in length. > > Here is the pci-bios -vvv output result: > > MEM 96500800 80 > IO 1000 80 > MEM 96500000 800 > MEM 96500800 80 - Flags 82 > MEM 96500000 800 - Flags 82 > > I use the following codes to map the device memory 2. > > uint32_t iosize = 0x80; > uint64_t ioport = PCI_IO_ADDR(inf.PciBaseAddress[2]); > iobase = (uintptr_t)mmap_device_memory(NULL, iosize, PROT_READ | > PROT_WRITE | PROT_NOCACHE, 0, ioport); > > for (i = 0; i < 8; i++) { > out8((iobase + 1 + i), wbuf[i]); > } You have mixed up IO access and memory access. You should you PCI_MEM_ADDR not PCI_IO_ADDR and mmap_device_memory doesn't return an ioport but a pointer. > > 于 2013/5/31 0:03, Mario Charest 写道: > > > >> -----Message d'origine----- > >> De : Allen Chen [mailto:community-noreply@qnx.com] > >> Envoyé : 30 mai 2013 12:00 > >> À : general-bsp > >> Objet : PCI continuous access causes QNX reboot or crash > >> > >> I write a PCI card testing program, which attaches the device, map > >> device memory, read/write bytes, unmap memory and detach the device, > >> exits at last. I make about 15 times of continuous executing the > >> program. Neutrino will crash or automatically reboot. > > Your program is probably writting in memory area that it should not, or > your hardware is causing some memory corruption. > > > >> One time I snapped the screen. The picture is in attachment. Please > >> view it and give me some advices to find the reason. > >> Thank you in advance. > >> Allen Chen > >> > >> > >> > >> _______________________________________________ > >> > >> QNX BSPs > >> http://community.qnx.com/sf/go/post101888 > >> To cancel your subscription to this discussion, please e-mail > >> general-bsp- unsubscribe@community.qnx.com > > > > > > > > _______________________________________________ > > > > QNX BSPs > > http://community.qnx.com/sf/go/post101889 > > To cancel your subscription to this discussion, please e-mail > > general-bsp-unsubscribe@community.qnx.com > > > > > > _______________________________________________ > > QNX BSPs > http://community.qnx.com/sf/go/post101912 > To cancel your subscription to this discussion, please e-mail general-bsp- > unsubscribe@community.qnx.com Fri, 31 May 2013 12:40:46 GMT http://community.qnx.com/sf/go/post101929 Mario Charest 2013-05-31T12:40:46Z http://community.qnx.com/sf/go/post101927 > -----Message d'origine----- > De : Allen Chen [mailto:community-noreply@qnx.com] > Envoyé : 30 mai 2013 12:16 > À : general-bsp@community.qnx.com > Objet : Re: PCI continuous access causes QNX reboot or crash > > l am testing on x86 platform. The mapped device memory is the same as the > original address, which is 09604100h. That is VERY suspicious. I've never seen a physical address exactly match a virtual address. > Maybe the program has some memory > access error. How can I probe it? > > Thank you for the instant reply! > > > > _______________________________________________ > > QNX BSPs > http://community.qnx.com/sf/go/post101890 > To cancel your subscription to this discussion, please e-mail general-bsp- > unsubscribe@community.qnx.com Fri, 31 May 2013 12:33:11 GMT http://community.qnx.com/sf/go/post101927 Mario Charest 2013-05-31T12:33:11Z http://community.qnx.com/sf/go/post101914 Il 31/05/2013 3.10, Allen Chen ha scritto: > Sorry, the mapped device memory address is 96500000h 0x800 in length. > > Here is the pci-bios -vvv output result: > > MEM 96500800 80 > IO 1000 80 > MEM 96500000 800 > MEM 96500800 80 - Flags 82 > MEM 96500000 800 - Flags 82 > > I use the following codes to map the device memory 2. > > uint32_t iosize = 0x80; > uint64_t ioport = PCI_IO_ADDR(inf.PciBaseAddress[2]); > iobase = (uintptr_t)mmap_device_memory(NULL, iosize, PROT_READ | > PROT_WRITE | PROT_NOCACHE, 0, ioport); Chen, If t is an IO address, You have to use mmap_device_io, not mmap_device_memory. > > for (i = 0; i < 8; i++) { > out8((iobase + 1 + i), wbuf[i]); > } You can't access an IO instruction using an address on a x86 system. You have mixed two different way to access a resource :-) On PLX, the default is CpuBaseAddress[2] Local bus memory space and CpuBaseAddress[3] is the IO. You have to chose one of them according to Your hardware function. If You want to use memory : unsigned char *pMem; pMem=mmap_device_memory(NULL,size, (PROT_...), 0, inf.CpuBaseAddress[2]); for(i=0; i<8; i++) pMem[i+1]= wbuf[i]; If You want to use IO, You must use the BAR[3] space: iobase = mmap_device_io(info.CpuBaseAddressSize[3], PCI_IO_ADDR(inf.CpuBaseAddress[3])); for(i=0; i<8; i++) out8(iocase+i+1,wbuf[i]); M. Sangalli Fri, 31 May 2013 06:21:30 GMT http://community.qnx.com/sf/go/post101914 mario sangalli 2013-05-31T06:21:30Z http://community.qnx.com/sf/go/post101912 Sorry, the mapped device memory address is 96500000h 0x800 in length. Here is the pci-bios -vvv output result: MEM 96500800 80 IO 1000 80 MEM 96500000 800 MEM 96500800 80 - Flags 82 MEM 96500000 800 - Flags 82 I use the following codes to map the device memory 2. uint32_t iosize = 0x80; uint64_t ioport = PCI_IO_ADDR(inf.PciBaseAddress[2]); iobase = (uintptr_t)mmap_device_memory(NULL, iosize, PROT_READ | PROT_WRITE | PROT_NOCACHE, 0, ioport); for (i = 0; i < 8; i++) { out8((iobase + 1 + i), wbuf[i]); } 于 2013/5/31 0:03, Mario Charest 写道: > >> -----Message d'origine----- >> De : Allen Chen [mailto:community-noreply@qnx.com] >> Envoyé : 30 mai 2013 12:00 >> À : general-bsp >> Objet : PCI continuous access causes QNX reboot or crash >> >> I write a PCI card testing program, which attaches the device, map device >> memory, read/write bytes, unmap memory and detach the device, exits at >> last. I make about 15 times of continuous executing the program. Neutrino >> will crash or automatically reboot. > Your program is probably writting in memory area that it should not, or your hardware is causing some memory corruption. > >> One time I snapped the screen. The picture is in attachment. Please view it >> and give me some advices to find the reason. >> Thank you in advance. >> Allen Chen >> >> >> >> _______________________________________________ >> >> QNX BSPs >> http://community.qnx.com/sf/go/post101888 >> To cancel your subscription to this discussion, please e-mail general-bsp- >> unsubscribe@community.qnx.com > > > > _______________________________________________ > > QNX BSPs > http://community.qnx.com/sf/go/post101889 > To cancel your subscription to this discussion, please e-mail general-bsp-unsubscribe@community.qnx.com Fri, 31 May 2013 01:10:41 GMT http://community.qnx.com/sf/go/post101912 Allen Chen 2013-05-31T01:10:41Z http://community.qnx.com/sf/go/post101904 You will have to run the PCI server with the '-B' command line option. Also check to see if Plug 'n Play (PNP) is turned off in the BIOS. On 2013-05-30 2:58 PM, "Sylvain Comtois" <community-noreply@qnx.com> wrote: >Hi, > > I use an acromag pci carrier on QNX neutrino since one year and she >just work fine. We update our motherboard and neutrino to SP1 to have >better performance and the pci card is no longer working. > > We can access the card with the pci_xxx function and the pci utility. >But when we try to reach the memory return by the BARs address space all >values are always read as 0xff. > > When we run the pci utility he said that the I/O space and the memory >space access is disable. We also try with the pci-bios service start with >the -B option and the result is similar. The only difference is the >address of I/O en memory spaces are all 0 in the second case. The address >of the first case are similar to the addresse we obtain before the >migration of the computer and neutrino. Trying to access the address of >the second case (pci-bios -B) made the system to crash very fast. > > There is a snapshot of the pci utility output without the -B option. > >-------------------------------------- >Class = Bridge (Other) >Vendor ID = 10b5h, PLX Technology, Inc. >Device ID = 1024h, Acromag, Inc. IndustryPack Carrier Card >PCI index = 0h >Class Codes = 068000h >Revision ID = 1h >Bus number = 7 >Device number = 1 >Function num = 0 >Status Reg = 280h >Command Reg = 0h > I/O space access disabled > Memory space access disabled > Bus Master disabled > Special Cycle operations ignored > Memory Write and Invalidate disabled > Palette Snooping disabled > Parity Error Response disabled > Data/Address stepping disabled > SERR# driver disabled > Fast back-to-back transactions to different agents disabled > PCI INTx enabled >Header type = 0h Single-function >BIST = 0h Build-in-self-test not supported >Latency Timer = 0h >Cache Line Size= 10h un-cacheable >Subsystem Vendor ID = 10b5h >Subsystem ID = 1024h >Max Lat = 0ns >Min Gnt = 0ns >PCI Int Pin = INT A >Interrupt line = 11 >------------------------ > > Is there a way to enabling the I/O and memory space? > > I search in the BIOS configuration and i don't find any configuration >for the PCI card. > >Thank you, Sylvain > > > >_______________________________________________ > >QNX BSPs >http://community.qnx.com/sf/go/post101903 >To cancel your subscription to this discussion, please e-mail >general-bsp-unsubscribe@community.qnx.com Thu, 30 May 2013 19:16:37 GMT http://community.qnx.com/sf/go/post101904 Hugh Brown 2013-05-30T19:16:37Z http://community.qnx.com/sf/go/post101903 Hi, I use an acromag pci carrier on QNX neutrino since one year and she just work fine. We update our motherboard and neutrino to SP1 to have better performance and the pci card is no longer working. We can access the card with the pci_xxx function and the pci utility. But when we try to reach the memory return by the BARs address space all values are always read as 0xff. When we run the pci utility he said that the I/O space and the memory space access is disable. We also try with the pci-bios service start with the -B option and the result is similar. The only difference is the address of I/O en memory spaces are all 0 in the second case. The address of the first case are similar to the addresse we obtain before the migration of the computer and neutrino. Trying to access the address of the second case (pci-bios -B) made the system to crash very fast. There is a snapshot of the pci utility output without the -B option. -------------------------------------- Class = Bridge (Other) Vendor ID = 10b5h, PLX Technology, Inc. Device ID = 1024h, Acromag, Inc. IndustryPack Carrier Card PCI index = 0h Class Codes = 068000h Revision ID = 1h Bus number = 7 Device number = 1 Function num = 0 Status Reg = 280h Command Reg = 0h I/O space access disabled Memory space access disabled Bus Master disabled Special Cycle operations ignored Memory Write and Invalidate disabled Palette Snooping disabled Parity Error Response disabled Data/Address stepping disabled SERR# driver disabled Fast back-to-back transactions to different agents disabled PCI INTx enabled Header type = 0h Single-function BIST = 0h Build-in-self-test not supported Latency Timer = 0h Cache Line Size= 10h un-cacheable Subsystem Vendor ID = 10b5h Subsystem ID = 1024h Max Lat = 0ns Min Gnt = 0ns PCI Int Pin = INT A Interrupt line = 11 ------------------------ Is there a way to enabling the I/O and memory space? I search in the BIOS configuration and i don't find any configuration for the PCI card. Thank you, Sylvain Thu, 30 May 2013 18:58:26 GMT http://community.qnx.com/sf/go/post101903 Sylvain Comtois 2013-05-30T18:58:26Z http://community.qnx.com/sf/go/post101895 Il 30/05/2013 17.59, Allen Chen ha scritto: > I write a PCI card testing program, which attaches the device, map device memory, read/write bytes, unmap memory and detach the device, exits at last. I make about 15 times of continuous executing the program. Neutrino will crash or automatically reboot. > One time I snapped the screen. The picture is in attachment. Please view it and give me some advices to find the reason. > Thank you in advance. > Allen Chen Run the debug version (_g) of test instate of the release one , catch the .core generated and then use the postmortem debug or coreinfo on target to check the poit where crash appens in your program. Be sure dumper is running. M. Sangalli Thu, 30 May 2013 16:52:58 GMT http://community.qnx.com/sf/go/post101895 mario sangalli 2013-05-30T16:52:58Z http://community.qnx.com/sf/go/post101890 l am testing on x86 platform. The mapped device memory is the same as the original address, which is 09604100h. Maybe the program has some memory access error. How can I probe it? Thank you for the instant reply! Thu, 30 May 2013 16:16:32 GMT http://community.qnx.com/sf/go/post101890 Allen Chen 2013-05-30T16:16:32Z http://community.qnx.com/sf/go/post101889 > -----Message d'origine----- > De : Allen Chen [mailto:community-noreply@qnx.com] > Envoyé : 30 mai 2013 12:00 > À : general-bsp > Objet : PCI continuous access causes QNX reboot or crash > > I write a PCI card testing program, which attaches the device, map device > memory, read/write bytes, unmap memory and detach the device, exits at > last. I make about 15 times of continuous executing the program. Neutrino > will crash or automatically reboot. Your program is probably writting in memory area that it should not, or your hardware is causing some memory corruption. > One time I snapped the screen. The picture is in attachment. Please view it > and give me some advices to find the reason. > Thank you in advance. > Allen Chen > > > > _______________________________________________ > > QNX BSPs > http://community.qnx.com/sf/go/post101888 > To cancel your subscription to this discussion, please e-mail general-bsp- > unsubscribe@community.qnx.com Thu, 30 May 2013 16:03:39 GMT http://community.qnx.com/sf/go/post101889 Mario Charest 2013-05-30T16:03:39Z http://community.qnx.com/sf/go/post101888 I write a PCI card testing program, which attaches the device, map device memory, read/write bytes, unmap memory and detach the device, exits at last. I make about 15 times of continuous executing the program. Neutrino will crash or automatically reboot. One time I snapped the screen. The picture is in attachment. Please view it and give me some advices to find the reason. Thank you in advance. Allen Chen Thu, 30 May 2013 15:59:58 GMT http://community.qnx.com/sf/go/post101888 Allen Chen 2013-05-30T15:59:58Z http://community.qnx.com/sf/go/post101872 I have no idea how your hardware works, so am unable to help you with this. On 2013-05-30 2:29 AM, "Allen Chen" <community-noreply@qnx.com> wrote: >Thank you. I really don't know PCI interface. > >Here I face a new question. >I write 8bytes of time data into up iobase+0h~7h, it is expected that the >written bytes should be read from iobase+20h~27h. But it does not work. >However if I read from iobase+0h~7h after writing, it will be ok. > >Why? I cannot understand. > >在 2013-5-29，19:27，Hugh Brown <community-noreply@qnx.com> 写道： > >> PCI I/O addresses are determined by setting bit 0 in the base address >> register, so if you use the PCI_IO_ADDR() macro, it will return the >> correct address. If your I/O address is in base register 1, then that is >> the one you must use. >> >> >> >> >> On 2013-05-28 9:33 PM, "Allen Chen" <community-noreply@qnx.com> wrote: >> >>> Hi Hugh Brown. I slay pci-bios and run pci-bios -B, now the pci card >>>is >>> ok. >>> The obvious differences are I/O space access enabled, memory space >>> access enabled. >>> The PciBaseAddress[0] and PciBaseAddress[2] are Memory. >>> The PciBaseAddress[1] is IO, which base address value is 0x1000 and the >>> size is 128 bytes. >>> >>> I still have two questions: >>> 1. Should I use PciBaseAddress[1] to call mmap_device_io()? >>> 2. I got mapped IO base address 0x1001. Why does it only plus 1 based >>> PciBaseAddress[1]? Is this correct? >>> >>> Thank you! I have almost successfully ported the driver. >>> >>> 于 2013/5/29 1:23, Hugh Brown 写道: >>>> Are you running 'pci-bios -B' and do you have Plug 'n Play (PNP) >>>>turned >>>> off in the BIOS? >>>> >>>> >>>> >>>> On 2013-05-28 12:06 PM, "Allen Chen" <community-noreply@qnx.com> >>>>wrote: >>>> >>>>> Thank you for the reply. >>>>> I am testing on x86 system. What shall I do to solve the question? >>>>> >>>>> 在 2013-5-28，下午11:35，Hugh Brown <community-noreply@qnx.com> 写道： >>>>> >>>>>> If you are on a non-x86 platform, then the base address registers >>>>>>will >>>>>> only show up once you have performed a pci_attach_device. If you are >>>>>> on >>>>>> an >>>>>> x86 system, then the BIOS most probably doesn't know how to setup >>>>>>the >>>>>> device. >>>>>> >>>>>> >>>>>> >>>>>> >>>>>> On 2013-05-28 11:22 AM, "Allen Chen" <community-noreply@qnx.com> >>>>>> wrote: >>>>>> >>>>>>> What are I/O space access disabled, Memory space access disabled >>>>>>> mean? >>>>>>> It there anything wrong with the pic card? >>>>>>> >>>>>>> >>>>>>> #pci -vv >>>>>>> >>>>>>> PCI version = 3.00 >>>>>>> >>>>>>> Class = Bridge (Other) >>>>>>> Vendor ID = 10b5h, PLX Technology, Inc. >>>>>>> Device ID = 9050h, PCI <-> IOBus Bridge >>>>>>> PCI index = 0h >>>>>>> Class Codes = 068000h >>>>>>> Revision ID = 2h >>>>>>> Bus number = 7 >>>>>>> Device number = 13 >>>>>>> Function num = 0 >>>>>>> Status Reg = 280h >>>>>>> Command Reg = 0h >>>>>>> I/O space access disabled >>>>>>> Memory space access disabled >>>>>>> Bus Master disabled >>>>>>> Special Cycle operations ignored >>>>>>> Memory Write and Invalidate disabled >>>>>>> Palette Snooping disabled >>>>>>> Parity Error Response disabled >>>>>>> Data/Address stepping disabled >>>>>>> SERR# driver disabled >>>>>>> Fast back-to-back transactions to different agents disabled >>>>>>> PCI INTx enabled >>>>>>> Header type = 0h Single-function >>>>>>> BIST = 0h Build-in-self-test not supported >>>>>>> Latency Timer = 0h >>>>>>> Cache Line Size= 10h un-cacheable >>>>>>> Subsystem Vendor ID = 1h >>>>>>> Subsystem ID = 4859h >>>>>>> Max Lat = 0ns >>>>>>> Min Gnt = 0ns >>>>>>> PCI Int Pin = INT A >>>>>>> Interrupt line = no connection >>>>>>> Device Dependent Registers: >>>>>>> 0x040: 0000 0000 0000 0000 0000 0000 0000 0000 >>>>>>> ... >>>>>>> 0x0f0: 0000 0000 0000 0000 0000 0000 0000 0000 >>>>>>> >>>>>>> >>>>>>> >>>>>>> _______________________________________________ >>>>>>> >>>>>>> QNX BSPs >>>>>>> http://community.qnx.com/sf/go/post101761 >>>>>>> To cancel your subscription to this discussion, please e-mail >>>>>>> general-bsp-unsubscribe@community.qnx.com >>>>>> >>>>>> >>>>>> >>>>>> >>>>>> _______________________________________________ >>>>>> >>>>>> QNX BSPs >>>>>> http://community.qnx.com/sf/go/post101764 >>>>>> To cancel your subscription to this discussion, please e-mail >>>>>> general-bsp-unsubscribe@community.qnx.com >>>>> >>>>> >>>>> >>>>> _______________________________________________ >>>>> >>>>> QNX BSPs >>>>> http://community.qnx.com/sf/go/post101767 >>>>> To cancel your subscription to this discussion, please e-mail >>>>> general-bsp-unsubscribe@community.qnx.com >>>> >>>> >>>> >>>> >>>> _______________________________________________ >>>> >>>> QNX BSPs >>>> http://community.qnx.com/sf/go/post101776 >>>> To cancel your subscription to this discussion, please e-mail >>>> general-bsp-unsubscribe@community.qnx.com >>> >>> >>> >>> >>> >>> _______________________________________________ >>> >>> QNX BSPs >>> http://community.qnx.com/sf/go/post101791 >>> To cancel your subscription to this discussion, please e-mail >>> general-bsp-unsubscribe@community.qnx.com >> >> >> >> >> >> _______________________________________________ >> >> QNX BSPs >> http://community.qnx.com/sf/go/post101805 >> To cancel your subscription to this discussion, please e-mail >>general-bsp-unsubscribe@community.qnx.com > > > > >_______________________________________________ > >QNX BSPs >http://community.qnx.com/sf/go/post101856 >To cancel your subscription to this discussion, please e-mail >general-bsp-unsubscribe@community.qnx.com Thu, 30 May 2013 12:30:48 GMT http://community.qnx.com/sf/go/post101872 Hugh Brown 2013-05-30T12:30:48Z http://community.qnx.com/sf/go/post101856 Thank you. I really don't know PCI interface. Here I face a new question. I write 8bytes of time data into up iobase+0h~7h, it is expected that the written bytes should be read from iobase+20h~27h. But it does not work. However if I read from iobase+0h~7h after writing, it will be ok. Why? I cannot understand. 在 2013-5-29，19:27，Hugh Brown <community-noreply@qnx.com> 写道： > PCI I/O addresses are determined by setting bit 0 in the base address > register, so if you use the PCI_IO_ADDR() macro, it will return the > correct address. If your I/O address is in base register 1, then that is > the one you must use. > > > > > On 2013-05-28 9:33 PM, "Allen Chen" <community-noreply@qnx.com> wrote: > >> Hi Hugh Brown. I slay pci-bios and run pci-bios -B, now the pci card is >> ok. >> The obvious differences are I/O space access enabled, memory space >> access enabled. >> The PciBaseAddress[0] and PciBaseAddress[2] are Memory. >> The PciBaseAddress[1] is IO, which base address value is 0x1000 and the >> size is 128 bytes. >> >> I still have two questions: >> 1. Should I use PciBaseAddress[1] to call mmap_device_io()? >> 2. I got mapped IO base address 0x1001. Why does it only plus 1 based >> PciBaseAddress[1]? Is this correct? >> >> Thank you! I have almost successfully ported the driver. >> >> 于 2013/5/29 1:23, Hugh Brown 写道: >>> Are you running 'pci-bios -B' and do you have Plug 'n Play (PNP) turned >>> off in the BIOS? >>> >>> >>> >>> On 2013-05-28 12:06 PM, "Allen Chen" <community-noreply@qnx.com> wrote: >>> >>>> Thank you for the reply. >>>> I am testing on x86 system. What shall I do to solve the question? >>>> >>>> 在 2013-5-28，下午11:35，Hugh Brown <community-noreply@qnx.com> 写道： >>>> >>>>> If you are on a non-x86 platform, then the base address registers will >>>>> only show up once you have performed a pci_attach_device. If you are >>>>> on >>>>> an >>>>> x86 system, then the BIOS most probably doesn't know how to setup the >>>>> device. >>>>> >>>>> >>>>> >>>>> >>>>> On 2013-05-28 11:22 AM, "Allen Chen" <community-noreply@qnx.com> >>>>> wrote: >>>>> >>>>>> What are I/O space access disabled, Memory space access disabled >>>>>> mean? >>>>>> It there anything wrong with the pic card? >>>>>> >>>>>> >>>>>> #pci -vv >>>>>> >>>>>> PCI version = 3.00 >>>>>> >>>>>> Class = Bridge (Other) >>>>>> Vendor ID = 10b5h, PLX Technology, Inc. >>>>>> Device ID = 9050h, PCI <-> IOBus Bridge >>>>>> PCI index = 0h >>>>>> Class Codes = 068000h >>>>>> Revision ID = 2h >>>>>> Bus number = 7 >>>>>> Device number = 13 >>>>>> Function num = 0 >>>>>> Status Reg = 280h >>>>>> Command Reg = 0h >>>>>> I/O space access disabled >>>>>> Memory space access disabled >>>>>> Bus Master disabled >>>>>> Special Cycle operations ignored >>>>>> Memory Write and Invalidate disabled >>>>>> Palette Snooping disabled >>>>>> Parity Error Response disabled >>>>>> Data/Address stepping disabled >>>>>> SERR# driver disabled >>>>>> Fast back-to-back transactions to different agents disabled >>>>>> PCI INTx enabled >>>>>> Header type = 0h Single-function >>>>>> BIST = 0h Build-in-self-test not supported >>>>>> Latency Timer = 0h >>>>>> Cache Line Size= 10h un-cacheable >>>>>> Subsystem Vendor ID = 1h >>>>>> Subsystem ID = 4859h >>>>>> Max Lat = 0ns >>>>>> Min Gnt = 0ns >>>>>> PCI Int Pin = INT A >>>>>> Interrupt line = no connection >>>>>> Device Dependent Registers: >>>>>> 0x040: 0000 0000 0000 0000 0000 0000 0000 0000 >>>>>> ... >>>>>> 0x0f0: 0000 0000 0000 0000 0000 0000 0000 0000 >>>>>> >>>>>> >>>>>> >>>>>> _______________________________________________ >>>>>> >>>>>> QNX BSPs >>>>>> http://community.qnx.com/sf/go/post101761 >>>>>> To cancel your subscription to this discussion, please e-mail >>>>>> general-bsp-unsubscribe@community.qnx.com >>>>> >>>>> >>>>> >>>>> >>>>> _______________________________________________ >>>>> >>>>> QNX BSPs >>>>> http://community.qnx.com/sf/go/post101764 >>>>> To cancel your subscription to this discussion, please e-mail >>>>> general-bsp-unsubscribe@community.qnx.com >>>> >>>> >>>> >>>> _______________________________________________ >>>> >>>> QNX BSPs >>>> http://community.qnx.com/sf/go/post101767 >>>> To cancel your subscription to this discussion, please e-mail >>>> general-bsp-unsubscribe@community.qnx.com >>> >>> >>> >>> >>> _______________________________________________ >>> >>> QNX BSPs >>> http://community.qnx.com/sf/go/post101776 >>> To cancel your subscription to this discussion, please e-mail >>> general-bsp-unsubscribe@community.qnx.com >> >> >> >> >> >> _______________________________________________ >> >> QNX BSPs >> http://community.qnx.com/sf/go/post101791 >> To cancel your subscription to this discussion, please e-mail >> general-bsp-unsubscribe@community.qnx.com > > > > > > _______________________________________________ > > QNX BSPs > http://community.qnx.com/sf/go/post101805 > To cancel your subscription to this discussion, please e-mail general-bsp-unsubscribe@community.qnx.com Thu, 30 May 2013 06:29:58 GMT http://community.qnx.com/sf/go/post101856 Allen Chen 2013-05-30T06:29:58Z http://community.qnx.com/sf/go/post101805 PCI I/O addresses are determined by setting bit 0 in the base address register, so if you use the PCI_IO_ADDR() macro, it will return the correct address. If your I/O address is in base register 1, then that is the one you must use. On 2013-05-28 9:33 PM, "Allen Chen" <community-noreply@qnx.com> wrote: >Hi Hugh Brown. I slay pci-bios and run pci-bios -B, now the pci card is >ok. >The obvious differences are I/O space access enabled, memory space >access enabled. >The PciBaseAddress[0] and PciBaseAddress[2] are Memory. >The PciBaseAddress[1] is IO, which base address value is 0x1000 and the >size is 128 bytes. > >I still have two questions: >1. Should I use PciBaseAddress[1] to call mmap_device_io()? >2. I got mapped IO base address 0x1001. Why does it only plus 1 based >PciBaseAddress[1]? Is this correct? > >Thank you! I have almost successfully ported the driver. > >于 2013/5/29 1:23, Hugh Brown 写道: >> Are you running 'pci-bios -B' and do you have Plug 'n Play (PNP) turned >> off in the BIOS? >> >> >> >> On 2013-05-28 12:06 PM, "Allen Chen" <community-noreply@qnx.com> wrote: >> >>> Thank you for the reply. >>> I am testing on x86 system. What shall I do to solve the question? >>> >>> 在 2013-5-28，下午11:35，Hugh Brown <community-noreply@qnx.com> 写道： >>> >>>> If you are on a non-x86 platform, then the base address registers will >>>> only show up once you have performed a pci_attach_device. If you are >>>>on >>>> an >>>> x86 system, then the BIOS most probably doesn't know how to setup the >>>> device. >>>> >>>> >>>> >>>> >>>> On 2013-05-28 11:22 AM, "Allen Chen" <community-noreply@qnx.com> >>>>wrote: >>>> >>>>> What are I/O space access disabled, Memory space access disabled >>>>>mean? >>>>> It there anything wrong with the pic card? >>>>> >>>>> >>>>> #pci -vv >>>>> >>>>> PCI version = 3.00 >>>>> >>>>> Class = Bridge (Other) >>>>> Vendor ID = 10b5h, PLX Technology, Inc. >>>>> Device ID = 9050h, PCI <-> IOBus Bridge >>>>> PCI index = 0h >>>>> Class Codes = 068000h >>>>> Revision ID = 2h >>>>> Bus number = 7 >>>>> Device number = 13 >>>>> Function num = 0 >>>>> Status Reg = 280h >>>>> Command Reg = 0h >>>>> I/O space access disabled >>>>> Memory space access disabled >>>>> Bus Master disabled >>>>> Special Cycle operations ignored >>>>> Memory Write and Invalidate disabled >>>>> Palette Snooping disabled >>>>> Parity Error Response disabled >>>>> Data/Address stepping disabled >>>>> SERR# driver disabled >>>>> Fast back-to-back transactions to different agents disabled >>>>> PCI INTx enabled >>>>> Header type = 0h Single-function >>>>> BIST = 0h Build-in-self-test not supported >>>>> Latency Timer = 0h >>>>> Cache Line Size= 10h un-cacheable >>>>> Subsystem Vendor ID = 1h >>>>> Subsystem ID = 4859h >>>>> Max Lat = 0ns >>>>> Min Gnt = 0ns >>>>> PCI Int Pin = INT A >>>>> Interrupt line = no connection >>>>> Device Dependent Registers: >>>>> 0x040: 0000 0000 0000 0000 0000 0000 0000 0000 >>>>> ... >>>>> 0x0f0: 0000 0000 0000 0000 0000 0000 0000 0000 >>>>> >>>>> >>>>> >>>>> _______________________________________________ >>>>> >>>>> QNX BSPs >>>>> http://community.qnx.com/sf/go/post101761 >>>>> To cancel your subscription to this discussion, please e-mail >>>>> general-bsp-unsubscribe@community.qnx.com >>>> >>>> >>>> >>>> >>>> _______________________________________________ >>>> >>>> QNX BSPs >>>> http://community.qnx.com/sf/go/post101764 >>>> To cancel your subscription to this discussion, please e-mail >>>> general-bsp-unsubscribe@community.qnx.com >>> >>> >>> >>> _______________________________________________ >>> >>> QNX BSPs >>> http://community.qnx.com/sf/go/post101767 >>> To cancel your subscription to this discussion, please e-mail >>> general-bsp-unsubscribe@community.qnx.com >> >> >> >> >> _______________________________________________ >> >> QNX BSPs >> http://community.qnx.com/sf/go/post101776 >> To cancel your subscription to this discussion, please e-mail >>general-bsp-unsubscribe@community.qnx.com > > > > > >_______________________________________________ > >QNX BSPs >http://community.qnx.com/sf/go/post101791 >To cancel your subscription to this discussion, please e-mail >general-bsp-unsubscribe@community.qnx.com Wed, 29 May 2013 11:27:45 GMT http://community.qnx.com/sf/go/post101805 Hugh Brown 2013-05-29T11:27:45Z http://community.qnx.com/sf/go/post101800 Il 29/05/2013 10.30, Allen Chen ha scritto: > Hi mario, it is ok now. > I should use PciBaseAddress[2], it can write time and read time. That's > great! > > I still have two further questions: > 1. I must have PCL device start after bootup using by typing command > 'slay pci-bios' and 'pci-bios -B'. How to automatically execute > 'pci-bios -B' when booting? In such case, You have to modify the boot script in the .boot: use the Momentics system build and change the start up script, if You can. If You cannot change the boot,You have to run a script at start up time to do the work for You: try to place a rc.local script in /etc/rc.d/rc.local and make it executable, place in it your commands (I do not know if this works on your system...) > 2. Becuase PciBaseAddress[2] is BAR -2 [Mem] = 96500000h 32bit length > 2048 enabled, is it correct to use mmap_device_io(inf.PciBaseAddress[2], > inf.BaseAddressSize[2])? Use the mmap_device_memoty :-) M. Sangalli Wed, 29 May 2013 09:49:58 GMT http://community.qnx.com/sf/go/post101800 mario sangalli 2013-05-29T09:49:58Z http://community.qnx.com/sf/go/post101799 OK, I've made modification as you provided. I feel very happy to port this IRIG-B pci driver onto QNX. Thanks for all of your helps! 于 2013/5/29 16:30, mario sangalli 写道: >> Thank you. I understand now. >> I use mmap_device_io(PCI_IO_ADDR(inf.PciBaseAddress[1]), >> inf.BaseAddressSize[1]) to access I/O, and read/write bytes from/to PLC device. >> But I cannot write data into the device because the read bytes are all 0. > Chen, I suppose You want to access the PLX registers: instate of use the IO space, > map the memory one (the bar [0] ) and so You can access all the 128bytes as memory > it should be much more easy to debug. > > Remember to map in READ/WRITE mode if You want to write on them: > > pPLXregBase = mmap_device_memory( > NULL, (BaseAddressSize[0]),(PROT_READ|PROT_WRITE|PROT_NOCACHE), > 0, CpuBaseAddress[0] > ); > > M.Sangalli > > > > > _______________________________________________ > > QNX BSPs > http://community.qnx.com/sf/go/post101797 > To cancel your subscription to this discussion, please e-mail general-bsp-unsubscribe@community.qnx.com > Wed, 29 May 2013 08:44:01 GMT http://community.qnx.com/sf/go/post101799 Allen Chen 2013-05-29T08:44:01Z http://community.qnx.com/sf/go/post101798 The post contains invalid characters .Please click uhe above post link to view the content. Wed, 29 May 2013 08:31:01 GMT http://community.qnx.com/sf/go/post101798 Allen Chen 2013-05-29T08:31:01Z http://community.qnx.com/sf/go/post101797 >Thank you. I understand now. >I use mmap_device_io(PCI_IO_ADDR(inf.PciBaseAddress[1]), >inf.BaseAddressSize[1]) to access I/O, and read/write bytes from/to PLC device. >But I cannot write data into the device because the read bytes are all 0. Chen, I suppose You want to access the PLX registers: instate of use the IO space, map the memory one (the bar [0] ) and so You can access all the 128bytes as memory it should be much more easy to debug. Remember to map in READ/WRITE mode if You want to write on them: pPLXregBase = mmap_device_memory( NULL, (BaseAddressSize[0]),(PROT_READ|PROT_WRITE|PROT_NOCACHE), 0, CpuBaseAddress[0] ); M.Sangalli Wed, 29 May 2013 08:30:45 GMT http://community.qnx.com/sf/go/post101797 mario sangalli 2013-05-29T08:30:45Z http://community.qnx.com/sf/go/post101796 The post contains invalid characters .Please click uhe above post link to view the content. Wed, 29 May 2013 07:59:04 GMT http://community.qnx.com/sf/go/post101796 Allen Chen 2013-05-29T07:59:04Z http://community.qnx.com/sf/go/post101795 Thanks David. Uncommenting the debugging support section did the required thing. BR,Raghu Wed, 29 May 2013 07:10:57 GMT http://community.qnx.com/sf/go/post101795 Raghunandan Kamath 2013-05-29T07:10:57Z http://community.qnx.com/sf/go/post101794 The post contains invalid characters .Please click uhe above post link to view the content. Wed, 29 May 2013 06:27:24 GMT http://community.qnx.com/sf/go/post101794 mario sangalli 2013-05-29T06:27:24Z http://community.qnx.com/sf/go/post101791 Hi Hugh Brown. I slay pci-bios and run pci-bios -B, now the pci card is ok. The obvious differences are I/O space access enabled, memory space access enabled. The PciBaseAddress[0] and PciBaseAddress[2] are Memory. The PciBaseAddress[1] is IO, which base address value is 0x1000 and the size is 128 bytes. I still have two questions: 1. Should I use PciBaseAddress[1] to call mmap_device_io()? 2. I got mapped IO base address 0x1001. Why does it only plus 1 based PciBaseAddress[1]? Is this correct? Thank you! I have almost successfully ported the driver. 于 2013/5/29 1:23, Hugh Brown 写道: > Are you running 'pci-bios -B' and do you have Plug 'n Play (PNP) turned > off in the BIOS? > > > > On 2013-05-28 12:06 PM, "Allen Chen" <community-noreply@qnx.com> wrote: > >> Thank you for the reply. >> I am testing on x86 system. What shall I do to solve the question? >> >> 在 2013-5-28，下午11:35，Hugh Brown <community-noreply@qnx.com> 写道： >> >>> If you are on a non-x86 platform, then the base address registers will >>> only show up once you have performed a pci_attach_device. If you are on >>> an >>> x86 system, then the BIOS most probably doesn't know how to setup the >>> device. >>> >>> >>> >>> >>> On 2013-05-28 11:22 AM, "Allen Chen" <community-noreply@qnx.com> wrote: >>> >>>> What are I/O space access disabled, Memory space access disabled mean? >>>> It there anything wrong with the pic card? >>>> >>>> >>>> #pci -vv >>>> >>>> PCI version = 3.00 >>>> >>>> Class = Bridge (Other) >>>> Vendor ID = 10b5h, PLX Technology, Inc. >>>> Device ID = 9050h, PCI <-> IOBus Bridge >>>> PCI index = 0h >>>> Class Codes = 068000h >>>> Revision ID = 2h >>>> Bus number = 7 >>>> Device number = 13 >>>> Function num = 0 >>>> Status Reg = 280h >>>> Command Reg = 0h >>>> I/O space access disabled >>>> Memory space access disabled >>>> Bus Master disabled >>>> Special Cycle operations ignored >>>> Memory Write and Invalidate disabled >>>> Palette Snooping disabled >>>> Parity Error Response disabled >>>> Data/Address stepping disabled >>>> SERR# driver disabled >>>> Fast back-to-back transactions to different agents disabled >>>> PCI INTx enabled >>>> Header type = 0h Single-function >>>> BIST = 0h Build-in-self-test not supported >>>> Latency Timer = 0h >>>> Cache Line Size= 10h un-cacheable >>>> Subsystem Vendor ID = 1h >>>> Subsystem ID = 4859h >>>> Max Lat = 0ns >>>> Min Gnt = 0ns >>>> PCI Int Pin = INT A >>>> Interrupt line = no connection >>>> Device Dependent Registers: >>>> 0x040: 0000 0000 0000 0000 0000 0000 0000 0000 >>>> ... >>>> 0x0f0: 0000 0000 0000 0000 0000 0000 0000 0000 >>>> >>>> >>>> >>>> _______________________________________________ >>>> >>>> QNX BSPs >>>> http://community.qnx.com/sf/go/post101761 >>>> To cancel your subscription to this discussion, please e-mail >>>> general-bsp-unsubscribe@community.qnx.com >>> >>> >>> >>> >>> _______________________________________________ >>> >>> QNX BSPs >>> http://community.qnx.com/sf/go/post101764 >>> To cancel your subscription to this discussion, please e-mail >>> general-bsp-unsubscribe@community.qnx.com >> >> >> >> _______________________________________________ >> >> QNX BSPs >> http://community.qnx.com/sf/go/post101767 >> To cancel your subscription to this discussion, please e-mail >> general-bsp-unsubscribe@community.qnx.com > > > > > _______________________________________________ > > QNX BSPs > http://community.qnx.com/sf/go/post101776 > To cancel your subscription to this discussion, please e-mail general-bsp-unsubscribe@community.qnx.com Wed, 29 May 2013 01:33:28 GMT http://community.qnx.com/sf/go/post101791 Allen Chen 2013-05-29T01:33:28Z http://community.qnx.com/sf/go/post101780 devnp-shim.so should be found on your host system under: $QNX_HOST/target/qnx6/armle-v7/lib/dll/devnp-shim.so There is a section of the default build file for the OMAP5432 BSP, that is commented out by default, and needs to be un-commented, before the necessary components for remote debugging are included in the IFS image: ########################################################################### ## uncomment for debugging support ########################################################################### #devc-pty #ftpd #inetd #/bin/login = login #pdebug #qconn #telnetd #/etc/services = ../tools/qnx650/target/qnx6/etc/services #/etc/inetd.conf = { #ftp stream tcp nowait root /proc/boot/ftpd in.ftpd -l #telnet stream tcp nowait root /proc/boot/telnetd in.telnetd #} #/etc/ftpusers = { #/* Allow all users to connect to the ftp server */ #* allow #} #/etc/ftpd.conf = { #/* Make things a+rw by default */ #umask all 0000 #} # #/etc/passwd = { #root::0:0:Superuser:/root:/bin/sh #ftp::14:80:FTP User:/tmp: #} Tue, 28 May 2013 17:58:00 GMT http://community.qnx.com/sf/go/post101780 David Green 2013-05-28T17:58:00Z http://community.qnx.com/sf/go/post101776 Are you running 'pci-bios -B' and do you have Plug 'n Play (PNP) turned off in the BIOS? On 2013-05-28 12:06 PM, "Allen Chen" <community-noreply@qnx.com> wrote: >Thank you for the reply. >I am testing on x86 system. What shall I do to solve the question? > >在 2013-5-28，下午11:35，Hugh Brown <community-noreply@qnx.com> 写道： > >> If you are on a non-x86 platform, then the base address registers will >> only show up once you have performed a pci_attach_device. If you are on >>an >> x86 system, then the BIOS most probably doesn't know how to setup the >> device. >> >> >> >> >> On 2013-05-28 11:22 AM, "Allen Chen" <community-noreply@qnx.com> wrote: >> >>> What are I/O space access disabled, Memory space access disabled mean? >>> It there anything wrong with the pic card? >>> >>> >>> #pci -vv >>> >>> PCI version = 3.00 >>> >>> Class = Bridge (Other) >>> Vendor ID = 10b5h, PLX Technology, Inc. >>> Device ID = 9050h, PCI <-> IOBus Bridge >>> PCI index = 0h >>> Class Codes = 068000h >>> Revision ID = 2h >>> Bus number = 7 >>> Device number = 13 >>> Function num = 0 >>> Status Reg = 280h >>> Command Reg = 0h >>> I/O space access disabled >>> Memory space access disabled >>> Bus Master disabled >>> Special Cycle operations ignored >>> Memory Write and Invalidate disabled >>> Palette Snooping disabled >>> Parity Error Response disabled >>> Data/Address stepping disabled >>> SERR# driver disabled >>> Fast back-to-back transactions to different agents disabled >>> PCI INTx enabled >>> Header type = 0h Single-function >>> BIST = 0h Build-in-self-test not supported >>> Latency Timer = 0h >>> Cache Line Size= 10h un-cacheable >>> Subsystem Vendor ID = 1h >>> Subsystem ID = 4859h >>> Max Lat = 0ns >>> Min Gnt = 0ns >>> PCI Int Pin = INT A >>> Interrupt line = no connection >>> Device Dependent Registers: >>> 0x040: 0000 0000 0000 0000 0000 0000 0000 0000 >>> ... >>> 0x0f0: 0000 0000 0000 0000 0000 0000 0000 0000 >>> >>> >>> >>> _______________________________________________ >>> >>> QNX BSPs >>> http://community.qnx.com/sf/go/post101761 >>> To cancel your subscription to this discussion, please e-mail >>> general-bsp-unsubscribe@community.qnx.com >> >> >> >> >> >> _______________________________________________ >> >> QNX BSPs >> http://community.qnx.com/sf/go/post101764 >> To cancel your subscription to this discussion, please e-mail >>general-bsp-unsubscribe@community.qnx.com > > > > >_______________________________________________ > >QNX BSPs >http://community.qnx.com/sf/go/post101767 >To cancel your subscription to this discussion, please e-mail >general-bsp-unsubscribe@community.qnx.com Tue, 28 May 2013 17:23:56 GMT http://community.qnx.com/sf/go/post101776 Hugh Brown 2013-05-28T17:23:56Z http://community.qnx.com/sf/go/post101767 Thank you for the reply. I am testing on x86 system. What shall I do to solve the question? 在 2013-5-28，下午11:35，Hugh Brown <community-noreply@qnx.com> 写道： > If you are on a non-x86 platform, then the base address registers will > only show up once you have performed a pci_attach_device. If you are on an > x86 system, then the BIOS most probably doesn't know how to setup the > device. > > > > > On 2013-05-28 11:22 AM, "Allen Chen" <community-noreply@qnx.com> wrote: > >> What are I/O space access disabled, Memory space access disabled mean? >> It there anything wrong with the pic card? >> >> >> #pci -vv >> >> PCI version = 3.00 >> >> Class = Bridge (Other) >> Vendor ID = 10b5h, PLX Technology, Inc. >> Device ID = 9050h, PCI <-> IOBus Bridge >> PCI index = 0h >> Class Codes = 068000h >> Revision ID = 2h >> Bus number = 7 >> Device number = 13 >> Function num = 0 >> Status Reg = 280h >> Command Reg = 0h >> I/O space access disabled >> Memory space access disabled >> Bus Master disabled >> Special Cycle operations ignored >> Memory Write and Invalidate disabled >> Palette Snooping disabled >> Parity Error Response disabled >> Data/Address stepping disabled >> SERR# driver disabled >> Fast back-to-back transactions to different agents disabled >> PCI INTx enabled >> Header type = 0h Single-function >> BIST = 0h Build-in-self-test not supported >> Latency Timer = 0h >> Cache Line Size= 10h un-cacheable >> Subsystem Vendor ID = 1h >> Subsystem ID = 4859h >> Max Lat = 0ns >> Min Gnt = 0ns >> PCI Int Pin = INT A >> Interrupt line = no connection >> Device Dependent Registers: >> 0x040: 0000 0000 0000 0000 0000 0000 0000 0000 >> ... >> 0x0f0: 0000 0000 0000 0000 0000 0000 0000 0000 >> >> >> >> _______________________________________________ >> >> QNX BSPs >> http://community.qnx.com/sf/go/post101761 >> To cancel your subscription to this discussion, please e-mail >> general-bsp-unsubscribe@community.qnx.com > > > > > > _______________________________________________ > > QNX BSPs > http://community.qnx.com/sf/go/post101764 > To cancel your subscription to this discussion, please e-mail general-bsp-unsubscribe@community.qnx.com Tue, 28 May 2013 16:06:41 GMT http://community.qnx.com/sf/go/post101767 Allen Chen 2013-05-28T16:06:41Z http://community.qnx.com/sf/go/post101764 If you are on a non-x86 platform, then the base address registers will only show up once you have performed a pci_attach_device. If you are on an x86 system, then the BIOS most probably doesn't know how to setup the device. On 2013-05-28 11:22 AM, "Allen Chen" <community-noreply@qnx.com> wrote: >What are I/O space access disabled, Memory space access disabled mean? >It there anything wrong with the pic card? > > >#pci -vv > >PCI version = 3.00 > >Class = Bridge (Other) >Vendor ID = 10b5h, PLX Technology, Inc. >Device ID = 9050h, PCI <-> IOBus Bridge >PCI index = 0h >Class Codes = 068000h >Revision ID = 2h >Bus number = 7 >Device number = 13 >Function num = 0 >Status Reg = 280h >Command Reg = 0h > I/O space access disabled > Memory space access disabled > Bus Master disabled > Special Cycle operations ignored > Memory Write and Invalidate disabled > Palette Snooping disabled > Parity Error Response disabled > Data/Address stepping disabled > SERR# driver disabled > Fast back-to-back transactions to different agents disabled > PCI INTx enabled >Header type = 0h Single-function >BIST = 0h Build-in-self-test not supported >Latency Timer = 0h >Cache Line Size= 10h un-cacheable >Subsystem Vendor ID = 1h >Subsystem ID = 4859h >Max Lat = 0ns >Min Gnt = 0ns >PCI Int Pin = INT A >Interrupt line = no connection >Device Dependent Registers: >0x040: 0000 0000 0000 0000 0000 0000 0000 0000 >... >0x0f0: 0000 0000 0000 0000 0000 0000 0000 0000 > > > >_______________________________________________ > >QNX BSPs >http://community.qnx.com/sf/go/post101761 >To cancel your subscription to this discussion, please e-mail >general-bsp-unsubscribe@community.qnx.com Tue, 28 May 2013 15:35:58 GMT http://community.qnx.com/sf/go/post101764 Hugh Brown 2013-05-28T15:35:58Z http://community.qnx.com/sf/go/post101761 What are I/O space access disabled, Memory space access disabled mean? It there anything wrong with the pic card? #pci -vv PCI version = 3.00 Class = Bridge (Other) Vendor ID = 10b5h, PLX Technology, Inc. Device ID = 9050h, PCI <-> IOBus Bridge PCI index = 0h Class Codes = 068000h Revision ID = 2h Bus number = 7 Device number = 13 Function num = 0 Status Reg = 280h Command Reg = 0h I/O space access disabled Memory space access disabled Bus Master disabled Special Cycle operations ignored Memory Write and Invalidate disabled Palette Snooping disabled Parity Error Response disabled Data/Address stepping disabled SERR# driver disabled Fast back-to-back transactions to different agents disabled PCI INTx enabled Header type = 0h Single-function BIST = 0h Build-in-self-test not supported Latency Timer = 0h Cache Line Size= 10h un-cacheable Subsystem Vendor ID = 1h Subsystem ID = 4859h Max Lat = 0ns Min Gnt = 0ns PCI Int Pin = INT A Interrupt line = no connection Device Dependent Registers: 0x040: 0000 0000 0000 0000 0000 0000 0000 0000 ... 0x0f0: 0000 0000 0000 0000 0000 0000 0000 0000 Tue, 28 May 2013 15:22:00 GMT http://community.qnx.com/sf/go/post101761 Allen Chen 2013-05-28T15:22:00Z http://community.qnx.com/sf/go/post101755 Hi, The Momentics IDE is not able to connect to the" TI OMAP5432 EVM" with the image build from the source available in the foundry27. Followed the release notes and have applied the "patch-650SP1-3507". I can see the EVM is able to get a IP address and can ping the windows machine successfully. Vice versa is able successful. But giving the EVM IP address in the "New Target", the IDE is not able to make connection to the EVM. However, I do not see the "devnp-shim.so" required lib for network driver. Let me know how to get the IDE connected to the EVM. BR,Raghu Tue, 28 May 2013 14:12:30 GMT http://community.qnx.com/sf/go/post101755 Raghunandan Kamath 2013-05-28T14:12:30Z http://community.qnx.com/sf/go/post101743 Try running the pci server with the '-B' command line option. On 2013-05-28 7:26 AM, "Allen Chen" <community-noreply@qnx.com> wrote: >I don't know whether this topic should be posted here. If should not, >please help me to move it. >There is a Linux PCI IRIG-B time-synchronizing card driver for me to port >onto QNX. The source code is attached, i.e. PCI_SZK.c. > >I wrote a test pci program (attachment testpci.c) and have detected >successfully the named pci card. >But when run testpci, it will print all the values of BaseAddressSize, >CpuBaseAddress, PciBaseAddress are 0. The result of testpci is attached >as testpci.log. > >I also attach the output of pci -vv command, i.e. pciv.log. > >Any advice will be greatly appreciated. > >Allen Chen > > > >_______________________________________________ > >QNX BSPs >http://community.qnx.com/sf/go/post101742 >To cancel your subscription to this discussion, please e-mail >general-bsp-unsubscribe@community.qnx.com Tue, 28 May 2013 11:50:43 GMT http://community.qnx.com/sf/go/post101743 Hugh Brown 2013-05-28T11:50:43Z http://community.qnx.com/sf/go/post101742 I don't know whether this topic should be posted here. If should not, please help me to move it. There is a Linux PCI IRIG-B time-synchronizing card driver for me to port onto QNX. The source code is attached, i.e. PCI_SZK.c. I wrote a test pci program (attachment testpci.c) and have detected successfully the named pci card. But when run testpci, it will print all the values of BaseAddressSize, CpuBaseAddress, PciBaseAddress are 0. The result of testpci is attached as testpci.log. I also attach the output of pci -vv command, i.e. pciv.log. Any advice will be greatly appreciated. Allen Chen Tue, 28 May 2013 11:26:14 GMT http://community.qnx.com/sf/go/post101742 Allen Chen 2013-05-28T11:26:14Z http://community.qnx.com/sf/go/post101598 Hi; I am trying to boot beagleboard-xm rev c (4611xM383 card), with qnx 6.5.0 & SP1 but ethernet device cannot be identified. What can be the problem? I have "readenv() fail" at boot time. Any suggestions and comments? Thank you. Wed, 22 May 2013 14:10:35 GMT http://community.qnx.com/sf/go/post101598 Önder Altan 2013-05-22T14:10:35Z http://community.qnx.com/sf/go/post101561 Unfortunately I need the LCD working, not DVI :( I've been looking at this problem quite extensively, and I've determined that I need to modify the display driver code in order to get it functional with our board (similar to a beagleboard, but not quite the same). Simply modifying the config files won't work for our system Mon, 20 May 2013 18:18:04 GMT http://community.qnx.com/sf/go/post101561 David Kvasnica 2013-05-20T18:18:04Z http://community.qnx.com/sf/go/post101550 hi,thanks for your advice very much,can i ask you a question?what do you use the beagleboard for? now i am writing a USB driver for a USB camera,but i don't know how to do it,because i don't have a USB DDK,have you ever did this kind of work before,would you please give me some advices,thanks very much. White Sun, 19 May 2013 13:05:54 GMT http://community.qnx.com/sf/go/post101550 white shaw 2013-05-19T13:05:54Z http://community.qnx.com/sf/go/post101548 Sent from my BlackBerry 10 smartphone. From: Peter Barrie Sent: Saturday, May 18, 2013 9:48 AM To: general-bsp Reply To: general-bsp@community.qnx.com Subject: Re: can't use usb on omap3530 I came across the same problem on Revision C board, since USB is disabled at boot time since RevC. I provided a quick fix for this: See: http://community.qnx.com/sf/go/projects.bsp/discussion.bsp.topc20371 However, you can ignore this since the USB is now enabled in the latest BSP that you can download from Foundry27. _______________________________________________ QNX BSPs http://community.qnx.com/sf/go/post101547 To cancel your subscription to this discussion, please e-mail general-bsp-unsubscribe@community.qnx.com Sat, 18 May 2013 15:57:42 GMT http://community.qnx.com/sf/go/post101548 David Sarrazin 2013-05-18T15:57:42Z http://community.qnx.com/sf/go/post101547 I came across the same problem on Revision C board, since USB is disabled at boot time since RevC. I provided a quick fix for this: See: http://community.qnx.com/sf/go/projects.bsp/discussion.bsp.topc20371 However, you can ignore this since the USB is now enabled in the latest BSP that you can download from Foundry27. Sat, 18 May 2013 13:48:52 GMT http://community.qnx.com/sf/go/post101547 Peter Barrie 2013-05-18T13:48:52Z http://community.qnx.com/sf/go/post101546 Beagleboard xM Revision C / QNX 6.5 SP1 Does anybody have an omap35xx.conf (and display.conf) configuration setting for standard LCD monitor 1024x768 @ 60 or 75Hz ? Or alternatively can somebody point me at appropriate documentation for this file so that I can calculate the settings? I've searched quite extensively but cannot find this information. I'm currently running at 800x600 (with Dell LCD monitor 1908FPC) and can provide working settings if anybody has had problems. Also, I'm running qt applications on this board and am willing to help help if anybody has had any initial problems (Windows XP host and two working targets: Beagleboard xM RevC and latest QNX VmWare image ). Thanks, Pete Sat, 18 May 2013 13:40:04 GMT http://community.qnx.com/sf/go/post101546 Peter Barrie 2013-05-18T13:40:04Z http://community.qnx.com/sf/go/post101545 I have spent several days before sorting an identical problem. Try setting disptype=5 for the display configuration that you enable (the first un-commented configuration line) In the omap35xx.conf file shipped with the 6.4 BSP the comment at top of file says: # disptype 0 - DVI, 1 - QVGA (3530evm), 2 - VGA (3530evm), 3 - Custom, 4 - AM3517EVM (LCD), 5 - DVI for omap3730 xM A/B However, this does not carry through to the omap45xx.conf file shipped with the latest version of the BSP, where the option 5 part of the comment is unfortunately missed out! So I have: # VGA 800 x 600 @ 56Hz VESA 1024 800 625 600 35.16 56.25 36.00 24 72 + 128 1 2 + 22 (tested on Beagle DVI) WORKING Beagleboard xM Rev C Display.conf hsw=72,hfp=24,hbp=128,vsw=2,vfp=1,vbp=22,ivs=1,ihs=1,ipc=1,ieo=0x0,acb=0,acbi=0,pcd=0x4,ppl=800,lpp=600,irq=25,disptype=5,lcdfmt=0x3,dpowerg70=1 Note my display.conf setting: device { drivername=omap35xx vid=0 did=0 modeopts=/etc/system/config/omap35xx.conf display { xres=800 yres=600 refresh=60 pixel_format=rgb565 } } Just to note - if you look closely at the shipped file you will see that disptype=5 is actually set for the default display configuration that comes enabled with this file (720 x 400 @ 70Hz IBM) - it is just not documented. BTW I have tested this with Beagleboard xM Revison C board and it is working. It is displaying with settings above on a standard 800x600 mode on desktop LCD monitor: Dell 1908FPC. Also, I am now running qt on the board and it is displaying OK. Sat, 18 May 2013 13:25:40 GMT http://community.qnx.com/sf/go/post101545 Peter Barrie 2013-05-18T13:25:40Z http://community.qnx.com/sf/go/post101488 Hi, I've downloaded "TI OMAP5432 EVM" BSP. I see that main() enables mmu and disable it back when starting SMP. Is this a requirement for A15 SMP ? Thanks, Ran Thu, 16 May 2013 15:39:55 GMT http://community.qnx.com/sf/go/post101488 ran wainstein 2013-05-16T15:39:55Z http://community.qnx.com/sf/go/post101430 Hi all, I have been working on the freescale p4080 for months.The QNX bsp downloaded from the QNX.com downloaded center works perfect, but when I tried to run the OS on the Windriver hypervisor instead of runing directly on the hardware, smp initiation failed. When runing on the hardware, the OS init the smp by setting the registers in CCSR, and when running on the hypervisor, hypervisor mapped the CCSR space, and the data in related registers seems OK, but actually smp initiation was failed. I was wondering if the hypervisor had an effect on the initiation of smp. I worked on the hypervisor for several days and found out that the hypervisor use "spin table" to init the OS running on it, I tried to use the "spin table" instead of the function of CCSR to init smp, but it still doesn't work. Anyone has related works and can lend me a hand please? Wed, 15 May 2013 07:43:35 GMT http://community.qnx.com/sf/go/post101430 xu kanfeng 2013-05-15T07:43:35Z http://community.qnx.com/sf/go/post101320 Hi Fred, Is there any idea to support BSPs for Qualcomm chipsets? Regards, Krishna Kanth Bangalore, India Mon, 13 May 2013 05:49:49 GMT http://community.qnx.com/sf/go/post101320 Krishna Kanth Reddy 2013-05-13T05:49:49Z http://community.qnx.com/sf/go/post101208 Hi, I am also having this exact problem and can't find where we have gone wrong. If anyone can give me an idea where our problem is that would be a great help! Cheers, Stefan Tue, 07 May 2013 12:49:39 GMT http://community.qnx.com/sf/go/post101208 Stefan Hall 2013-05-07T12:49:39Z http://community.qnx.com/sf/go/post101206 http://newsroom.intel.com/community/intel_newsroom/blog/2013/05/06/intel-launches-low-power-high-performance-silvermont-microarchitecture --Armin Tue, 07 May 2013 10:48:00 GMT http://community.qnx.com/sf/go/post101206 Armin Steinhoff 2013-05-07T10:48:00Z http://community.qnx.com/sf/go/post101159 Dear all, I am having a problem with Nitrogen6x board.I am using the QNX BSP provided for Nitrogen6x. I am trying to write a C code for Canbus and Serial Port seperately. I can transmit Canbus and Serial Port data from board but can't recieve any data. I made all possible configration (change O_NDELAY,O_NOCTTY CLOCAL, CREAD, CS8 for serial port) . I tested serial port with connecting Tx and Rx so there shouldn't be a baud rate problem. What should i do about that problem? Thanks, Çağrı AKALIN Mon, 06 May 2013 06:44:40 GMT http://community.qnx.com/sf/go/post101159 cagri akalin 2013-05-06T06:44:40Z http://community.qnx.com/sf/go/post101152 > I know the underlying processor has the capability to swap to little endian in > hardware, ... I'm not sure that's true... In fact I don't remember choices other than MSB first with any processors; but that doesn't mean much :) From the am335x user manual: "The SPI words are transferred with MSB first." I don't know how one would change that. I'm fairly new to QNX (less new to the am335x), and since you are already sending spi data; how did you link the spi-master libraries to your project? I get constant errors saying that the linker can't find spi-open(). I've been searching for tips on this for weeks, but I can't quite figure out how to get a spi version of "hello-world" on the beaglebone under QNX. I can build the image, boot, connect, blink LEDs, and debug; but no spi so far. fileHandle = open( "/dev/spi1", O_RDWR ); Doesn't help either. Any help you could post might help a lot of people, since it's not really out there. > This is the initialisation code I am using: > > const char SPI_HANDLE[] = "/dev/spi0"; > const int SPI_SPEED = 125000; > > //Gain hardware access > ThreadCtl(_NTO_TCTL_IO, 0); > > // Load SPI Driver > if (access(SPI_HANDLE, F_OK) == -1) > { > system("spi-master -d am335x base=0x481A0100,irq=125,edma=1,edmairq=555, > edmachannel=43"); > std::cout << "SPI Driver Loaded..." << std::endl; > } > > // Open SPI Module (/dev/spi0 actually loads SPI1 in hardware...) > fd_ = spi_open(SPI_HANDLE); > > if (fd_ < 0) > std::cout << "Unable to open SPI..." << std::endl; > else > { > spi_devinfo_t info; > if(spi_getdevinfo(fd_, SPI_DEV_DEFAULT, &info) != EOK) > std::cout << "Error reading SPI Configuration!" << std::endl; > > //info.cfg.mode |= SPI_MODE_CSPOL_HIGH; > info.cfg.mode |= SPI_MODE_CSSTAT_HIGH; > //info.cfg.mode |= SPI_MODE_CSHOLD_HIGH; > info.cfg.clock_rate = SPI_SPEED; > info.cfg.mode &= ~SPI_MODE_CKPOL_HIGH; > info.cfg.mode |= SPI_MODE_CKPHASE_HALF; > //info.cfg.mode |= SPI_MODE_RDY_EDGE; > //info.cfg.mode |= SPI_MODE_BODER_MSB; > //info.cfg.mode |= SPI_MODE_RDY_LEVEL; > //info.cfg.mode |= SPI_MODE_IDLE_INSERT; > > if (spi_setcfg(fd_, SPI_DEV_DEFAULT, &info.cfg) != EOK) > std::cout << "Error setting SPI Configuration!" << std::endl; > > if(spi_getdevinfo(fd_, SPI_DEV_DEFAULT, &info) != EOK) > std::cout << "Error reading SPI Configuration!" << std::endl; > > const int w = 16; > > std::cout << std::left; > std::cout << "+------------------------------------+" << std::endl; > std::cout << "| BeagleBone SPI1 Configuration |" << std::endl; > std::cout << "+-----------------+------------------+" << std::endl; > std::cout << "| Clock Rate: | " << std::setw(w) << info.cfg.clock_rate < > < " |" << std::endl; > std::cout << "| Clock Polarity: | " << std::setw(w) << ((info.cfg.mode & > SPI_MODE_CKPOL_HIGH) ? 1 : 0) << " |" << std::endl; > std::cout << "| Clock Phase: | " << std::setw(w) << ((info.cfg.mode & > SPI_MODE_CKPHASE_HALF) ? 1 : 0) << " |" << std::endl; > std::cout << "| Bit Order: | " << std::setw(w) << ((info.cfg.mode & > SPI_MODE_BODER_MSB) ? 1 : 0) << " |" << std::endl; > std::cout << "| CS Polarity: | " << std::setw(w) << ((info.cfg.mode & > SPI_MODE_CSPOL_HIGH) ? 1 : 0) << " |" << std::endl; > std::cout << "| CSSTAT: | " << std::setw(w) << ((info.cfg.mode & > SPI_MODE_CSSTAT_HIGH) ? 1 : 0) << " |" << std::endl; > std::cout << "| Ready Edge: | " << std::setw(w) << ((info.cfg.mode & > SPI_MODE_RDY_EDGE) ? 1 : 0) << " |" << std::endl; > std::cout << "| Ready Level: | " << std::setw(w) << ((info.cfg.mode & > SPI_MODE_RDY_LEVEL) ? 1 : 0) << " |" << std::endl; > std::cout << "| Idle Insert: | " << std::setw(w) << ((info.cfg.mode & > SPI_MODE_IDLE_INSERT) ? 1 : 0) << " |" << std::endl; > std::cout << "+-----------------+------------------+" << std::endl; > } > > Any help towards fixing this problem will be greatly appreciated. > > Thanks, Thomas. Sun, 05 May 2013 03:30:05 GMT http://community.qnx.com/sf/go/post101152 Dan Kirkpatrick 2013-05-05T03:30:05Z http://community.qnx.com/sf/go/post101137 Hi ! I have an issue with the CAN Device on beagle bone running QNX. I am using the QNX BSP provided for beaglebone[1]. I initialized the CAN device by adding the binary to the QNX image and I am able to send messages in a self-test loop back mode using echo testing > /dev/can1/tx16 and cat /dev/can1/rx0. I am trying to write a C code for transmitting messages using the library provided in the BSP under /src/hardware/can . My code initialize the structures(messages and can device) provided in canam335x.h and calls the function can_drvr_transmit(&(devlist[16].cdev)); When the program reach this ligne(in canam335x.c/ function dcansetobj() ) out32(devinfo->base + AM335X_DCAN_IF1CMD, cmd); the board reboot. I tried to debug this problem by printing the register status and compare the values obtained by a sample echo testing > /dev/can1/tx16 and executing my code. [Attached files] Did you guys tired to test the can bus on beagle bone running QNX before? Anyone had this bug before? Any sample code for help? Thanks. [1]: http://community.qnx.com/sf/wiki/do/viewPage/projects.bsp/wiki/TiAm335Beaglebone Fri, 03 May 2013 19:09:58 GMT http://community.qnx.com/sf/go/post101137 aymen ketata 2013-05-03T19:09:58Z http://community.qnx.com/sf/go/post101128 Hi John, The QNX BSP for beaglebone has a library for the CAN device. I am using it to write a C code for transmitting messages. It's in src/hardware/can. I am still working on it but I guess this library should be helpful for you. Fri, 03 May 2013 15:38:19 GMT http://community.qnx.com/sf/go/post101128 aymen ketata 2013-05-03T15:38:19Z http://community.qnx.com/sf/go/post101121 Hi! I have the same issue as you guys. I could include and initiate the CAN device by including the binary in my build image. I was able to echo messages on the tx mailboxes and read it on the rx ones. I want to write C code for that so I used the library provided by the BSP under src/hardware/can. My code crashes (and QNX reboot) when I try to send a cmd to the can register (in dcan_setobj function when it reaches IF1/IF2 message control command). Did you guys figured out how to use the library? did you test the can bus? any help with sample code? Thanks. Fri, 03 May 2013 14:55:09 GMT http://community.qnx.com/sf/go/post101121 aymen ketata 2013-05-03T14:55:09Z http://community.qnx.com/sf/go/post101120 Hi, I am facing the same issue. Has anyone found the solution? BR,Raghu Fri, 03 May 2013 14:28:17 GMT http://community.qnx.com/sf/go/post101120 Raghunandan Kamath 2013-05-03T14:28:17Z http://community.qnx.com/sf/go/post100934 Hey Everyone, Writing an application that uses SPI to communicate with a handheld controller using the BeagleBone. I have written code to successfully communicate between the two, however I have to manually reverse the Endian-ness of the transmitted information in software. The controller requires little endian (LSB first) data, where QNX as it is currently setup only allows big endian transmission. I know the underlying processor has the capability to swap to little endian in hardware, but I have not been able to find a relevant setting that will do this for me. This is the initialisation code I am using: const char SPI_HANDLE[] = "/dev/spi0"; const int SPI_SPEED = 125000; //Gain hardware access ThreadCtl(_NTO_TCTL_IO, 0); // Load SPI Driver if (access(SPI_HANDLE, F_OK) == -1) { system("spi-master -d am335x base=0x481A0100,irq=125,edma=1,edmairq=555,edmachannel=43"); std::cout << "SPI Driver Loaded..." << std::endl; } // Open SPI Module (/dev/spi0 actually loads SPI1 in hardware...) fd_ = spi_open(SPI_HANDLE); if (fd_ < 0) std::cout << "Unable to open SPI..." << std::endl; else { spi_devinfo_t info; if(spi_getdevinfo(fd_, SPI_DEV_DEFAULT, &info) != EOK) std::cout << "Error reading SPI Configuration!" << std::endl; //info.cfg.mode |= SPI_MODE_CSPOL_HIGH; info.cfg.mode |= SPI_MODE_CSSTAT_HIGH; //info.cfg.mode |= SPI_MODE_CSHOLD_HIGH; info.cfg.clock_rate = SPI_SPEED; info.cfg.mode &= ~SPI_MODE_CKPOL_HIGH; info.cfg.mode |= SPI_MODE_CKPHASE_HALF; //info.cfg.mode |= SPI_MODE_RDY_EDGE; //info.cfg.mode |= SPI_MODE_BODER_MSB; //info.cfg.mode |= SPI_MODE_RDY_LEVEL; //info.cfg.mode |= SPI_MODE_IDLE_INSERT; if (spi_setcfg(fd_, SPI_DEV_DEFAULT, &info.cfg) != EOK) std::cout << "Error setting SPI Configuration!" << std::endl; if(spi_getdevinfo(fd_, SPI_DEV_DEFAULT, &info) != EOK) std::cout << "Error reading SPI Configuration!" << std::endl; const int w = 16; std::cout << std::left; std::cout << "+------------------------------------+" << std::endl; std::cout << "| BeagleBone SPI1 Configuration |" << std::endl; std::cout << "+-----------------+------------------+" << std::endl; std::cout << "| Clock Rate: | " << std::setw(w) << info.cfg.clock_rate << " |" << std::endl; std::cout << "| Clock Polarity: | " << std::setw(w) << ((info.cfg.mode & SPI_MODE_CKPOL_HIGH) ? 1 : 0) << " |" << std::endl; std::cout << "| Clock Phase: | " << std::setw(w) << ((info.cfg.mode & SPI_MODE_CKPHASE_HALF) ? 1 : 0) << " |" << std::endl; std::cout << "| Bit Order: | " << std::setw(w) << ((info.cfg.mode & SPI_MODE_BODER_MSB) ? 1 : 0) << " |" << std::endl; std::cout << "| CS Polarity: | " << std::setw(w) << ((info.cfg.mode & SPI_MODE_CSPOL_HIGH) ? 1 : 0) << " |" << std::endl; std::cout << "| CSSTAT: | " << std::setw(w) << ((info.cfg.mode & SPI_MODE_CSSTAT_HIGH) ? 1 : 0) << " |" << std::endl; std::cout << "| Ready Edge: | " << std::setw(w) << ((info.cfg.mode & SPI_MODE_RDY_EDGE) ? 1 : 0) << " |" << std::endl; std::cout << "| Ready Level: | " << std::setw(w) << ((info.cfg.mode & SPI_MODE_RDY_LEVEL) ? 1 : 0) << " |" << std::endl; std::cout << "| Idle Insert: | " << std::setw(w) << ((info.cfg.mode & SPI_MODE_IDLE_INSERT) ? 1 : 0) << " |" << std::endl; std::cout << "+-----------------+------------------+" << std::endl; } Any help towards fixing this problem will be greatly appreciated. Thanks, Thomas. Sun, 28 Apr 2013 09:57:32 GMT http://community.qnx.com/sf/go/post100934 Thomas Hudson 2013-04-28T09:57:32Z http://community.qnx.com/sf/go/post100927 I am trying to get Qt 5 running on the Sabre Lite evaluation board using the QNX Accelerator Kit. The QNX Accelerator Kit Quickstart Guide says the "Qt 5 QNX SDK" must be installed. • the Qt 5 QNX SDK, frs.mmmm.qt5_software_development_kit. Install this SDK on your Windows PC. Where can this be downloaded? I can't find any information on the QNX or Qt sites. Thank you! Fri, 26 Apr 2013 21:37:44 GMT http://community.qnx.com/sf/go/post100927 David Lafreniere 2013-04-26T21:37:44Z http://community.qnx.com/sf/go/post100925 Solved. I was using the wrong SP1 and needed the Windows installation. Fri, 26 Apr 2013 21:23:57 GMT http://community.qnx.com/sf/go/post100925 David Lafreniere 2013-04-26T21:23:57Z http://community.qnx.com/sf/go/post100923 Hi guys, I want to add some archives to my projects and build it afterwards. Is there any fency thing to do to add it to the build process using Momentics IDE ?? Thanks Fri, 26 Apr 2013 19:52:36 GMT http://community.qnx.com/sf/go/post100923 john kurcher 2013-04-26T19:52:36Z http://community.qnx.com/sf/go/post100899 I want to implement CAN communication on beaglebone running QNX. I built a new image of QNX supporting CAN. I couldn't find a library or a sample code using CAN protocol on beaglebone. Most of forums says that this implementation is hard and has not been tested before. Anyone has an idea, help ?? Fri, 26 Apr 2013 14:24:37 GMT http://community.qnx.com/sf/go/post100899 john kurcher 2013-04-26T14:24:37Z http://community.qnx.com/sf/go/post100861 Hi I would like to know if QNX can support OSPF protocol (Open shortest path first). We are looking for the same in our project. can some one help with - How it can be activiated, which BSP/QNX version .. in case QNX supports - Is there any alternate approach to acheive the funcationality .. thanks Ravi Wed, 24 Apr 2013 17:17:32 GMT http://community.qnx.com/sf/go/post100861 ravi varma 2013-04-24T17:17:32Z http://community.qnx.com/sf/go/post100851 Hi, are there plans to support the new BeagleBone Black ? Time frames ? --Armin PS: the ARMv7/QNX6 version of DACHSview works now with the BeagleBone ! It is using the JIT support of TCC for creation of functionblock code ... http://www.the-better-idea.com/embedded_CC.htm Wed, 24 Apr 2013 14:43:09 GMT http://community.qnx.com/sf/go/post100851 Armin Steinhoff 2013-04-24T14:43:09Z http://community.qnx.com/sf/go/post100832 > We have many variants of the server.c code to cater for different > platforms, so to answer your question, no, we won't be merging and PCI > code. I was thinking, there could be a Master-Source-Tree at QSSL, where the newest pci-server is maintained (e.g. server.c). Also I thougth, this actual pci-server would have further developed interfaces, so that there is no need for future BSP's to clone the generic part from the year 2008. Ok, this thoughs seems to be wrong. Thanks for your answers Michael > > > > On 2013-04-23 12:45 PM, "Michael Tasche" <community-noreply@qnx.com> wrote: > > >> I would put some debug into the setup_pci_io and setup_pci_mem functions > >> and see what is happening there, as that is where the resources should > >>be > >> allocated. > > > >Yes, I was already there with the gdb. > >Well, I just found the problem: > >In this strange root-complex the class is wired to PCI2PCI-Bridge. > >=> This break condition erroneously stops the traversback through the > >bridges. > >if (dev->ClassCode == host_bridge_class) > > break; > > > >Well, there is one question left. > >During the bugfixing, I looked at several new BSP'S, where the generic > >part of the pci-server was cloned to the actual driver directories > >getting many patches. > >=> We have a generic part from the year 2008 and several patched generic > >parts in some new BSP'S. > >Is there a plan to merge this to a new official generic pci-server? > > > >-Michael > > > >> > >> > >> > >> > >> On 2013-04-23 8:14 AM, "Michael Tasche" <community-noreply@qnx.com> > >>wrote: > >> > >> >> What BSP are you using to base your PCI server on? > >> >"Freescale i.MX6Q Sabre Board for Smart Devices" > >> > > >> >I had to intergrate some knowledge of the last linux driver. > >> >The original imx6x pci driver seems to work only with exact one > >>device. > >> >I attached my actual driver files. > >> > > >> >-Michael > >> > > >> >> > >> >> > >> >> > >> >> > >> >> On 2013-04-23 4:45 AM, "Michael Tasche" <community-noreply@qnx.com> > >> >>wrote: > >> >> > >> >> >Hi all, > >> >> > > >> >> >I am working on a BSP (QNX 6.5.0SP1) for an i.mx6 board. > >> >> >The boot-monitor has no PCI-Support! > >> >> >=> Everything has to be done by the pci-server. > >> >> > > >> >> >There seems to be a problem with the bridge configuration. > >> >> >Attached you will find some logs. (pci-bridges, bus_map, pci-v, > >> >>sloginfo) > >> >> > > >> >> >At the momnet there is only one device attached(bus5/dev0/func0). > >> >> >This device is connected to one port of a 3-port pcie-switch. > >> >> >The upstream-port of this switch is connected to the > >> >>root-complex(i.mx6). > >> >> > > >> >> >The bus-map seems to be NOT initialized correctly (mem_start = 0x0, > >> >> >mem_end = 0x0?). > >> >> > > >> >> >If I try to start the device driver, the pci-server fails, because > >> >> >"pcimemory/Bus0/Bus1/Bus5" has not been created by the pci-server. > >> >>(Look > >> >> >at the last sloginfo) > >> >> > > >> >> >Where is my problem? > >> >> > > >> >> >Thanks in advance > >> >> >Michael > >> >> > > >> >> > > >> >> > > >> >> >_______________________________________________ > >> >> > > >> >> >QNX BSPs > >> >> >http://community.qnx.com/sf/go/post100788 > >> >> >To cancel your subscription to this discussion, please e-mail > >> >> >general-bsp-unsubscribe@community.qnx.com > >> >> > >> > > >> > > >> > > >> > > >> > > >> > > >> >_______________________________________________ > >> > > >> >QNX BSPs > >> >http://community.qnx.com/sf/go/post100797 > >> >To cancel your subscription to this discussion, please e-mail > >> >general-bsp-unsubscribe@community.qnx.com > >> > > > > > > > > > > > > > >_______________________________________________ > > > >QNX BSPs > >http://community.qnx.com/sf/go/post100817 > >To cancel your subscription to this discussion, please e-mail > >general-bsp-unsubscribe@community.qnx.com > Wed, 24 Apr 2013 10:08:42 GMT http://community.qnx.com/sf/go/post100832 Michael Tasche 2013-04-24T10:08:42Z http://community.qnx.com/sf/go/post100818 We have many variants of the server.c code to cater for different platforms, so to answer your question, no, we won't be merging and PCI code. On 2013-04-23 12:45 PM, "Michael Tasche" <community-noreply@qnx.com> wrote: >> I would put some debug into the setup_pci_io and setup_pci_mem functions >> and see what is happening there, as that is where the resources should >>be >> allocated. > >Yes, I was already there with the gdb. >Well, I just found the problem: >In this strange root-complex the class is wired to PCI2PCI-Bridge. >=> This break condition erroneously stops the traversback through the >bridges. >if (dev->ClassCode == host_bridge_class) > break; > >Well, there is one question left. >During the bugfixing, I looked at several new BSP'S, where the generic >part of the pci-server was cloned to the actual driver directories >getting many patches. >=> We have a generic part from the year 2008 and several patched generic >parts in some new BSP'S. >Is there a plan to merge this to a new official generic pci-server? > >-Michael > >> >> >> >> >> On 2013-04-23 8:14 AM, "Michael Tasche" <community-noreply@qnx.com> >>wrote: >> >> >> What BSP are you using to base your PCI server on? >> >"Freescale i.MX6Q Sabre Board for Smart Devices" >> > >> >I had to intergrate some knowledge of the last linux driver. >> >The original imx6x pci driver seems to work only with exact one >>device. >> >I attached my actual driver files. >> > >> >-Michael >> > >> >> >> >> >> >> >> >> >> >> On 2013-04-23 4:45 AM, "Michael Tasche" <community-noreply@qnx.com> >> >>wrote: >> >> >> >> >Hi all, >> >> > >> >> >I am working on a BSP (QNX 6.5.0SP1) for an i.mx6 board. >> >> >The boot-monitor has no PCI-Support! >> >> >=> Everything has to be done by the pci-server. >> >> > >> >> >There seems to be a problem with the bridge configuration. >> >> >Attached you will find some logs. (pci-bridges, bus_map, pci-v, >> >>sloginfo) >> >> > >> >> >At the momnet there is only one device attached(bus5/dev0/func0). >> >> >This device is connected to one port of a 3-port pcie-switch. >> >> >The upstream-port of this switch is connected to the >> >>root-complex(i.mx6). >> >> > >> >> >The bus-map seems to be NOT initialized correctly (mem_start = 0x0, >> >> >mem_end = 0x0?). >> >> > >> >> >If I try to start the device driver, the pci-server fails, because >> >> >"pcimemory/Bus0/Bus1/Bus5" has not been created by the pci-server. >> >>(Look >> >> >at the last sloginfo) >> >> > >> >> >Where is my problem? >> >> > >> >> >Thanks in advance >> >> >Michael >> >> > >> >> > >> >> > >> >> >_______________________________________________ >> >> > >> >> >QNX BSPs >> >> >http://community.qnx.com/sf/go/post100788 >> >> >To cancel your subscription to this discussion, please e-mail >> >> >general-bsp-unsubscribe@community.qnx.com >> >> >> > >> > >> > >> > >> > >> > >> >_______________________________________________ >> > >> >QNX BSPs >> >http://community.qnx.com/sf/go/post100797 >> >To cancel your subscription to this discussion, please e-mail >> >general-bsp-unsubscribe@community.qnx.com >> > > > > > > >_______________________________________________ > >QNX BSPs >http://community.qnx.com/sf/go/post100817 >To cancel your subscription to this discussion, please e-mail >general-bsp-unsubscribe@community.qnx.com Tue, 23 Apr 2013 17:10:07 GMT http://community.qnx.com/sf/go/post100818 Hugh Brown 2013-04-23T17:10:07Z http://community.qnx.com/sf/go/post100817 > I would put some debug into the setup_pci_io and setup_pci_mem functions > and see what is happening there, as that is where the resources should be > allocated. Yes, I was already there with the gdb. Well, I just found the problem: In this strange root-complex the class is wired to PCI2PCI-Bridge. => This break condition erroneously stops the traversback through the bridges. if (dev->ClassCode == host_bridge_class) break; Well, there is one question left. During the bugfixing, I looked at several new BSP'S, where the generic part of the pci-server was cloned to the actual driver directories getting many patches. => We have a generic part from the year 2008 and several patched generic parts in some new BSP'S. Is there a plan to merge this to a new official generic pci-server? -Michael > > > > > On 2013-04-23 8:14 AM, "Michael Tasche" <community-noreply@qnx.com> wrote: > > >> What BSP are you using to base your PCI server on? > >"Freescale i.MX6Q Sabre Board for Smart Devices" > > > >I had to intergrate some knowledge of the last linux driver. > >The original imx6x pci driver seems to work only with exact one device. > >I attached my actual driver files. > > > >-Michael > > > >> > >> > >> > >> > >> On 2013-04-23 4:45 AM, "Michael Tasche" <community-noreply@qnx.com> > >>wrote: > >> > >> >Hi all, > >> > > >> >I am working on a BSP (QNX 6.5.0SP1) for an i.mx6 board. > >> >The boot-monitor has no PCI-Support! > >> >=> Everything has to be done by the pci-server. > >> > > >> >There seems to be a problem with the bridge configuration. > >> >Attached you will find some logs. (pci-bridges, bus_map, pci-v, > >>sloginfo) > >> > > >> >At the momnet there is only one device attached(bus5/dev0/func0). > >> >This device is connected to one port of a 3-port pcie-switch. > >> >The upstream-port of this switch is connected to the > >>root-complex(i.mx6). > >> > > >> >The bus-map seems to be NOT initialized correctly (mem_start = 0x0, > >> >mem_end = 0x0?). > >> > > >> >If I try to start the device driver, the pci-server fails, because > >> >"pcimemory/Bus0/Bus1/Bus5" has not been created by the pci-server. > >>(Look > >> >at the last sloginfo) > >> > > >> >Where is my problem? > >> > > >> >Thanks in advance > >> >Michael > >> > > >> > > >> > > >> >_______________________________________________ > >> > > >> >QNX BSPs > >> >http://community.qnx.com/sf/go/post100788 > >> >To cancel your subscription to this discussion, please e-mail > >> >general-bsp-unsubscribe@community.qnx.com > >> > > > > > > > > > > > > > >_______________________________________________ > > > >QNX BSPs > >http://community.qnx.com/sf/go/post100797 > >To cancel your subscription to this discussion, please e-mail > >general-bsp-unsubscribe@community.qnx.com > Tue, 23 Apr 2013 16:45:13 GMT http://community.qnx.com/sf/go/post100817 Michael Tasche 2013-04-23T16:45:13Z http://community.qnx.com/sf/go/post100801 I would put some debug into the setup_pci_io and setup_pci_mem functions and see what is happening there, as that is where the resources should be allocated. On 2013-04-23 8:14 AM, "Michael Tasche" <community-noreply@qnx.com> wrote: >> What BSP are you using to base your PCI server on? >"Freescale i.MX6Q Sabre Board for Smart Devices" > >I had to intergrate some knowledge of the last linux driver. >The original imx6x pci driver seems to work only with exact one device. >I attached my actual driver files. > >-Michael > >> >> >> >> >> On 2013-04-23 4:45 AM, "Michael Tasche" <community-noreply@qnx.com> >>wrote: >> >> >Hi all, >> > >> >I am working on a BSP (QNX 6.5.0SP1) for an i.mx6 board. >> >The boot-monitor has no PCI-Support! >> >=> Everything has to be done by the pci-server. >> > >> >There seems to be a problem with the bridge configuration. >> >Attached you will find some logs. (pci-bridges, bus_map, pci-v, >>sloginfo) >> > >> >At the momnet there is only one device attached(bus5/dev0/func0). >> >This device is connected to one port of a 3-port pcie-switch. >> >The upstream-port of this switch is connected to the >>root-complex(i.mx6). >> > >> >The bus-map seems to be NOT initialized correctly (mem_start = 0x0, >> >mem_end = 0x0?). >> > >> >If I try to start the device driver, the pci-server fails, because >> >"pcimemory/Bus0/Bus1/Bus5" has not been created by the pci-server. >>(Look >> >at the last sloginfo) >> > >> >Where is my problem? >> > >> >Thanks in advance >> >Michael >> > >> > >> > >> >_______________________________________________ >> > >> >QNX BSPs >> >http://community.qnx.com/sf/go/post100788 >> >To cancel your subscription to this discussion, please e-mail >> >general-bsp-unsubscribe@community.qnx.com >> > > > > > > >_______________________________________________ > >QNX BSPs >http://community.qnx.com/sf/go/post100797 >To cancel your subscription to this discussion, please e-mail >general-bsp-unsubscribe@community.qnx.com Tue, 23 Apr 2013 13:20:49 GMT http://community.qnx.com/sf/go/post100801 Hugh Brown 2013-04-23T13:20:49Z http://community.qnx.com/sf/go/post100797 > What BSP are you using to base your PCI server on? "Freescale i.MX6Q Sabre Board for Smart Devices" I had to intergrate some knowledge of the last linux driver. The original imx6x pci driver seems to work only with exact one device. I attached my actual driver files. -Michael > > > > > On 2013-04-23 4:45 AM, "Michael Tasche" <community-noreply@qnx.com> wrote: > > >Hi all, > > > >I am working on a BSP (QNX 6.5.0SP1) for an i.mx6 board. > >The boot-monitor has no PCI-Support! > >=> Everything has to be done by the pci-server. > > > >There seems to be a problem with the bridge configuration. > >Attached you will find some logs. (pci-bridges, bus_map, pci-v, sloginfo) > > > >At the momnet there is only one device attached(bus5/dev0/func0). > >This device is connected to one port of a 3-port pcie-switch. > >The upstream-port of this switch is connected to the root-complex(i.mx6). > > > >The bus-map seems to be NOT initialized correctly (mem_start = 0x0, > >mem_end = 0x0?). > > > >If I try to start the device driver, the pci-server fails, because > >"pcimemory/Bus0/Bus1/Bus5" has not been created by the pci-server. (Look > >at the last sloginfo) > > > >Where is my problem? > > > >Thanks in advance > >Michael > > > > > > > >_______________________________________________ > > > >QNX BSPs > >http://community.qnx.com/sf/go/post100788 > >To cancel your subscription to this discussion, please e-mail > >general-bsp-unsubscribe@community.qnx.com > Tue, 23 Apr 2013 12:14:11 GMT http://community.qnx.com/sf/go/post100797 Michael Tasche 2013-04-23T12:14:11Z http://community.qnx.com/sf/go/post100796 What BSP are you using to base your PCI server on? On 2013-04-23 4:45 AM, "Michael Tasche" <community-noreply@qnx.com> wrote: >Hi all, > >I am working on a BSP (QNX 6.5.0SP1) for an i.mx6 board. >The boot-monitor has no PCI-Support! >=> Everything has to be done by the pci-server. > >There seems to be a problem with the bridge configuration. >Attached you will find some logs. (pci-bridges, bus_map, pci-v, sloginfo) > >At the momnet there is only one device attached(bus5/dev0/func0). >This device is connected to one port of a 3-port pcie-switch. >The upstream-port of this switch is connected to the root-complex(i.mx6). > >The bus-map seems to be NOT initialized correctly (mem_start = 0x0, >mem_end = 0x0?). > >If I try to start the device driver, the pci-server fails, because >"pcimemory/Bus0/Bus1/Bus5" has not been created by the pci-server. (Look >at the last sloginfo) > >Where is my problem? > >Thanks in advance >Michael > > > >_______________________________________________ > >QNX BSPs >http://community.qnx.com/sf/go/post100788 >To cancel your subscription to this discussion, please e-mail >general-bsp-unsubscribe@community.qnx.com Tue, 23 Apr 2013 11:55:59 GMT http://community.qnx.com/sf/go/post100796 Hugh Brown 2013-04-23T11:55:59Z http://community.qnx.com/sf/go/post100788 Hi all, I am working on a BSP (QNX 6.5.0SP1) for an i.mx6 board. The boot-monitor has no PCI-Support! => Everything has to be done by the pci-server. There seems to be a problem with the bridge configuration. Attached you will find some logs. (pci-bridges, bus_map, pci-v, sloginfo) At the momnet there is only one device attached(bus5/dev0/func0). This device is connected to one port of a 3-port pcie-switch. The upstream-port of this switch is connected to the root-complex(i.mx6). The bus-map seems to be NOT initialized correctly (mem_start = 0x0, mem_end = 0x0?). If I try to start the device driver, the pci-server fails, because "pcimemory/Bus0/Bus1/Bus5" has not been created by the pci-server. (Look at the last sloginfo) Where is my problem? Thanks in advance Michael Tue, 23 Apr 2013 08:45:49 GMT http://community.qnx.com/sf/go/post100788 Michael Tasche 2013-04-23T08:45:49Z http://community.qnx.com/sf/go/post100772 Manuel- Sounds like "wave" doesn't like the format of your file. Use a windows .wav file. Output should look like... # wave /audio/utopia.wav SampleRate = 22050, Channels = 1, SampleBits = 16 Format Signed 16-bit Little Endian Frag Size 882 Total Frags 68 Rate 22050 Voices 1 Mixer Pcm Group [Wave playback channel] Mon, 22 Apr 2013 12:38:48 GMT http://community.qnx.com/sf/go/post100772 Dennis Kellly 2013-04-22T12:38:48Z http://community.qnx.com/sf/go/post100771 Manuel- Wave plays fine to lower jack for me. My /dev/snd looks like this. # ls -Fal /dev/snd total 0 -rw-rw-rw- 1 root root 0 Apr 22 08:29 controlC0 -rw-rw-rw- 1 root root 0 Apr 22 08:29 mixerC0D0 -rw-rw-rw- 1 root root 0 Apr 22 08:29 pcmC0D0c -rw-rw-rw- 1 root root 0 Dec 31 1999 pcmC0D0p -rw-rw-rw- 1 root root 0 Apr 22 08:30 pcmC0D1p -rw-rw-rw- 1 root root 0 Apr 22 08:29 pcmC0D2c -rw-rw-rw- 1 root root 0 Apr 22 08:29 pcmC0D2p -rw-rw-rw- 1 root root 0 Apr 22 08:29 pcmC0D3p lrw-rw-rw- 1 root root 0 Apr 22 08:29 pcmPreferredc@ -> pcmC0 D0c lrw-rw-rw- 1 root root 0 Apr 22 08:29 pcmPreferredp@ -> pcmC0 D1p Started in bootscript as... io-audio -d omap4pdm waitfor /dev/snd/pcmC0D0p Dennis Mon, 22 Apr 2013 12:35:52 GMT http://community.qnx.com/sf/go/post100771 Dennis Kellly 2013-04-22T12:35:52Z http://community.qnx.com/sf/go/post100770 Hello, Using the Panda Board BSP along with our Panda Board ES Rev B2, we're getting no audio out from our board. (I tried playing a PCM file via the `wave` command; the command just outputs "ChechHdr #1: No error", and returns with an error value of 255.) This is an excerpt from our boot-up messages, containing an audio driver info: --- Welcome to QNX Neutrino 6.5.0 SP1 on the Texas Instruments OMAP4430 (ARMv7 Cortex-A9 core) - Panda Board starting I2C driver... Configuring power management chip... TWL6030 ES2.1 Starting McPDM audio driver... Setting OS clock from on-board RTC... ---- After boot-up is complete, I see the following contents in /dev/snd/ : controlC0 pcmC0D0p pcmC0D2p pcmPreferredp mixerC0D0 pcmC0D1p pcmC0D3p pcmC0D0c pcmC0D2c pcmPreferredc The first entry of `sloginfo`reads as follows: --- Time Sev Major Minor Args Jan 01 00:00:01 1 7 0 twl6040_mixer_reset: Automatic power up failed --- Any hints on what could be the issue here, or how to proceed with testing? Cheers Manuel Mon, 22 Apr 2013 12:21:19 GMT http://community.qnx.com/sf/go/post100770 Manuel Kirschner 2013-04-22T12:21:19Z http://community.qnx.com/sf/go/post100753 OK, I've found way to solve it.: from:http://community.qnx.com/sf/discussion/do/listPosts/projects.bsp/discussion.bsp.topc22496 From the BSP's Quick Start Guide: Two patch files are available for the Neutrino 6.5.0 graphics 1. patch-650-2258-CompMgr.tar (http://community.qnx.com/sf/frs/do/viewRelease/projects.graphics/frs.sgx_drivers.650_v7) 2. patch-650-2413-iMX53GPU.tar (http://community.qnx.com/sf/frs/do/viewRelease/projects.graphics/frs.imx51_gpu_driver.imx53_20101115) the GPU files are already included in the BSP source. The composition manager patch (Patch 1) must be downloaded and installed, as it contains files required to build the touchscreen drivers and run hardware accelerated OpenGL applications. Without it the touchscreen drivers will fail to build, and binaries requiring OpenGL ES libraries to be present will not run. Fri, 19 Apr 2013 08:23:36 GMT http://community.qnx.com/sf/go/post100753 Mark He Qinglong 2013-04-19T08:23:36Z http://community.qnx.com/sf/go/post100752 Hi, Did you solve this problem ? I have treated this problem too. After delete the devi driver module it could be compile fine. But when I run the raw file, it would told me: Jan 01 00:01:29 5 9 1 mc34708_comms i2c_write_read failed (code 5, rb ytes 0) Jan 01 00:01:29 2 9 1 mc34708_comms_read_register i2c write read fail ed (code 5) Jan 01 00:01:29 2 6 0 Master send did not terminate Jan 01 00:01:29 2 6 0 Master send NACK So, I'm trying to find a same sign at here. Did you solve this problem ? Fri, 19 Apr 2013 08:01:55 GMT http://community.qnx.com/sf/go/post100752 Mark He Qinglong 2013-04-19T08:01:55Z http://community.qnx.com/sf/go/post100721 Hi, floating point is working ... have a different problem :) --Armin Thu, 18 Apr 2013 09:42:54 GMT http://community.qnx.com/sf/go/post100721 Armin Steinhoff 2013-04-18T09:42:54Z http://community.qnx.com/sf/go/post100700 Hi, I'm neeed some help for the BeagleBone. I#m testing with the newest BSP of the BeagleBone and get a SIGBUS event when I do an assignment between two floating point variables. The code looks like: float x,y=0.3; x = y; I have added the option -Wc,-mfpx=vfp3 w/o success. What's the problem ? Do I miss some compile options ? I'm working with Momentics 4.7 / 6.5 SP1 --Armin Wed, 17 Apr 2013 15:25:40 GMT http://community.qnx.com/sf/go/post100700 Armin Steinhoff 2013-04-17T15:25:40Z http://community.qnx.com/sf/go/post100664 Root cause was wrong part. The part on the Nitrogen6X was discovered to be a PCIMX6S6AVM08AB or Single Core, which has different I/O MUX registers and is not compatible with the QNX BSP. The boards were defective for this application. Tue, 16 Apr 2013 23:30:50 GMT http://community.qnx.com/sf/go/post100664 Erick Roane 2013-04-16T23:30:50Z http://community.qnx.com/sf/go/post100662 I just confirmed with boundary devices today that the issue does not appear on Nitrogen REV2 board with a Quad Core i.MX6. However, the boards I have are Dual Core. So it appears there is some kind of N-core dependent code in the BSP. The Linux image did not have this issue, it appears the QNX BSP does. Anyone have any idea on what would cause some dependency on the number of cores to cause a problem. Tue, 16 Apr 2013 21:39:59 GMT http://community.qnx.com/sf/go/post100662 Erick Roane 2013-04-16T21:39:59Z http://community.qnx.com/sf/go/post100657 Thank you for your help. When I try to install the SP1 from the Korn Shell it fails with numerous errors then fails with a invalid license key (I’m using the 30-day evaluation version). $ qnxsdp-6.5.0SP1-201206270843-nto.sh Sage Software $ qnxsdp-6.5.0SP1-201206270843-nto.sh ./qnxsdp-6.5.0SP1-201206270843-nto.sh: line 3: fullpath: command not found ./qnxsdp-6.5.0SP1-201206270843-nto.sh: line 51: head: command not found ./qnxsdp-6.5.0SP1-201206270843-nto.sh: line 54: test: too many arguments Welcome to the installation of QNX Software Development Platform 6.5.0SP1 Installing QNX Software Development Platform 6.5.0SP1 overwrites components of QNX SDP 6.5.0 without backing anything up. Once installed, the QNX Software Development Platform 6.5.0SP1 cannot be uninstalled. Do you want to continue with the installation (y/n)? [y] y ./qnxsdp-6.5.0SP1-201206270843-nto.sh: line 116: [: version 61 Service Pack 1 (B uild 7601) : integer expression expected ./qnxsdp-6.5.0SP1-201206270843-nto.sh: line 137: more: command not found Do you accept the terms and conditions of this message (y/n)? [n] y ./qnxsdp-6.5.0SP1-201206270843-nto.sh: line 171: tail: command not found ./qnxsdp-6.5.0SP1-201206270843-nto.sh: line 171: head: command not found ./qnxsdp-6.5.0SP1-201206270843-nto.sh: line 171: qinst: command not found ./qnxsdp-6.5.0SP1-201206270843-nto.sh: line 180: tail: command not found ./qnxsdp-6.5.0SP1-201206270843-nto.sh: line 180: head: command not found ./qnxsdp-6.5.0SP1-201206270843-nto.sh: line 180: qinst: command not found ./qnxsdp-6.5.0SP1-201206270843-nto.sh: line 231: tail: command not found gzip: stdin: unexpected end of file tar: Child returned status 1 tar: Exiting with failure status due to previous errors ./qnxsdp-6.5.0SP1-201206270843-nto.sh: line 234: /tmp/instlicsup/qlicflags: No s uch file or directory You have entered an invalid key for this product How can I get SP1 installed on a Windows machine using the evaluation version? Tue, 16 Apr 2013 19:59:50 GMT http://community.qnx.com/sf/go/post100657 David Lafreniere 2013-04-16T19:59:50Z http://community.qnx.com/sf/go/post100642 No, there is no way to support this with the current version. Tue, 16 Apr 2013 14:42:03 GMT http://community.qnx.com/sf/go/post100642 Jim Gilderson 2013-04-16T14:42:03Z http://community.qnx.com/sf/go/post100640 Hi David, Please install the 6.5.0 SP1 patch on your host, then rebuild the IFS. Thanks, Mark On 2013-04-15 6:57 PM, "David Lafreniere" <community-noreply@qnx.com> wrote: >I tried changing the bootcmd U-Boot environment variable to: > >echo Starting QNX...; fatload mmc 0:1 0x10800000 ifs-mx6q-nitrogen.raw; >go 0x10800000 > >Now the board keeps rebooting. I noticed in the output log when A/C is >plugged in outputs this line: > >Reset cause: POR > >The next boot and all subsequent reboots outputs this line: > >Reset cause: WDOG > >So it appears that the watchdog is firing during QNX booting. How can the >watchdog be disabled? > >I've attached a log file of the serial output. > >Thanks! > > > >_______________________________________________ > >QNX BSPs >http://community.qnx.com/sf/go/post100614 >To cancel your subscription to this discussion, please e-mail >general-bsp-unsubscribe@community.qnx.com Tue, 16 Apr 2013 14:11:00 GMT http://community.qnx.com/sf/go/post100640 Mark Wakim 2013-04-16T14:11:00Z http://community.qnx.com/sf/go/post100624 Been running for the last 16 hours with no problems. Something in the service pack solves the issue - now to try and find out where... Tue, 16 Apr 2013 08:08:36 GMT http://community.qnx.com/sf/go/post100624 Chris Bradshaw 2013-04-16T08:08:36Z http://community.qnx.com/sf/go/post100614 I tried changing the bootcmd U-Boot environment variable to: echo Starting QNX...; fatload mmc 0:1 0x10800000 ifs-mx6q-nitrogen.raw; go 0x10800000 Now the board keeps rebooting. I noticed in the output log when A/C is plugged in outputs this line: Reset cause: POR The next boot and all subsequent reboots outputs this line: Reset cause: WDOG So it appears that the watchdog is firing during QNX booting. How can the watchdog be disabled? I've attached a log file of the serial output. Thanks! Mon, 15 Apr 2013 22:57:52 GMT http://community.qnx.com/sf/go/post100614 David Lafreniere 2013-04-15T22:57:52Z http://community.qnx.com/sf/go/post100610 Hi, I am trying to get QNX to boot on my Nitrogen6x evaluation board from Boundary Devices. I have followed the QNX 6.5.0 SP1 BSP for Boundary Devices iMX6 Nitrogen6x Quick Start Guide I execute these commands: # fatload mmc 0:1 0x10800000 ifs-mx6q-nitrogen.raw # go 0x10800000 And the error obtained is: 6x_bootscript not found serial console at 115200, 8N1 details at http://boundarydevices.com/6q_bootscript Now I have copied the 6x_bootscript to the SD card root directory. It still cannot find the file. I also notice that the U-Boot environment variable for bootcmd is: bootcmd=for dtype in sata mmc ; do for disk in 0 1 ; do E{dtype} dev ${disk} ;for fs in fat ext2 ; do ${fs}load ${dtype} ${disk}:1 10008000 /6x_bootscript&& source 10008000 ; done ; done ; done; setenv stdout serial,vga ; echo ; echo 6x_bootscript not found ; echo ; echo serial console at 115200, 8N1 ; echo ; echo details at http://boundarydevices.com/6q_bootscript ; setenv stdout serial Questions: How can I get the the 6x_bootscript to be found? Where should it be copied? Should the bootcmd be changed to something else so that QNX boots automatically? If so, what should the U-Boot bootcmd environment variable be changed to? Thanks for your help! Mon, 15 Apr 2013 20:57:56 GMT http://community.qnx.com/sf/go/post100610 David Lafreniere 2013-04-15T20:57:56Z http://community.qnx.com/sf/go/post100595 > Hi Erick, > > If you're running procnto-smp, it shouldn't matter whether it's a dual-core or > quad-core version of the i.MX6; the startup/kernel code will figure it out > automatically. However, it's possible to over-ride the default, and specify > the number of cores you want active, using the -P option to startup, in the > build file. For example, if you had a quad core i.MX6, but only wanted to run > two cores (or uni-processor, but still using procnto-smp), you could do the > following: > > startup-nitrogen6x -P2 (for dual-core operation) > startup-nitrogen6x -P1 (for single-core operation) > > Regarding your serial console input issue, we don't have any nitrogen6x boards > in-house, although we are expecting one soon for some other development work. > However, I've notified MPC Data (the developer of the BSP), and asked them > to take a look at this thread, to see if they have any ideas what the problem > might be. > > Regards, > > Dave > > Yeah, it does not seem to matter if I boot with -P1 or -P2, issue still persists. Also, I'm not sure if it matters but I'm actually running procnto-smp-instr versus procnto-smp. Again, it does not seem to matter if either one is used, issue still persists. Thanks for notifying the BSP vendor. I'm also interested to know why I cannot use the SATA and Touchscreen drivers, even though I do not use them. I think it has something to do with this being a REV 2 Nitrogen board. As I explained, the QNX FAE said he had no issues running the BSP on REV 1 Nitrogen boards. Mon, 15 Apr 2013 15:46:55 GMT http://community.qnx.com/sf/go/post100595 Erick Roane 2013-04-15T15:46:55Z http://community.qnx.com/sf/go/post100593 Interesting. I've put QNX 6.5.0 SP1 on it, and now i'm having much better luck. No BSP, just 6.5.0 + SP1. Going to run overnight to see if it fails. Mon, 15 Apr 2013 15:37:38 GMT http://community.qnx.com/sf/go/post100593 Chris Bradshaw 2013-04-15T15:37:38Z http://community.qnx.com/sf/go/post100592 > >>>after a few minutes I see Path=0 - FREESCALE USDHC come out. > > Does this mean that most of the output is "delayed"? Maybe the watchdog > printf's are causing the output to be drained eventually (but not be txempty > interrupt)? > > Coupled with no input (no rx intr), perhaps the IRQ may be different for your > board? The output string " Path=0 - FREESCALE USDHC" comes out regardless of the watchdog printfs. It does take a minute or two. Recently, I put in some debug code in the devc-sermx1 thread to print whenever an rx interrupt occurs. I have not seen any prints so I can only assume the interrupt vector is not set up correctly. But again, I'm using the same default BSP options devc-sermx1 -u 2 -e -F -S -c80000000 0x021E8000,59 However, since this is a REV 2 Nitrogen board I'm suspicious something has changed. The FAE I spoke with last week told me the BSP image works on REV 1 Nitrogen boards. Mon, 15 Apr 2013 15:28:31 GMT http://community.qnx.com/sf/go/post100592 Erick Roane 2013-04-15T15:28:31Z http://community.qnx.com/sf/go/post100573 >>>after a few minutes I see Path=0 - FREESCALE USDHC come out. Does this mean that most of the output is "delayed"? Maybe the watchdog printf's are causing the output to be drained eventually (but not be txempty interrupt)? Coupled with no input (no rx intr), perhaps the IRQ may be different for your board? Mon, 15 Apr 2013 12:52:16 GMT http://community.qnx.com/sf/go/post100573 Dennis Kellly 2013-04-15T12:52:16Z http://community.qnx.com/sf/go/post100571 Hi Erick, If you're running procnto-smp, it shouldn't matter whether it's a dual-core or quad-core version of the i.MX6; the startup/kernel code will figure it out automatically. However, it's possible to over-ride the default, and specify the number of cores you want active, using the -P option to startup, in the build file. For example, if you had a quad core i.MX6, but only wanted to run two cores (or uni-processor, but still using procnto-smp), you could do the following: startup-nitrogen6x -P2 (for dual-core operation) startup-nitrogen6x -P1 (for single-core operation) Regarding your serial console input issue, we don't have any nitrogen6x boards in-house, although we are expecting one soon for some other development work. However, I've notified MPC Data (the developer of the BSP), and asked them to take a look at this thread, to see if they have any ideas what the problem might be. Regards, Dave Mon, 15 Apr 2013 12:33:48 GMT http://community.qnx.com/sf/go/post100571 David Green 2013-04-15T12:33:48Z http://community.qnx.com/sf/go/post100545 Would it matter that my Nitrogen6X boards are Dual Core versus Quad? Not sure where to specify this in the BSP build. Fri, 12 Apr 2013 21:58:58 GMT http://community.qnx.com/sf/go/post100545 Erick Roane 2013-04-12T21:58:58Z http://community.qnx.com/sf/go/post100540 I don't think so, otherwise I would see any output right. See below, even after a few minutes I see Path=0 - FREESCALE USDHC come out. Also, remember I said I was able to print from the wdtkick and see the output. I think it has something to do with the UART driver or ksch setup. Welcome to QNX Neutrino 6.5.0 SP1 on the i.mx6Q Nitrogen (ARM Cortex-A9 MPCore) Starting watchdog... Starting I2C1,2,3 driver (/dev/i2c1,2,3)... Starting SD3 (microSD) memory card driver... Starting SD4 (microSD) memory card driver... Path=0 - FREESCALE USDHC (devf t1::f3s_flash_probe:285) Unable to properly identify any flash devices Starting USB host1 and OTG driver (operating in host mode) Launching devb-umass... Starting Ethernet driver Starting Shell # Path=0 - FREESCALE USDHC > Could be the -c (clock) option to devc-sermx1 - likely driven be differing > clock rates between the two boards. Fri, 12 Apr 2013 20:02:47 GMT http://community.qnx.com/sf/go/post100540 Erick Roane 2013-04-12T20:02:47Z http://community.qnx.com/sf/go/post100538 Could be the -c (clock) option to devc-sermx1 - likely driven be differing clock rates between the two boards. Fri, 12 Apr 2013 19:52:54 GMT http://community.qnx.com/sf/go/post100538 Dennis Kellly 2013-04-12T19:52:54Z http://community.qnx.com/sf/go/post100537 Yeah, I tried software flow control enable/disabled with both Xon/Xoff and None settings in Tera Term Pro and got no results. I also confirmed the Linux BSP works just fine. I happened to have another Nitrogen board as well and the issue still exists for QNX. A colleague of mine is using SABRE lite it has the same devc-sermx1 options as Nitrogen and they have no issues. It works perfectly. I guess I have no choice but to start debugging the driver. Unless you have any recommendations. Fri, 12 Apr 2013 19:49:38 GMT http://community.qnx.com/sf/go/post100537 Erick Roane 2013-04-12T19:49:38Z http://community.qnx.com/sf/go/post100534 I would still try setting Teraterm's flow control to Xon/Xoff, just to be sure. ------------------------------------- Dave Green QNX Software Systems Limited dgreen@qnx.com On 13-04-12 2:20 PM, "Erick Roane" <community-noreply@qnx.com> wrote: >Thanks David, > >Yes, agreed, just trying to see if someone has used the same terminal >emulator. Anyhow the serial port is setup for no hardware or software >flow control from the build script... > >devc-sermx1 -u 2 -e -F -S -c80000000 0x021E8000,59 >waitfor /dev/ser2 4 >reopen /dev/ser2 > >And I see all the normal display messages, it just does not respond on >the command line. > >Erick > > > > > >_______________________________________________ > >QNX BSPs >http://community.qnx.com/sf/go/post100533 >To cancel your subscription to this discussion, please e-mail >general-bsp-unsubscribe@community.qnx.com Fri, 12 Apr 2013 18:38:50 GMT http://community.qnx.com/sf/go/post100534 David Green 2013-04-12T18:38:50Z http://community.qnx.com/sf/go/post100533 Thanks David, Yes, agreed, just trying to see if someone has used the same terminal emulator. Anyhow the serial port is setup for no hardware or software flow control from the build script... devc-sermx1 -u 2 -e -F -S -c80000000 0x021E8000,59 waitfor /dev/ser2 4 reopen /dev/ser2 And I see all the normal display messages, it just does not respond on the command line. Erick Fri, 12 Apr 2013 18:20:50 GMT http://community.qnx.com/sf/go/post100533 Erick Roane 2013-04-12T18:20:50Z http://community.qnx.com/sf/go/post100532 Problem solved. The daisy-chain was not set properly to get response back to controller. Fri, 12 Apr 2013 17:33:56 GMT http://community.qnx.com/sf/go/post100532 Devan Lippman 2013-04-12T17:33:56Z http://community.qnx.com/sf/go/post100525 It's not the shell, it's the serial driver on the target. If the QNX devc-sermx1 driver starts with software or hardware flow control enabled, then yes, the flow control on the host side must match. ------------------------- Dave Green QNX Software Systems Limited dgreen@qnx.com On 13-04-12 10:25 AM, "Erick Roane" <community-noreply@qnx.com> wrote: >I'm using Tera Term with the same 115200 baud rate, 8-bit, 1 stop bit, >and no flow control. This is the same as U-boot, which works just fine >with my terminal settings. > >So are you saying the terminal settings for the QNX ksh are different >than U-boot? > > > >_______________________________________________ > >QNX BSPs >http://community.qnx.com/sf/go/post100523 >To cancel your subscription to this discussion, please e-mail >general-bsp-unsubscribe@community.qnx.com Fri, 12 Apr 2013 14:57:28 GMT http://community.qnx.com/sf/go/post100525 David Green 2013-04-12T14:57:28Z http://community.qnx.com/sf/go/post100523 I'm using Tera Term with the same 115200 baud rate, 8-bit, 1 stop bit, and no flow control. This is the same as U-boot, which works just fine with my terminal settings. So are you saying the terminal settings for the QNX ksh are different than U-boot? Fri, 12 Apr 2013 14:25:52 GMT http://community.qnx.com/sf/go/post100523 Erick Roane 2013-04-12T14:25:52Z http://community.qnx.com/sf/go/post100518 Hello, What host environment and terminal program are you using to communicate with the Nitrogen6x board? Often when this sort of behaviour is seen, it's due to the serial flow control settings on the host side. Try experimenting with hardware flow control, Xon/Xoff flow control, or no flow control on the host side, and see if that gets your console input working. Fri, 12 Apr 2013 13:35:11 GMT http://community.qnx.com/sf/go/post100518 David Green 2013-04-12T13:35:11Z http://community.qnx.com/sf/go/post100515 Just tried with 2 - 5 times. No failures. Tried with 10, on second go it failed the same way. Fri, 12 Apr 2013 11:59:55 GMT http://community.qnx.com/sf/go/post100515 Chris Bradshaw 2013-04-12T11:59:55Z http://community.qnx.com/sf/go/post100512 Does the crash happen with a smaller number of processes? 10? 2? -----Original Message----- From: Chris Bradshaw [mailto:community-noreply@qnx.com] Sent: Friday, April 12, 2013 7:19 AM To: general-bsp Subject: Re: RE: Vortex86Dx ICOP VDX-6356 and QNX 6.5.0 Hi, Yes, I've tried all the boot images provided with the standard install (smp, dma, other). They all behave the same. Chris _______________________________________________ QNX BSPs http://community.qnx.com/sf/go/post100511 To cancel your subscription to this discussion, please e-mail general-bsp-unsubscribe@community.qnx.com Fri, 12 Apr 2013 11:25:36 GMT http://community.qnx.com/sf/go/post100512 Dennis Kellly 2013-04-12T11:25:36Z http://community.qnx.com/sf/go/post100511 Hi, Yes, I've tried all the boot images provided with the standard install (smp, dma, other). They all behave the same. Chris Fri, 12 Apr 2013 11:19:06 GMT http://community.qnx.com/sf/go/post100511 Chris Bradshaw 2013-04-12T11:19:06Z http://community.qnx.com/sf/go/post100510 Have you tried building/running without the "smp" kernel? ...seems a poor choice for this hardware. -----Original Message----- From: Chris Bradshaw [mailto:community-noreply@qnx.com] Sent: Friday, April 12, 2013 6:18 AM To: general-bsp Subject: Re: Vortex86Dx ICOP VDX-6356 and QNX 6.5.0 Here is the "really simple" program I'm running to cause this failure. I've had it reviewed and we can't see any problem with it. It is called from the command line (press shutdown after getting to the login screen in photon - "Exit to Text Mode"). Call it with; ./NumPrint x y > dev/null & where x is number of processes to start (20) y is the number to count up to (1000000) _______________________________________________ QNX BSPs http://community.qnx.com/sf/go/post100509 To cancel your subscription to this discussion, please e-mail general-bsp-unsubscribe@community.qnx.com Fri, 12 Apr 2013 11:15:41 GMT http://community.qnx.com/sf/go/post100510 Dennis Kellly 2013-04-12T11:15:41Z http://community.qnx.com/sf/go/post100509 Here is the "really simple" program I'm running to cause this failure. I've had it reviewed and we can't see any problem with it. It is called from the command line (press shutdown after getting to the login screen in photon - "Exit to Text Mode"). Call it with; ./NumPrint x y > dev/null & where x is number of processes to start (20) y is the number to count up to (1000000) Fri, 12 Apr 2013 10:17:57 GMT http://community.qnx.com/sf/go/post100509 Chris Bradshaw 2013-04-12T10:17:57Z http://community.qnx.com/sf/go/post100508 Hi All, I'm currently having trouble with OS stability when using this X86 BIOS compatible card. (http://www.icoptech.com/pddetail.aspx?id=138&pid=4) The basics are this; I have a very simple program that spawns 20 further processes. Each of these processes print the numbers 1 to 1000000 to the console and then closes. On the command line, the console is redirected to /dev/null. My problem is - I believe the kernel is crashing with a Segmentation Fault S/C/F 11/1/11 (see screenshot attached). The reason I've raised this in the BSP forum is; The manufacturer provides a BSP but it is for QNX 6.3.2. 1. I can build this BSP with 2 minor code changes, but I dont know what to do with it. 2. Why would the BSP improve things here. Isn't the BSP just a set of drivers for peripherals - and if drivers aren't found, then the peripheral isn't available? 3. Has anyone else tried this processor perhaps with this board? I have tried another card (http://www.diamondsystems.com/products/helios) with the SAME RESULT. The output from the BSP is a set of binaries and libraries; startup-bios, startup-bios-32, libStartup-64.a, libStartup.a, pci-bios, devf-generic, devc-ser8250, devc-tser8250. Some of these sound pretty critical to the system - are they? I'm unsure which direction to go down. Any help much appreciated. Chris Fri, 12 Apr 2013 10:13:46 GMT http://community.qnx.com/sf/go/post100508 Chris Bradshaw 2013-04-12T10:13:46Z http://community.qnx.com/sf/go/post100503 Downloaded the Nitrogen6X BSP and successfully built it in Momentics 6.5.0 (SP1). However, when I booted it hung and was reseting via the watchdog. After commenting out SATA and Touchscreen features, it was able to successfully boot. However, now the korn shell is unresponsive. I test the UART lines and the host is actively sending data. But the system is just silent on the other end. To make sure it wasn't completely out to lunch, I put in a printf where the watchdog was being petted and it was successfully printing out on the shell console. However, it is still unresponsive to input. Keep in mind, this is the out of the box BSP so I'm assuming someone else could reproduce this issue easily? Is there something I'm missing here? Thanks! Fri, 12 Apr 2013 04:48:58 GMT http://community.qnx.com/sf/go/post100503 Erick Roane 2013-04-12T04:48:58Z http://community.qnx.com/sf/go/post100458 Michael, how come this startup-apic is only 140+ Kb whereas the one included in Momentics is about 1MB? Am I missing something? Thanks, Giovanni Wed, 10 Apr 2013 22:04:52 GMT http://community.qnx.com/sf/go/post100458 Giovanni Andrea Conte 2013-04-10T22:04:52Z http://community.qnx.com/sf/go/post100443 I apologize if this is the wrong board to post this question to, but I'm having trouble rotating the display of our CAR2 image. I've tried the screen_rotation command but had no luck. The online directory also mentioned changing the window properties in "graphics.conf" with the command, rotation = 90. I found five "graphics.conf" files on the image and they are read-only. Am I on the right track, and if so how do I alter the files? Wed, 10 Apr 2013 16:17:21 GMT http://community.qnx.com/sf/go/post100443 Nick Skadberg 2013-04-10T16:17:21Z http://community.qnx.com/sf/go/post100434 The cnfg_bridge function is there to allow the low-level code to perform any bridge configuration (if necessary) and to return the address to pcie extended configuration space if applicable. We don't have any documentation on the PCI server code, but you could download one of our BSPs as a reference, from our web site. I am not at all familiar with the hardware that you are using, so I don't know what PCI setup is necessary to get it working. On 2013-04-09 7:08 PM, "Preetham Chandrian" <community-noreply@qnx.com> wrote: >Hi, > >I programmed the root complex and I see that the PCI device configuration >manager make call to configure the bridge.Could you please tell me the >purpose of int (*cnfg_bridge)( void *hdl, uint32_t bus, uint32_t devfunc, >pci_bus_t *pbus ) function? Is there any documentation on pdrvr_entry_t >and pci_bus_t? > >I am still getting the same error. I have attached the logs. Could you >tell me where I am going wrong? > >Thanks, >Preetham > > > >_______________________________________________ > >QNX BSPs >http://community.qnx.com/sf/go/post100418 >To cancel your subscription to this discussion, please e-mail >general-bsp-unsubscribe@community.qnx.com Wed, 10 Apr 2013 11:55:51 GMT http://community.qnx.com/sf/go/post100434 Hugh Brown 2013-04-10T11:55:51Z http://community.qnx.com/sf/go/post100418 Hi, I programmed the root complex and I see that the PCI device configuration manager make call to configure the bridge.Could you please tell me the purpose of int (*cnfg_bridge)( void *hdl, uint32_t bus, uint32_t devfunc, pci_bus_t *pbus ) function? Is there any documentation on pdrvr_entry_t and pci_bus_t? I am still getting the same error. I have attached the logs. Could you tell me where I am going wrong? Thanks, Preetham Tue, 09 Apr 2013 23:08:38 GMT http://community.qnx.com/sf/go/post100418 Preetham Chandrian 2013-04-09T23:08:38Z http://community.qnx.com/sf/go/post100396 On non-x86 systems the memory and I/O are assigned by the low-level PCI code (platform specific) using the rsrcdbmgr function calls. Yes, you must also program these values into the root complex so that it knows which addresses are PCI memory and I/O. On 2013-04-08 6:14 PM, "Preetham Chandrian" <community-noreply@qnx.com> wrote: >Could you please explain me how the I/O and memory is allocated. I see >that in PCI device configuration manager(server.c) it uses >rsrcdbmgr_attach to reserve resources. I have done a rsrcdbmgr_create >for the RSRCDBMGR_PCI_MEMORY and RSRCDBMGR_IO_PORT resources, memory for >both are allocated using >mmap( 0,size,PROT_READ|PROT_WRITE|PROT_NOCACHE,MAP_PHYS|MAP_ANON,NOFD,0) >and aligned to 1MB boundary. Is this the correct way of reserving memory? >DO I need to handle the I/O memory specially? > >Slog for memory allocation > >Jan 01 00:00:09 5 17 0 Low memory CPU f700000 - PCI f700000 >Jan 01 00:00:09 5 17 0 High memory CPU fbfffff - PCI fbfffff >Jan 01 00:00:09 5 17 0 reserve_resource: Start f700000 - End >fbfffff - Name pcimemory/Bus0 >Jan 01 00:00:09 5 17 0 Low port CPU fe60000 - PCI 0 >Jan 01 00:00:09 5 17 0 High port CPU fe60ffe - PCI fff >Jan 01 00:00:09 5 17 0 reserve_resource: Start fe60000 - End >fe60fff - Name io/Bus0 > > > >I understand that for end point memory and I/O are allocated through >pci_attach_device(). For the root complex do I need to program the memory >base, prefetchable memory base, I/O and BAR in the attach of >pdrvr_entry_t? > >Thanks, >Preetham > > > >_______________________________________________ > >QNX BSPs >http://community.qnx.com/sf/go/post100388 >To cancel your subscription to this discussion, please e-mail >general-bsp-unsubscribe@community.qnx.com Tue, 09 Apr 2013 11:39:01 GMT http://community.qnx.com/sf/go/post100396 Hugh Brown 2013-04-09T11:39:01Z http://community.qnx.com/sf/go/post100388 Could you please explain me how the I/O and memory is allocated. I see that in PCI device configuration manager(server.c) it uses rsrcdbmgr_attach to reserve resources. I have done a rsrcdbmgr_create for the RSRCDBMGR_PCI_MEMORY and RSRCDBMGR_IO_PORT resources, memory for both are allocated using mmap( 0,size,PROT_READ|PROT_WRITE|PROT_NOCACHE,MAP_PHYS|MAP_ANON,NOFD,0) and aligned to 1MB boundary. Is this the correct way of reserving memory? DO I need to handle the I/O memory specially? Slog for memory allocation Jan 01 00:00:09 5 17 0 Low memory CPU f700000 - PCI f700000 Jan 01 00:00:09 5 17 0 High memory CPU fbfffff - PCI fbfffff Jan 01 00:00:09 5 17 0 reserve_resource: Start f700000 - End fbfffff - Name pcimemory/Bus0 Jan 01 00:00:09 5 17 0 Low port CPU fe60000 - PCI 0 Jan 01 00:00:09 5 17 0 High port CPU fe60ffe - PCI fff Jan 01 00:00:09 5 17 0 reserve_resource: Start fe60000 - End fe60fff - Name io/Bus0 I understand that for end point memory and I/O are allocated through pci_attach_device(). For the root complex do I need to program the memory base, prefetchable memory base, I/O and BAR in the attach of pdrvr_entry_t? Thanks, Preetham Mon, 08 Apr 2013 22:14:01 GMT http://community.qnx.com/sf/go/post100388 Preetham Chandrian 2013-04-08T22:14:01Z http://community.qnx.com/sf/go/post100367 The memory and I/O will be enabled when the driver performs a pci_attach_device() function. It looks as though you might have a PCI bus problem due to the errors in your output. On 2013-04-05 11:09 AM, "Preetham Chandrian" <community-noreply@qnx.com> wrote: >Thanks for the response. > >I am using QNX 6.5.0 SP1. The devnp-e1000.so is under proc/boot and I >downloaded it from >http://community.qnx.com/sf/go/projects.bsp/frs.network_driver_updates. > >From the pci -vvvv output I noticed that memory and I/O access were not >enabled so I an enabling them and configuring the BAR register in my >(*attach)( char *options, void **hdl ) driver callback. Is this the >correct way of doing it?? > >Even after these changes I get the same error. I have attached the pci >-vvvv output > > > >_______________________________________________ > >QNX BSPs >http://community.qnx.com/sf/go/post100335 >To cancel your subscription to this discussion, please e-mail >general-bsp-unsubscribe@community.qnx.com Mon, 08 Apr 2013 11:33:22 GMT http://community.qnx.com/sf/go/post100367 Hugh Brown 2013-04-08T11:33:22Z http://community.qnx.com/sf/go/post100355 Hi, All I am a newbie of QNX. I have a AM335X_SK Board Version 1.0A, I download the BSP and prebuilt images to run qnx on AM335X_SK with images stored in SDCard. After about one minute, the board finished booting, but I can see nothing on LCD and nothing happened when I touch the touchscreen. I check the serial console, the console works well. I want to know why this happen, how should I do if I want to see the desktop on LCD and works with touchscreen. Sun, 07 Apr 2013 01:16:44 GMT http://community.qnx.com/sf/go/post100355 stephen zhang 2013-04-07T01:16:44Z http://community.qnx.com/sf/go/post100335 Thanks for the response. I am using QNX 6.5.0 SP1. The devnp-e1000.so is under proc/boot and I downloaded it from http://community.qnx.com/sf/go/projects.bsp/frs.network_driver_updates. From the pci -vvvv output I noticed that memory and I/O access were not enabled so I an enabling them and configuring the BAR register in my (*attach)( char *options, void **hdl ) driver callback. Is this the correct way of doing it?? Even after these changes I get the same error. I have attached the pci -vvvv output Fri, 05 Apr 2013 15:09:58 GMT http://community.qnx.com/sf/go/post100335 Preetham Chandrian 2013-04-05T15:09:58Z http://community.qnx.com/sf/go/post100331 Hi Ivan, Yes, spi-master is the resource manager used to load the board (or SoC) specific SPI driver. libspi-master.a is the library containing the various SPI related functions that application level code can call into. libspi.a is an older SPI library, which was deprecated in favour of the spi-master framework, but was still included in the source archive, since the original customer who requested the source archive had used it in legacy SPI code. However, it's not needed for current SPI drivers; spi-master, and the SoC-specific SPI DLL are all that's needed for the SPI driver itself, and libspi-master.a is used for the application code to perform various SPI-based operations. Hope this helps, Dave Fri, 05 Apr 2013 12:43:38 GMT http://community.qnx.com/sf/go/post100331 David Green 2013-04-05T12:43:38Z http://community.qnx.com/sf/go/post100323 First of all 1. What qnx version you use????????? 2. Is the file devnp-e1000.so realy exist in /lib/dll directory??????????????? Fri, 05 Apr 2013 02:59:19 GMT http://community.qnx.com/sf/go/post100323 Oleg Gopov 2013-04-05T02:59:19Z http://community.qnx.com/sf/go/post100314 Hi, I am having trouble detecting the intel 82572EI Gigabit Ethernet Controller via PCI express on a ARMleV5 board. I have implemented configuration register read,write and functions in pdrvr_entry_t structure. I have attached the output of pci -vvvv and the log when I run the command io-pkt-v4-hc -vvvvvv -ptcpip stacksize=8192 -de1000 verbose=4 Can anyone tell me what I am doing wrong here? Thanks Preetham Thu, 04 Apr 2013 18:28:31 GMT http://community.qnx.com/sf/go/post100314 Preetham Chandrian 2013-04-04T18:28:31Z http://community.qnx.com/sf/go/post100307 Hello, I'm trying to use the devb-mmcsd-3dsmx35 on i.MX25. There are posts on the foundry about others having success here but those conversations appear to have run dry. I believe to have made the necessary changes but, when I start the driver, the controller is reporting command timeouts during MMCSD_STATE_IDENT. Capturing the trace with a protocol analyzer appears to show the response is present and no errors are flagged. Has anyone had success here? Thanks, Devan Steps to reproduce: - Copy ./src/hardware/devb from iMX35 BSP to iMX25 BSP - Change addresses for iMX25 eSDHC-2 (sim_mx.h) #define MX35_SDC_BASE 0x53FB8000 #define MX35_SDC_SIZE 0x100 #define MX35_SDC_IRQ 8 - Enable clocks at boot: MX25_CCM_CGCR0 |= 0x40010 MX25_CCM_CGCR1 |= 0x4000 - Configure CMUX at boot: IOMUXC_SW_PAD_CTL_GRP_DVS_CSI = 0 IOMUXC_SW_MUX_CTL_PAD_CSI_MCLK = 0x12 IOMUXC_SW_MUX_CTL_PAD_CSI_VSYNC= 0x12 IOMUXC_SW_MUX_CTL_PAD_CSI_HSYNC= 0x12 IOMUXC_SW_MUX_CTL_PAD_CSI_PIXCLK= 0x12 IOMUXC_SW_MUX_CTL_PAD_CSI_D7= 0x12 IOMUXC_SW_MUX_CTL_PAD_CSI_D6= 0x12 IOMUXC_SW_PAD_CTL_PAD_CSI_MCLK = 0xF1 IOMUXC_SW_PAD_CTL_PAD_CSI_VSYNC= 0xF1 IOMUXC_SW_PAD_CTL_PAD_CSI_HSYNC = 0xF1 IOMUXC_SW_PAD_CTL_PAD_CSI_PIXCLK= 0xF1 IOMUXC_SW_PAD_CTL_PAD_CSI_D7= 0xF1 IOMUXC_SW_PAD_CTL_PAD_CSI_D6= 0xF1 - Run driver from shell (devb-mmcsd-3dsmx35) Thu, 04 Apr 2013 15:32:19 GMT http://community.qnx.com/sf/go/post100307 Devan Lippman 2013-04-04T15:32:19Z http://community.qnx.com/sf/go/post100289 I'm receiving the above during boot from a flash card (SATA). The buiild is more or less a standard os.build - but using devb-ahci in stead of devb-eide (QNX 6.5.0 SP1). Any suggestions? Wed, 03 Apr 2013 13:27:43 GMT http://community.qnx.com/sf/go/post100289 Per Kristoffersen 2013-04-03T13:27:43Z http://community.qnx.com/sf/go/post100263 > Hi > > After some deeper investigations I got it running. It was a problem with the > IOMUX of the iMX. After setting up the stuff in the IOMUX registers the iMX35 > SD driver runs now on iMX25 also. > > Matthias Hi Matthias, Can you provide source or patch for you changes? Thanks, Devan Tue, 02 Apr 2013 13:53:23 GMT http://community.qnx.com/sf/go/post100263 Devan Lippman 2013-04-02T13:53:23Z http://community.qnx.com/sf/go/post100247 Hello everyone. I am able to successfully run the vsync and other 3D application on QNX with i.MX6 platform. These applications runs pretty fine. Now i need to demonstrate the dual display support. I.MX6 has two IPUs, and single IPU supports dual display. Please let me know the configuration and settings needed for dual display support. Whether dual display can be supported on QNX Nuetrino 6.5.0? I just need to display two independant content on two displays. Please provide the support. Mon, 01 Apr 2013 06:11:58 GMT http://community.qnx.com/sf/go/post100247 Ashfaque Ahamed 2013-04-01T06:11:58Z http://community.qnx.com/sf/go/post100242 Hello everyone. I am developing Nuetrino graphics driver for i.MX6/SABRELite platform. For LCD display verification im running the vsync application. When i run the application, it displays blue and then yellow color. Does it indicate that LCD driver is not configured or working properly? What should be the outcome on LCD running vsync? What other methods are available to test LCD? Also where can i get the source code of the vsync? All the .config files i had configured correctly as per my information. Thanks in advance. Regards, Ashfaque Fri, 29 Mar 2013 15:09:05 GMT http://community.qnx.com/sf/go/post100242 Ashfaque Ahamed 2013-03-29T15:09:05Z http://community.qnx.com/sf/go/post100235 Hey, Dave, thanks a lot. Can you answer a few questions, please? 1. There is a tool in the BSP called spi-master. As far as I understand, this tool is used to initialize the SPI driver. There is also a library that offers the high level SPI API and described in the docs (and included in your source code) which is also called spi-master. Do I understand correctly that these are two completely different things that just happen to be named identically or is there a reason for them being named the same? 2. What is libspi.a? 3. Which is the proper way to reference the library from my app? Include it in the BSP, build along with the BSP and reference it inside the BST structure? Keep it in the QNX650 folder? Again, thanks for getting back at me. > Hello, > > I have posted an experimental archive containing the SPI library and sample > driver source code, along with a Readme for building the source, here: > > http://community.qnx.com/sf/wiki/do/viewPage/projects.bsp/wiki/ > ExperimentalDriversAndUtilities?_message=1364476005299 > > Regards, > > Dave Thu, 28 Mar 2013 22:11:01 GMT http://community.qnx.com/sf/go/post100235 Ivan Tarapov 2013-03-28T22:11:01Z http://community.qnx.com/sf/go/post100230 Hello everyone, Im porting the graphics driver to i.MX6 from previous i.MX51. I have done all register mapping and configuration. Included io-display with my build file. Build file is attached for reference. When i run vsync application, im getting below pints and board is being restarted without any display on LCD. Please let me know what could be the issue? I just want to display some images or bitmaps on LCD. # vsync Display Mode Init----->>> filename /etc/system/config/imx51.conf iMX6 imx51_irq_setup-->imx51_irq_setup<--1 Reset IPU 2 3 Waiting for Reset 4 DMFC_DP_CHAN 0x9290 Diplay mod Init--- imx51_get_modelist--> imx51_get_modelist<-- imx51_get_modeinfo: mode 16--> imx51_get_modeinfo<-- imx51_get_modeinfo: mode 24--> 24 Bit Pixel Format imx51_get_modeinfo<-- imx51_set_mode: mode 24-> imx51_set_mode(): xres=800 yres=480 refresh=62 output_fmt=16 di_sel=0 display_type=2 yuv_layer=1 Output Format:RGB565 mode 1 imx51->di_sel 0 Mode 2: div 32 Mode 3: clkdown = 2, clkup = 0 Mode 4: div 2 Mode 5: HSYNC Mode 6: VSYNC Mode 7: DW+DC Mode 8: DW+DC Mode 9: DW+DC Mode 999+++ Mode 9888+++ Mode 10 Mode 11 Mode 12 imx51_layer_reset--> imx51_layer_set_source_viewport--> dispno = 0 layer_idx = 0 x1 = 0 y1 = 0 x2 = 799 y2 = 479 imx51_layer_set_source_viewport<-- imx51_layer_set_dest_viewport--> dispno = 0 layer_idx = 0 x1 = 0 y1 = 0 x2 = 799 y2 = 479 imx51_layer_set_dest_viewport<-- imx51_layer_reset<-- imx51_layer_reset--> imx51_layer_reset<-- Mode 13 imx51_set_mode<- imx51_layer_query--> layer_idx = 0 fmt_idx = 0 dispno = 0 imx51_layer_query<-- imx51_layer_query--> layer_idx = 1 fmt_idx = 0 dispno = 0 imx51_layer_query<-- imx51_layer_query--> layer_idx = 2 fmt_idx = 0 dispno = 0 imx51_mem_init--> imx51_mem_reset--> imx51_mem_fini--> imx51_mem_fini<-- imx51_mem_init--> imx51_query_apertures--> devg_get_miscfuncs--> devg_get_contextfuncs--> Number of displays: 1 Display 0: 800X480, refresh = 60Hz Number of layers: 2 imx51_layer_reset--> imx51_layer_set_source_viewport--> dispno = 0 layer_idx = 0 x1 = 0 y1 = 0 x2 = 799 y2 = 479 imx51_layer_set_source_viewport<-- imx51_layer_set_dest_viewport--> dispno = 0 layer_idx = 0 x1 = 0 y1 = 0 x2 = 799 y2 = 479 imx51_layer_set_dest_viewport<-- imx51_layer_reset<-- imx51_layer_query--> layer_idx = 0 fmt_idx = 0 dispno = 0 imx51_layer_query<-- imx51_alloc_layer_surface:width 800,height 480, format 4, surface_index 0, nlayers 1--> imx51_alloc_layer_surface<-- layer_format_to_surface_format--> SURFACE FORMAT ARGB8888 imx51_alloc_surface:width 800,height 480--> imx51_get_alloc_layer_info--> imx51_get_alloc_layer_info<-- layer_format_to_surface_format--> SURFACE FORMAT ARGB8888 imx51_get_alloc_info:width 800,height 480 --> SURFACE FORMAT ARGB8888 imx51_get_alloc_info<-- devg_get_corefuncs: pixel_format 536870917--> imx51_alloc_layer_surface:width 800,height 480, format 4, surface_index 0, nlayers 1--> imx51_alloc_layer_surface<-- layer_format_to_surface_format--> SURFACE FORMAT ARGB8888 imx51_alloc_surface:width 800,height 480 --> imx51_get_alloc_layer_info--> imx51_get_alloc_layer_info<-- layer_format_to_surface_format--> SURFACE FORMAT ARGB8888 imx51_get_alloc_info:width 800,height 480 --> SURFACE FORMAT ARGB8888 imx51_get_alloc_info<-- imx51_layer_enable--> layer_idx = 0 imx51_layer_set_surface--> surf->paddr: 4010000 Shutdown[0,3] S/C/F=0/0/0 C/D=fe0206a4/fe0a1040 state(3000001)= 1 QNX Version 6.5.0 Release 2012/06/20-13:49:13EDT [0]PID-TID=1-1? P/T FL=00019001/08000000 "proc/boot/procnto-smp-instr" [0]ASPACE PID=16400 PF=00401010 "proc/boot/io-display" [1]PID-TID=1-2? P/T FL=00019001/08000000 "proc/boot/procnto-smp-instr" [1]ASPACE PID=8 PF=00401010 "proc/boot/devb-mmcsd-mx6q-sabrelite" [2]PID-TID=1-3? P/T FL=00019001/08000000 "proc/boot/procnto-smp-instr" [2]ASPACE PID=16396 PF=00401010 "proc/boot/io-pkt-v4" [3]PID-TID=1-4? P/T FL=00019001/08000000 "proc/boot/procnto-smp-instr" [3]ASPACE PID=2 PF=00401010 "proc/boot/devc-sermx1" armle context[effeef20]: 0000: 010766c4 00000000 00000000 40100005 010766c4 00000000 eff199b8 fe0a1144 0020: effd5290 effd5290 fe0a1448 fc412000 00000050 effd1310 fe07d638 01037fec 0040: 80000113 instruction[01037fec]: 00 80 bd e8 00 80 bd e8 00 40 2d e9 57 c0 a0 e3 00 00 00 ef 00 80 bd e8 00 40 stack[effd1310]: 0000: fe0a1600 effdc010 00000000 fe07d638 00000000 00000000 effd132c 00000000 0020: 00000010 00000000 00000000 00000000 00000000 00000000 00000000 00000000 0040: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 0060: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 U-Boot 2009.08 (Nov 26 2012 - 22:32:26) Thu, 28 Mar 2013 14:07:23 GMT http://community.qnx.com/sf/go/post100230 Ashfaque Ahamed 2013-03-28T14:07:23Z http://community.qnx.com/sf/go/post100226 Hello, I have posted an experimental archive containing the SPI library and sample driver source code, along with a Readme for building the source, here: http://community.qnx.com/sf/wiki/do/viewPage/projects.bsp/wiki/ExperimentalDriversAndUtilities?_message=1364476005299 Regards, Dave Thu, 28 Mar 2013 13:07:59 GMT http://community.qnx.com/sf/go/post100226 David Green 2013-03-28T13:07:59Z http://community.qnx.com/sf/go/post100214 Anyone? I also discovered that there is no libspi-master library or sources in the Sabrelite BSP. Is there a place where I can get this? Thu, 28 Mar 2013 01:02:50 GMT http://community.qnx.com/sf/go/post100214 Ivan Tarapov 2013-03-28T01:02:50Z http://community.qnx.com/sf/go/post100208 Hello all, Mentioned above behavior wasn't a real problem. It was result of my debugging code. Only of what I caused my problem was using atomic_set function like that denv-sja1000/event.c atomic_set(&ext->ir, *(volatile uint8_t *)(ext->mem + SJA1000_IR)); it doesn't work at PPC platform at all. Converting it regular read solve problem in ugly way but it works: ext->ir = *(volatile uint8_t *)(ext->mem + SJA1000_IR); Summarizing driver works fine with QNX 6.4.1 with using old stack io-net. Wed, 27 Mar 2013 18:22:56 GMT http://community.qnx.com/sf/go/post100208 Jerzy Dyrda 2013-03-27T18:22:56Z http://community.qnx.com/sf/go/post100146 Can anyone please help point me in the right direction with this problem? Thanks! Mon, 25 Mar 2013 16:30:58 GMT http://community.qnx.com/sf/go/post100146 David Kvasnica 2013-03-25T16:30:58Z http://community.qnx.com/sf/go/post100144 So far I have not had any luck with this. According to our board documentation, our ethernet chip is connected to the GPMC, CS4 with irq GPIO65. I am not familiar with how addressing works with GPMCs (I tried doing some research to figure out how, but did not come up with much), therefore I'm still unsure which port we should be using. I loaded a working embedded version of linux onto our board and pulled some logs. During bootup, I can see that the Ethernet driver connects to port 0x2c000000, irq 323. However, once the board is booted, we see this line in the logs: “smsc911x smsc911x.0: eth0: SMSC911x/921x identified at 0xd086a000, IRQ: 323”. I tried using both ports, but both appear to crash the driver: Process 28686 (io-pkt-v4) terminated SIGBUS code=3 fltno=5 ip=7800c4e0(/proc/boot/devn-smc9118.so@smc9118_detect+0x3d4) mapaddr=000024e0. ref=28000050 Any help/pointers would be greatly appreciated! Thanks Mon, 25 Mar 2013 16:14:53 GMT http://community.qnx.com/sf/go/post100144 David Kvasnica 2013-03-25T16:14:53Z http://community.qnx.com/sf/go/post100136 I found it by Googling "qnx am omap boot resources" :-) Mon, 25 Mar 2013 14:16:54 GMT http://community.qnx.com/sf/go/post100136 David Green 2013-03-25T14:16:54Z http://community.qnx.com/sf/go/post100135 David, thank you for your reply! By the way, i couldn't find this document both using Global Foundry27 Search and Using Wiki search (even with "OMAP" keyword). there are probably some issues with search engine, aren't they? Thanks, Igor Mon, 25 Mar 2013 14:01:57 GMT http://community.qnx.com/sf/go/post100135 Igor Rondarev 2013-03-25T14:01:57Z http://community.qnx.com/sf/go/post100134 Hi, The link you're looking for is the same link as found elsewhere in the document, here: "TI AM/OMAP Booting and Flash Recovery <http://community.qnx.com/sf/wiki/do/viewPage/projects.bsp/wiki/AM_OMAP_boo t_resources>". We'll get this broken link fixed in the readme document. Thanks, ------------------------- Dave Green QNX Software Systems Limited dgreen@qnx.com On 13-03-25 9:37 AM, "Igor Rondarev" <community-noreply@qnx.com> wrote: >Errata: >* the document itself ("TI OMAP3530 Beagle 6.5.0 BSP Readme") is >http://community.qnx.com/sf/go/rel3878 >* the broken link inside it is >http://community.qnx.com/sf/wiki/do/viewPage/projects.bsp/wiki/AM-OMAP_boo >t_resources > > > >_______________________________________________ > >QNX BSPs >http://community.qnx.com/sf/go/post100133 >To cancel your subscription to this discussion, please e-mail >general-bsp-unsubscribe@community.qnx.com Mon, 25 Mar 2013 13:45:58 GMT http://community.qnx.com/sf/go/post100134 David Green 2013-03-25T13:45:58Z http://community.qnx.com/sf/go/post100133 Errata: * the document itself ("TI OMAP3530 Beagle 6.5.0 BSP Readme") is http://community.qnx.com/sf/go/rel3878 * the broken link inside it is http://community.qnx.com/sf/wiki/do/viewPage/projects.bsp/wiki/AM-OMAP_boot_resources Mon, 25 Mar 2013 13:37:59 GMT http://community.qnx.com/sf/go/post100133 Igor Rondarev 2013-03-25T13:37:59Z http://community.qnx.com/sf/go/post100132 Hello, i've found a broken link inside a document which describes QNX installation to OMAP 3530 Beagle Board device; http://community.qnx.com/sf/wiki/do/viewPage/projects.bsp/wiki/AM-OMAP_boot_resources (aka http://community.qnx.com/sf/go/rel3878 ) How could it be fixed? BTW, does anybody know, what is the current link to this document (i'm particulary interested in QNX IPL section of this document) Thanks, Igor Mon, 25 Mar 2013 13:32:58 GMT http://community.qnx.com/sf/go/post100132 Igor Rondarev 2013-03-25T13:32:58Z http://community.qnx.com/sf/go/post100117 I found the code, under ...src/services/usb/hcd/class.c, and studied it in some details. It seems the driver would manage allocation and deallocation of the device address #. When we saw the issue, command "usb" only printed details for 1 device. If there's a missed reset/disconnect, we should see 2 devices on the output, I'd think. However, if the reset/disconnect is detected, then the previous number should have been deallocated, before a new enumeration occurs during which the same device number of 1 should have been assigned. Would this suggest I need to check for the latest class.c (or maybe the entire USB implementation) in 6.4.0 from QNX? I can make that request. What do you think? Sat, 23 Mar 2013 01:15:15 GMT http://community.qnx.com/sf/go/post100117 Raymond Yeung 2013-03-23T01:15:15Z http://community.qnx.com/sf/go/post100116 Hi, I would like to try out some things with SPI on i.MX6 board from Novtech. QNX has a BSP for SabreLite which is a similar board. Novtech offers a version of the BSP which was modified to strip away graphics, audio and ethernet and reconfigure the serial port base address. I have launched the board with this BSP and now I would like to know, how can I create two SPI devices and transfer some data between them. For now I would like to use two SPI ports that are available from i.MX6 on this board. I have never done this before, so I just need a few simple nudges in the right direction. At first, I am assuming that drivers need to be launched to enable the SPI ports on the boards. The default startup script from Sabrelite has this line in its build script: spi-master -u1 -d mx51ecspi base=0x02008000,irq=63,loopback=1 It also has some commented lines after that that go like this: # Starting Enhanced SPI driver ECSPI2 (/dev/spi2) # spi-master -u2 -d mx51ecspi base=0x0200C000,irq=64,loopback=1 I am assuming that base=0x02008000 specifies the base address for the SPI and it is unlikely that it's the same for Novtech. Am I right to assume that I need to call spi-master with proper parameters a few times before being able to use the ports from user-level code? Another question - how do this call maps to creation of dev/spiX device? How does the number gets assigned? How does this number maps to the actual i.MX6 pins? Thanks Sat, 23 Mar 2013 00:59:08 GMT http://community.qnx.com/sf/go/post100116 Ivan Tarapov 2013-03-23T00:59:08Z http://community.qnx.com/sf/go/post100107 I wish I remembered specifically enough to direct you, but normally I used the verbose output from the usb server to figure out the sequence of the implementation, I think you might be able to do that as well. If anything the traces should point you in the right direction. I hope that helps! Fri, 22 Mar 2013 17:03:50 GMT http://community.qnx.com/sf/go/post100107 Gervais Mulongoy 2013-03-22T17:03:50Z http://community.qnx.com/sf/go/post100101 Thanks Gervais. I've the USB source code. Would you remember where this reset and address allocation take place? Raymond Fri, 22 Mar 2013 15:29:12 GMT http://community.qnx.com/sf/go/post100101 Raymond Yeung 2013-03-22T15:29:12Z http://community.qnx.com/sf/go/post100092 There might be some signalling issues which is causing resets where the USB server will use the next free device address. If you turn on verbosity in the server you should be able to confirm. Fri, 22 Mar 2013 12:20:51 GMT http://community.qnx.com/sf/go/post100092 Gervais Mulongoy 2013-03-22T12:20:51Z http://community.qnx.com/sf/go/post100079 We use 8641d CPU with a multiple ports USB 2.0 controller. We have only 1 USB memory device to one of the 3 ports on the controller. We use ehci.so driver. When we invoke QNX command "usb", sometimes we see the memory device has a device address other than 1 (e.g. 2). How is this possible? How does the driver determine the address #? I'm expecting that the address should be "1" all the time. Fri, 22 Mar 2013 02:51:57 GMT http://community.qnx.com/sf/go/post100079 Raymond Yeung 2013-03-22T02:51:57Z http://community.qnx.com/sf/go/post100075 Display config file 2 Thu, 21 Mar 2013 18:17:27 GMT http://community.qnx.com/sf/go/post100075 David Kvasnica 2013-03-21T18:17:27Z http://community.qnx.com/sf/go/post100074 Display config file 1 Thu, 21 Mar 2013 18:17:00 GMT http://community.qnx.com/sf/go/post100074 David Kvasnica 2013-03-21T18:17:00Z http://community.qnx.com/sf/go/post100073 Hello, I am working with a CompuLab T3730 target board which is very similar to a Beagleboard. I downloaded the "Texas Instruments 3730 Beagleboard-xM" BSP, compiled it, and loaded it onto my target which appears to have worked for the most part, aside from two components: ethernet and display. For the display, it appears my drivers are loading correctly and that the egl-gears app is running properly (I see fps console prints and, according to pidi,n the app is running), however I don't see anything on the LCD. In fact, the LCD does not appear to be turned on at all. Is there something special I need to do to get the display information to be redirected to the LCD? Or perhaps do I need to perform some special commands to turn on the LCD? Attached is my build script and display config files. Thanks in advance! David Thu, 21 Mar 2013 18:16:33 GMT http://community.qnx.com/sf/go/post100073 David Kvasnica 2013-03-21T18:16:33Z http://community.qnx.com/sf/go/post100062 Right sorry, is the attached what you are asking for? In terms of "why am I...", the short answer is that this is the build script that came with the beagleboard BSP. I have not made many changes to it yet; I am still exploring the build script myself and trying to figure out what is going on inside it. However, I have done some digging around, and I believe the beagleboard bsp set up ethernet through a USB dongle and hence why the command to start the ethernet driver does not set a port/irq. I noticed in the slogger file the following error with my build: "devn-smc9118: must specify an I/O port and IRQ" I'm still trying to determine what should be the correct port/irq for my hardware, so hopefully that is all that is left for me to configure for ethernet. I will let you know once I make progress. Wed, 20 Mar 2013 21:37:57 GMT http://community.qnx.com/sf/go/post100062 David Kvasnica 2013-03-20T21:37:57Z http://community.qnx.com/sf/go/post100052 Hello, David. We transfer a file from memory DDR2 of CPU to USB mass storage device. We used USB mass storage (USB flash) with DOS and QNX filesystem. Wed, 20 Mar 2013 15:52:52 GMT http://community.qnx.com/sf/go/post100052 Nikolaeva Marina 2013-03-20T15:52:52Z http://community.qnx.com/sf/go/post100039 could you please describe how you are transferring the file? Is it a USB mass storage device? If so, which device? Where are you copying the file from/to? What filesystem is in use, DOS or QNX4? Wed, 20 Mar 2013 13:24:44 GMT http://community.qnx.com/sf/go/post100039 David Green 2013-03-20T13:24:44Z http://community.qnx.com/sf/go/post100038 can you post the entire build file (not just the startup script)? I want to see what drivers and libraries are included in your boot image. Also, why are you slaying and re-starting io-usb in the startup script? ------------------------- Dave Green QNX Software Systems Limited dgreen@qnx.com On 13-03-19 4:27 PM, "David Kvasnica" <community-noreply@qnx.com> wrote: >Attached > > > >_______________________________________________ > >QNX BSPs >http://community.qnx.com/sf/go/post100017 >To cancel your subscription to this discussion, please e-mail >general-bsp-unsubscribe@community.qnx.com Wed, 20 Mar 2013 12:49:00 GMT http://community.qnx.com/sf/go/post100038 David Green 2013-03-20T12:49:00Z http://community.qnx.com/sf/go/post100032 Platform: Neutrino 6.4.1 BSP: Freescale P2020 Drivers: devu-ehci-p2020.so When we transfer a file more than 64 Mbyte, we see that the file is transferred incorrectly. We see file corruption when copying file more than 64Mbytes. File, which we transferred a contains 24 Kbytes of the correct data and 8 Kbytes of the wrong data. And so it is consecutive in all file. Thus wrong transfer occurs not constantly. Wed, 20 Mar 2013 10:37:07 GMT http://community.qnx.com/sf/go/post100032 Nikolaeva Marina 2013-03-20T10:37:07Z http://community.qnx.com/sf/go/post100020 i migrated a QNX to beagleboard omap3530,i want use a usb camera on the board,but i can't find the device file in /dev.i found that i can use the network card because of a script ran when the system is booting.but i can't write a script for the usb camera.i think if somone could teach me how to deal with it,or give me a script to start the camera,thanks! and i will offer the script named network.sh. Wed, 20 Mar 2013 01:12:48 GMT http://community.qnx.com/sf/go/post100020 white shaw 2013-03-20T01:12:48Z http://community.qnx.com/sf/go/post100017 Attached Tue, 19 Mar 2013 20:27:39 GMT http://community.qnx.com/sf/go/post100017 David Kvasnica 2013-03-19T20:27:39Z http://community.qnx.com/sf/go/post100016 can you post the build file you're using to build the IFS image that boots the board? It could be that you're missing a necessary library... ------------------------- Dave Green QNX Software Systems Limited dgreen@qnx.com On 13-03-19 2:03 PM, "David Kvasnica" <community-noreply@qnx.com> wrote: >Great, thanks! > >I am still getting a similar error though: > >Starting network driver... >Unable to init devn-smc9118.so: Unknown error > >I'm guessing I have to perform some configurations to get this driver >running. Can you point me to what kind of configurations I might need to >do, or what my next steps should be to debug this and get it to work? > >Cheers! >David > > > >_______________________________________________ > >QNX BSPs >http://community.qnx.com/sf/go/post100012 >To cancel your subscription to this discussion, please e-mail >general-bsp-unsubscribe@community.qnx.com Tue, 19 Mar 2013 20:22:43 GMT http://community.qnx.com/sf/go/post100016 David Green 2013-03-19T20:22:43Z http://community.qnx.com/sf/go/post100013 Hi QNX Tech Support, Normally the tftpd has "--create" option, to allow a new file to be created when using TFTP to upload (put command) a file to the server. But the tftpd in QNX Neutrino 6.5.0 does not support "--create" option. Is there a way to allow file creating in QNX's tftpd? Thanks, Jane Sun Tue, 19 Mar 2013 18:53:54 GMT http://community.qnx.com/sf/go/post100013 Jane Sun 2013-03-19T18:53:54Z http://community.qnx.com/sf/go/post100012 Great, thanks! I am still getting a similar error though: Starting network driver... Unable to init devn-smc9118.so: Unknown error I'm guessing I have to perform some configurations to get this driver running. Can you point me to what kind of configurations I might need to do, or what my next steps should be to debug this and get it to work? Cheers! David Tue, 19 Mar 2013 18:03:53 GMT http://community.qnx.com/sf/go/post100012 David Kvasnica 2013-03-19T18:03:53Z http://community.qnx.com/sf/go/post100011 > Thanks for these nifty utilities, they can talk to the smart battery on an > Xplore iX104C5 tablet with slight mods You are welcome, I'm glad I could help. > Would there be any utilities that can > place the Xplore (x86) into sleep state S5? Unfortunately, no. You could use ACPICA ( https://www.acpica.org/ ) project to control power states of system devices, but each hardware component, including each device driver have to support S5. ACPICA is just an API for ACPI, all you need is to call proper ACPI functions for your needs. Tue, 19 Mar 2013 17:21:30 GMT http://community.qnx.com/sf/go/post100011 Mike Gorchak 2013-03-19T17:21:30Z http://community.qnx.com/sf/go/post99994 Hi, The devn-smc9118.so driver (with source code) is included in the BSP for the i.MX53 Sabre AI platform. You can download this BSP here: http://community.qnx.com/sf/frs/do/viewRelease/projects.bsp/frs.freescale_i_mx53_sabre_ai.freescale_i_mx53_sabre_ai_bsp Regards, Dave Tue, 19 Mar 2013 12:49:22 GMT http://community.qnx.com/sf/go/post99994 David Green 2013-03-19T12:49:22Z http://community.qnx.com/sf/go/post99987 Thanks for these nifty utilities, they can talk to the smart battery on an Xplore iX104C5 tablet with slight mods. Would there be any utilities that can place the Xplore (x86) into sleep state S5? Thanks Steve Anderson Tue, 19 Mar 2013 11:57:41 GMT http://community.qnx.com/sf/go/post99987 Steven Anderson 2013-03-19T11:57:41Z http://community.qnx.com/sf/go/post99973 Hello, I am pretty new to QNX so please bear with me. I am working with a CompuLab T3730 target board which is very similar to a Beagleboard. I downloaded the "Texas Instruments 3730 Beagleboard-xM" BSP, compiled it, and loaded it onto my target which appears to have worked for the most part, aside from two components: ethernet and display. For ethernet, I get the following during boot-up: Starting network driver... Unable to init devn-smsc9500.so: Unknown error So now my question is, how do I go about debugging and fixing this? My first thought was that this library is not the correct lib for my ethernet chip (SMSC LAN9220). Looking through the forum (http://community.qnx.com/sf/discussion/do/listPosts/projects.bsp/discussion.bsp.topc21914?_pagenum=3), it appears that devn-smsc9118.so is the correct one, however where can I download this lib? Thanks in advance! David Mon, 18 Mar 2013 22:40:57 GMT http://community.qnx.com/sf/go/post99973 David Kvasnica 2013-03-18T22:40:57Z http://community.qnx.com/sf/go/post99952 I'm trying to toggle the GP2[10] pin which is multiplexed with "SPI1_SIMO" pin through QNX Neutrino using the following piece of code: int main(int argc, char *argv[]) { /* Control a Thread */ if(ThreadCtl(_NTO_TCTL_IO, 0) < 0) printf("ERROR\n"); /* Gain access to OMAPL138 device's registers */ syscfg_addr = mmap_device_io(32, OMAPL138_SYSCFG_BASE); /* Unlocking the KICK registers */ out32(syscfg_addr + OMAPL138_SYSCFG_KICK0R, 0x83E70B13); out32(syscfg_addr + OMAPL138_SYSCFG_KICK1R, 0x95A4F1E0); /* Configure GP2[10] pin */ out32(syscfg_addr + OMAPL138_SYSCFG_PINMUX16, 0x00800000); /* Gain access to OMAPL138 GPIO registers */ gpio_base_addr = mmap_device_io(OMAPL138_GPIO_SIZE, OMAPL138_GPIO_BASE); /* Configure GP2[10] in output mode */ out32(gpio_base_addr + OMAPL138_GPIO_DIR23, in32(gpio_base_addr + OMAPL138_GPIO_DIR23) & 0xfffffbff); /* Locking the KICK registers */ out32(syscfg_addr + OMAPL138_SYSCFG_KICK0R, 0); out32(syscfg_addr + OMAPL138_SYSCFG_KICK1R, 0); while(1) { out32(gpio_base_addr + OMAPL138_GPIO_OUT_DATA23, in32(gpio_base_addr + OMAPL138_GPIO_OUT_DATA23) ^ 0x00000400); delay(400); } return EXIT_SUCCESS; } The code compiles fine, but when checked on the DSO, I'm NOT able to see the toggling on the GP2[10] pin. Can somebody help me on this? Is there something which I'm missing out in the above code? Regards, Deepti Mon, 18 Mar 2013 10:17:01 GMT http://community.qnx.com/sf/go/post99952 Deepti Panchal 2013-03-18T10:17:01Z http://community.qnx.com/sf/go/post99844 Good day. In attachment presents undefined in the common <hw/pci...> headers type of data PCI_INF. Please tell what is this structure? Wed, 13 Mar 2013 07:25:56 GMT http://community.qnx.com/sf/go/post99844 Vadim V 2013-03-13T07:25:56Z http://community.qnx.com/sf/go/post99837 Hi, I am trying to port qnx bsp on to a ARM V5TE processor which is having a unified L2$ ( programmed through CP15). Could you tell me the steps to add L2$ during hardware Initialization? should it be done through the cacheattr? if so could you please explain. Thanks, Preetham Tue, 12 Mar 2013 20:55:25 GMT http://community.qnx.com/sf/go/post99837 Preetham Chandrian 2013-03-12T20:55:25Z http://community.qnx.com/sf/go/post99814 OK, just define them yourself: #define ... Tue, 12 Mar 2013 11:21:48 GMT http://community.qnx.com/sf/go/post99814 Vadim V 2013-03-12T11:21:48Z http://community.qnx.com/sf/go/post99804 Hi, I am using IMX53QSB, how can I enable the VGA and photon? I tried to modify in the build file from the src/hardware/startup/boards/imx53qsb/build file, could not fix. Tue, 12 Mar 2013 09:40:40 GMT http://community.qnx.com/sf/go/post99804 Ramesh R 2013-03-12T09:40:40Z http://community.qnx.com/sf/go/post99791 We have been working on project where we are porting from QNX kernel to Linux kernel,Currently we have QNX build file from where we are calling our procnto Qnx kernel after some startup code. Now we are trying to call Linux Kernel instead of Qnx Kernel but while building our IFS file we are not able to link to Linux Kernel to this final IFS image although we have inserted ELF Header into Linux KERNEL. Error msg shows says -> Warning: Host file 'libc.so' missing. Can not find required linker for '/nobackup/njaganat/CRS_2/nto/os/sys/bin-x86e/Linux_kernel '. /nobackup/njaganat/CRS_2/nto/util/bin-x86-linux/mkxfs returns error Below is content of build file. [image=0x400000] [+optional] [+compress] [linker="gld.c4.2.1-p2.linux -m elf_i386 -e _start -T/xyz/build/src-x86e/link.map -EL %(h!=0, -Ttext 0x%t%)%(d!=0, -Tdata 0x%d%) -o%o %i %[M -L%^i -uinit_%n -lmod_%n -L%^i -L/nobackup/xyz/nto/os/lib/bin-x86e -Bstatic -lc %]"] [virtual=x86,name] .bootstrap = { [+keeplinked] [search="$\{ROOT_DIR\}"/nto/os/sys/bin-x86e ] KER_VSIZE=512M PATH="/bin:/sbin:" Linux_kernel } Is it because we are missing libc.so file as "The runtime linker is expected to be found in a file called ldqnx.so.2, but the runtime linker is currently contained within the libc.so file, so we would make a process manager symbolic link to it." Canbody let us know what could be the problem Thanks, Amit Mon, 11 Mar 2013 19:51:38 GMT http://community.qnx.com/sf/go/post99791 AMIT TOMAR 2013-03-11T19:51:38Z http://community.qnx.com/sf/go/post99775 Hi, Although the topic is quite old, maybe You can help me. I'm interesting in using SUSI API with QNX RTOS on Advantech's PCM-3362. Is it included in BSP You have mentioned above or it is necessary to install it separately. If so, is there any manual/toutorial how to do this? I have not found any information about it either on foundary27 or Advantech's website. I would be gratefull for any help in this matter. Regards Marcin Fri, 08 Mar 2013 20:36:12 GMT http://community.qnx.com/sf/go/post99775 Marcin Morawski 2013-03-08T20:36:12Z http://community.qnx.com/sf/go/post99774 Sorry for past tiredness and thanks for answer, I meant the initialized function pci_attach_device(), of course. But how will I fill in the fields of struct pci_dev_info* inf: inf->VendorId and inf->DeviceId, if we have no QNX defined values for them? Fri, 08 Mar 2013 20:18:55 GMT http://community.qnx.com/sf/go/post99774 Vadim V 2013-03-08T20:18:55Z http://community.qnx.com/sf/go/post99728 I believe pci_device_attach() should do the trick even if your device isn't in the list of "known" or supported devices as per the documentation. Thu, 07 Mar 2013 12:37:01 GMT http://community.qnx.com/sf/go/post99728 Gervais Mulongoy 2013-03-07T12:37:01Z http://community.qnx.com/sf/go/post99721 Yes, I noticed that the patch files were binary and there were source files in the corresponding directory tree locations in the BSP project. Thanks for the answers. -----Original Message----- From: David Green [mailto:community-noreply@qnx.com] Sent: Wednesday, March 06, 2013 7:16 AM To: general-bsp@community.qnx.com Subject: Re: x86 patch installation for Advantech AIMB-580 BSP Hi Doug, Yes, building the current BSP in an SP1 environment will get you the 'latest greatest' x86 support. The previous patch was a roll-up of the current (at that time) x86 startup library and related components, but there have been additional improvements and chipset support added since then. Patches and BSPs don't typically intermingle; the patch likely consists of pre-built binaries and libraries, which will get installed to (for example) /boot/sys/startup-apic, or /boot/sys/startup-bios on your host PC. The BSP builds these components from source, and then installs them to the BSP's own install/x86/boot/sys/ directory, where they will get picked up by mkifs when you make IFS (in the BSP's /images directory). I think to apply the patch to an existing IDE project, you would need to manually copy the desired components from the patch to the equivalent directory where the IDE is picking them up for its project. ------------------------- Dave Green QNX Software Systems Limited dgreen@qnx.com On 13-03-05 6:28 PM, "Doug Warner" <community-noreply@qnx.com> wrote: >I have a separate development host with Momentics 6.5.0 SP1 installed >on it; the plan is to do the development work on the host and download >results to the target (AIMB-580) and debug remotely. > >I take it you are saying that building the current x86 BSP on this host >system, which includes SP1, effectively includes the patch I referenced >for use of the x86 BSP on my AIMB-580 board? > >I would still like to find instructions for adding a patch to a BSP >that will be built under Momentics (how to copy the patches into the >x86 project (or whatever target flavor) in Eclipse. > >-----Original Message----- >From: David Green [mailto:community-noreply@qnx.com] >Sent: Tuesday, March 05, 2013 7:29 AM >To: general-bsp@community.qnx.com >Subject: Re: x86 patch installation for Advantech AIMB-580 BSP > >Hi Doug, > >The x86 update patch you refer to is obsolete; the most current x86 >support can be found in QNX Momentics 6.5.0 SP1, upon which the current >x86 BIOS/APIC BSP is based. You can most likely use your AIMB-580 >system as a host, by connecting a CD-ROM and hard drive to it, and >install Momentics 6.5.0 directly, followed by applying the SP1 patch. >This combination already contains binaries of startup-bios and >startup-apic which should be suitable for booting your board. If you >find it necessary to rebuild the startup code, you can then get the x86 >BSP and build it. > >For the latest support of HD audio, Intel network controllers, >graphics, etc., you can find it here: > >http://community.qnx.com/sf/wiki/do/viewPage/projects.bsp/wiki/Experime >nta >lDriversAndUtilities > >http://community.qnx.com/sf/wiki/do/viewPage/projects.bsp/wiki/Released >Dri >versAndUtilities > >Regards, > >------------------------- >Dave Green >QNX Software Systems Limited >dgreen@qnx.com > > >From: Doug Warner ><community-noreply@qnx.com<mailto:community-noreply@qnx.com>> >Reply-To: >"general-bsp@community.qnx.com<mailto:general-bsp@community.qnx.com>" ><general-bsp@community.qnx.com<mailto:general-bsp@community.qnx.com>> >Date: Monday, 4 March, 2013 8:08 PM >To: "general-bsp@community.qnx.com<mailto:general-bsp@community.qnx.com>" ><general-bsp@community.qnx.com<mailto:general-bsp@community.qnx.com>> >Subject: x86 patch installation for Advantech AIMB-580 BSP > >I have the Advantech AIMB-580 board; have downloaded the ³x86 BIOS / >APIC² BSP and successfully built it using the 6.5.0 Eclipse IDE > >I assume I need start with the above x86 BSP and then add the following >update patch for use with the Advantech board: Patch: x86 update #1 >for SDP 6.5.0 ³patch-650-2338-RS3775_x86-650-updates.tar² > >How do I add this patch to the Eclipse project? > > > > >_______________________________________________ > >QNX BSPs >http://community.qnx.com/sf/go/post99682 >To cancel your subscription to this discussion, please e-mail >general-bsp-unsubscribe@community.qnx.com > > > > > >_______________________________________________ > >QNX BSPs >http://community.qnx.com/sf/go/post99695 >To cancel your subscription to this discussion, please e-mail >general-bsp-unsubscribe@community.qnx.com _______________________________________________ QNX BSPs http://community.qnx.com/sf/go/post99700 To cancel your subscription to this discussion, please e-mail general-bsp-unsubscribe@community.qnx.com Wed, 06 Mar 2013 23:32:38 GMT http://community.qnx.com/sf/go/post99721 Doug Warner 2013-03-06T23:32:38Z http://community.qnx.com/sf/go/post99718 Sorry for question, now I want to write a resource manager for the PCIe controller of the FPGA device. Among vendors in <hw/pci_device.h> my vendor -- 0x1172 -- is abscent. Do I have a chance to register my device in the PCI Config Space? And what kind of the way? Through pci_device_attach() or something else? With regards... Wed, 06 Mar 2013 21:49:57 GMT http://community.qnx.com/sf/go/post99718 Vadim V 2013-03-06T21:49:57Z http://community.qnx.com/sf/go/post99703 I am in need of a utility to obtain battery status for a commercial medical device. The iX104C5 uses an IT8760E LPC at bus address 2E according to XploreTech. Running dump_smbus finds SMBUS0 with 4 devices, two unknown. Running smb-ec results in "Memory fault (core dumped)". It appears the code attempts to read memory at address 0x400EC010, evidently a no-no. Any help would be much appreciated! Wed, 06 Mar 2013 13:57:50 GMT http://community.qnx.com/sf/go/post99703 Steven Anderson 2013-03-06T13:57:50Z http://community.qnx.com/sf/go/post99700 Hi Doug, Yes, building the current BSP in an SP1 environment will get you the 'latest greatest' x86 support. The previous patch was a roll-up of the current (at that time) x86 startup library and related components, but there have been additional improvements and chipset support added since then. Patches and BSPs don't typically intermingle; the patch likely consists of pre-built binaries and libraries, which will get installed to (for example) /boot/sys/startup-apic, or /boot/sys/startup-bios on your host PC. The BSP builds these components from source, and then installs them to the BSP's own install/x86/boot/sys/ directory, where they will get picked up by mkifs when you make IFS (in the BSP's /images directory). I think to apply the patch to an existing IDE project, you would need to manually copy the desired components from the patch to the equivalent directory where the IDE is picking them up for its project. ------------------------- Dave Green QNX Software Systems Limited dgreen@qnx.com On 13-03-05 6:28 PM, "Doug Warner" <community-noreply@qnx.com> wrote: >I have a separate development host with Momentics 6.5.0 SP1 installed on >it; the plan is to do the development work on the host and download >results to the target (AIMB-580) and debug remotely. > >I take it you are saying that building the current x86 BSP on this host >system, which includes SP1, effectively includes the patch I referenced >for use of the x86 BSP on my AIMB-580 board? > >I would still like to find instructions for adding a patch to a BSP that >will be built under Momentics (how to copy the patches into the x86 >project (or whatever target flavor) in Eclipse. > >-----Original Message----- >From: David Green [mailto:community-noreply@qnx.com] >Sent: Tuesday, March 05, 2013 7:29 AM >To: general-bsp@community.qnx.com >Subject: Re: x86 patch installation for Advantech AIMB-580 BSP > >Hi Doug, > >The x86 update patch you refer to is obsolete; the most current x86 >support can be found in QNX Momentics 6.5.0 SP1, upon which the current >x86 BIOS/APIC BSP is based. You can most likely use your AIMB-580 system >as a host, by connecting a CD-ROM and hard drive to it, and install >Momentics 6.5.0 directly, followed by applying the SP1 patch. This >combination already contains binaries of startup-bios and startup-apic >which should be suitable for booting your board. If you find it >necessary to rebuild the startup code, you can then get the x86 BSP and >build it. > >For the latest support of HD audio, Intel network controllers, graphics, >etc., you can find it here: > >http://community.qnx.com/sf/wiki/do/viewPage/projects.bsp/wiki/Experimenta >lDriversAndUtilities > >http://community.qnx.com/sf/wiki/do/viewPage/projects.bsp/wiki/ReleasedDri >versAndUtilities > >Regards, > >------------------------- >Dave Green >QNX Software Systems Limited >dgreen@qnx.com > > >From: Doug Warner ><community-noreply@qnx.com<mailto:community-noreply@qnx.com>> >Reply-To: >"general-bsp@community.qnx.com<mailto:general-bsp@community.qnx.com>" ><general-bsp@community.qnx.com<mailto:general-bsp@community.qnx.com>> >Date: Monday, 4 March, 2013 8:08 PM >To: "general-bsp@community.qnx.com<mailto:general-bsp@community.qnx.com>" ><general-bsp@community.qnx.com<mailto:general-bsp@community.qnx.com>> >Subject: x86 patch installation for Advantech AIMB-580 BSP > >I have the Advantech AIMB-580 board; have downloaded the ³x86 BIOS / >APIC² BSP and successfully built it using the 6.5.0 Eclipse IDE > >I assume I need start with the above x86 BSP and then add the following >update patch for use with the Advantech board: Patch: x86 update #1 for >SDP 6.5.0 ³patch-650-2338-RS3775_x86-650-updates.tar² > >How do I add this patch to the Eclipse project? > > > > >_______________________________________________ > >QNX BSPs >http://community.qnx.com/sf/go/post99682 >To cancel your subscription to this discussion, please e-mail >general-bsp-unsubscribe@community.qnx.com > > > > > >_______________________________________________ > >QNX BSPs >http://community.qnx.com/sf/go/post99695 >To cancel your subscription to this discussion, please e-mail >general-bsp-unsubscribe@community.qnx.com Wed, 06 Mar 2013 13:15:36 GMT http://community.qnx.com/sf/go/post99700 David Green 2013-03-06T13:15:36Z http://community.qnx.com/sf/go/post99695 I have a separate development host with Momentics 6.5.0 SP1 installed on it; the plan is to do the development work on the host and download results to the target (AIMB-580) and debug remotely. I take it you are saying that building the current x86 BSP on this host system, which includes SP1, effectively includes the patch I referenced for use of the x86 BSP on my AIMB-580 board? I would still like to find instructions for adding a patch to a BSP that will be built under Momentics (how to copy the patches into the x86 project (or whatever target flavor) in Eclipse. -----Original Message----- From: David Green [mailto:community-noreply@qnx.com] Sent: Tuesday, March 05, 2013 7:29 AM To: general-bsp@community.qnx.com Subject: Re: x86 patch installation for Advantech AIMB-580 BSP Hi Doug, The x86 update patch you refer to is obsolete; the most current x86 support can be found in QNX Momentics 6.5.0 SP1, upon which the current x86 BIOS/APIC BSP is based. You can most likely use your AIMB-580 system as a host, by connecting a CD-ROM and hard drive to it, and install Momentics 6.5.0 directly, followed by applying the SP1 patch. This combination already contains binaries of startup-bios and startup-apic which should be suitable for booting your board. If you find it necessary to rebuild the startup code, you can then get the x86 BSP and build it. For the latest support of HD audio, Intel network controllers, graphics, etc., you can find it here: http://community.qnx.com/sf/wiki/do/viewPage/projects.bsp/wiki/ExperimentalDriversAndUtilities http://community.qnx.com/sf/wiki/do/viewPage/projects.bsp/wiki/ReleasedDriversAndUtilities Regards, ------------------------- Dave Green QNX Software Systems Limited dgreen@qnx.com From: Doug Warner <community-noreply@qnx.com<mailto:community-noreply@qnx.com>> Reply-To: "general-bsp@community.qnx.com<mailto:general-bsp@community.qnx.com>" <general-bsp@community.qnx.com<mailto:general-bsp@community.qnx.com>> Date: Monday, 4 March, 2013 8:08 PM To: "general-bsp@community.qnx.com<mailto:general-bsp@community.qnx.com>" <general-bsp@community.qnx.com<mailto:general-bsp@community.qnx.com>> Subject: x86 patch installation for Advantech AIMB-580 BSP I have the Advantech AIMB-580 board; have downloaded the “x86 BIOS / APIC” BSP and successfully built it using the 6.5.0 Eclipse IDE I assume I need start with the above x86 BSP and then add the following update patch for use with the Advantech board: Patch: x86 update #1 for SDP 6.5.0 “patch-650-2338-RS3775_x86-650-updates.tar” How do I add this patch to the Eclipse project? _______________________________________________ QNX BSPs http://community.qnx.com/sf/go/post99682 To cancel your subscription to this discussion, please e-mail general-bsp-unsubscribe@community.qnx.com Tue, 05 Mar 2013 23:28:48 GMT http://community.qnx.com/sf/go/post99695 Doug Warner 2013-03-05T23:28:48Z http://community.qnx.com/sf/go/post99682 Hi Doug, The x86 update patch you refer to is obsolete; the most current x86 support can be found in QNX Momentics 6.5.0 SP1, upon which the current x86 BIOS/APIC BSP is based. You can most likely use your AIMB-580 system as a host, by connecting a CD-ROM and hard drive to it, and install Momentics 6.5.0 directly, followed by applying the SP1 patch. This combination already contains binaries of startup-bios and startup-apic which should be suitable for booting your board. If you find it necessary to rebuild the startup code, you can then get the x86 BSP and build it. For the latest support of HD audio, Intel network controllers, graphics, etc., you can find it here: http://community.qnx.com/sf/wiki/do/viewPage/projects.bsp/wiki/ExperimentalDriversAndUtilities http://community.qnx.com/sf/wiki/do/viewPage/projects.bsp/wiki/ReleasedDriversAndUtilities Regards, ------------------------- Dave Green QNX Software Systems Limited dgreen@qnx.com From: Doug Warner <community-noreply@qnx.com<mailto:community-noreply@qnx.com>> Reply-To: "general-bsp@community.qnx.com<mailto:general-bsp@community.qnx.com>" <general-bsp@community.qnx.com<mailto:general-bsp@community.qnx.com>> Date: Monday, 4 March, 2013 8:08 PM To: "general-bsp@community.qnx.com<mailto:general-bsp@community.qnx.com>" <general-bsp@community.qnx.com<mailto:general-bsp@community.qnx.com>> Subject: x86 patch installation for Advantech AIMB-580 BSP I have the Advantech AIMB-580 board; have downloaded the “x86 BIOS / APIC” BSP and successfully built it using the 6.5.0 Eclipse IDE I assume I need start with the above x86 BSP and then add the following update patch for use with the Advantech board: Patch: x86 update #1 for SDP 6.5.0 “patch-650-2338-RS3775_x86-650-updates.tar” How do I add this patch to the Eclipse project? Tue, 05 Mar 2013 13:29:35 GMT http://community.qnx.com/sf/go/post99682 David Green 2013-03-05T13:29:35Z http://community.qnx.com/sf/go/post99673 I have the Advantech AIMB-580 board; have downloaded the "x86 BIOS / APIC" BSP and successfully built it using the 6.5.0 Eclipse IDE I assume I need start with the above x86 BSP and then add the following update patch for use with the Advantech board: Patch: x86 update #1 for SDP 6.5.0 "patch-650-2338-RS3775_x86-650-updates.tar" How do I add this patch to the Eclipse project? Tue, 05 Mar 2013 01:08:58 GMT http://community.qnx.com/sf/go/post99673 Doug Warner 2013-03-05T01:08:58Z http://community.qnx.com/sf/go/post99669 Thank you. Mon, 04 Mar 2013 19:20:37 GMT http://community.qnx.com/sf/go/post99669 Scott Leonard 2013-03-04T19:20:37Z http://community.qnx.com/sf/go/post99667 Okay thanks! When I tried to reset the bootcmd environment variable to change it to 6q_bootscript using this command: setenv bootcmd "for dtype in sata mmc ; do for disk in 0 1 ; do ${dtype} dev ${disk} ;for fs in fat ext2 ; do ${fs}load ${dtype} ${disk}:1 10008000 /6q_bootscript&& source 10008000 ; done ; done ; done; setenv stdout serial,vga ; echo ; echo 6q_bootscript not found ; echo ; echo serial console at 115200, 8N1 ; echo ; echo details at http://boundarydevices.com/6q_bootscript ; setenv stdout serial" it stopped me midway and I couldn't finish the command. Is this a limit of Tera Term or the console? Mon, 04 Mar 2013 18:22:23 GMT http://community.qnx.com/sf/go/post99667 Ruben Rodriguez 2013-03-04T18:22:23Z http://community.qnx.com/sf/go/post99666 As I recall, renaming 6q_bootscript to 6x_bootscript allowed the same qnx bsp to boot on the newer Boundary hardware... if I am wrong, it wasn't hard to test anyway! Mon, 04 Mar 2013 18:01:40 GMT http://community.qnx.com/sf/go/post99666 Dennis Kellly 2013-03-04T18:01:40Z http://community.qnx.com/sf/go/post99665 Hello, My team and I are having issues booting up the Sabre Lite board that we received last week. When we look at the console in Tera Term, the board outputs: SATA device 1: unknown device ** Bad device sata 1 ** ** Bad device sata 1 ** mmc0 is current device reading /6x_bootscript ** Unable to read file /6x_bootscript ** Failed to mount ext2 filesystem... ** Unrecognized filesystem type ** MMC: no card present mmc1(part 0) is current device MMC: no card present ** Bad device mmc 1 ** MMC: no card present ** Bad device mmc 1 ** 6x_bootscript not found serial console at 115200, 8N1 details at http://boundarydevices.com/6q_bootscript We were wondering if anybody could help us. Thank you. Mon, 04 Mar 2013 17:52:00 GMT http://community.qnx.com/sf/go/post99665 Ruben Rodriguez 2013-03-04T17:52:00Z http://community.qnx.com/sf/go/post99659 Thanks for reply devc-sermx1 -e -F -c66500000 0x73FBC000,31 code is starting serial driver and this code added .bsh file. You can look my bsh file for more information Sat, 02 Mar 2013 20:46:01 GMT http://community.qnx.com/sf/go/post99659 Seyfettin Sünger 2013-03-02T20:46:01Z http://community.qnx.com/sf/go/post99658 Hi - to me it seems like you do not have serial driver started. ksh is using the "callout" to write to the terminal , these are basic C routines used by startup program to ouput to terminal during boot. once os runs - serila driver should be loaded. Ran Sat, 02 Mar 2013 17:08:19 GMT http://community.qnx.com/sf/go/post99658 ran wainstein 2013-03-02T17:08:19Z http://community.qnx.com/sf/go/post99657 Hi All, I'm working imx51 evk with QNX. I'm gettin this error when i load image to imx51 evk board. Also terminal locking when image loaded . You can look attachments for all termina outputs. How can i solve this? Regards, Sat, 02 Mar 2013 17:04:19 GMT http://community.qnx.com/sf/go/post99657 Eren Basturk 2013-03-02T17:04:19Z http://community.qnx.com/sf/go/post99648 We are getting the same error ENOSYS. mkfifo on ARM v7 doesn't work under /tmp (linked to /dev/shmem) or /sd (where our writable SD card is mounted). Did anyone find a solution to this problem? Fri, 01 Mar 2013 19:02:38 GMT http://community.qnx.com/sf/go/post99648 Vincent Wan 2013-03-01T19:02:38Z http://community.qnx.com/sf/go/post99618 See devc-serusb documentation. Supports common dongles with Prolific or FTDI chipsets. Thu, 28 Feb 2013 21:25:30 GMT http://community.qnx.com/sf/go/post99618 Dennis Kellly 2013-02-28T21:25:30Z http://community.qnx.com/sf/go/post99617 The docs list only 10 USB devices (literally): keyboards, mice, and a couple of printers. I see posts talking about thumb drives and ethernet adapters, so what about USB to serial? Thu, 28 Feb 2013 21:21:59 GMT http://community.qnx.com/sf/go/post99617 Scott Leonard 2013-02-28T21:21:59Z http://community.qnx.com/sf/go/post99568 Hello: I want to known whether QNX6.5 support multitouch screen? I design touch screen data will pass to photon interface. if QNX6.5 support multitouch screen, I should call which interface function? There is no example code reference？ Yin Xingjie Wed, 27 Feb 2013 09:40:17 GMT http://community.qnx.com/sf/go/post99568 yin xingjie 2013-02-27T09:40:17Z http://community.qnx.com/sf/go/post99493 <HTML> <BR> <BR> <BR> <BR> <span style="font-weight: bold;">On Sat Feb 23 7:14 , Allen Chen <community-noreply@qnx.com> sent:<BR> <BR> </community-noreply@qnx.com></span><blockquote style="BORDER-LEFT: #F5F5F5 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px; PADDING-RIGHT: 0px">I have two Arduino board, UNO and Mega. As a newbie for QNX, I wonder whether there is a QNX BSP for Arduino. Because Arduino is much cheap and easy to set up example experiments with I/O PINs.<BR> <BR> AVR micro are 8bit, no MMU, no way to have qnx on it :-)<BR> <BR> <BR> </blockquote></HTML> <BR> Sun, 24 Feb 2013 18:02:59 GMT http://community.qnx.com/sf/go/post99493 mario sangalli 2013-02-24T18:02:59Z http://community.qnx.com/sf/go/post99490 I have two Arduino board, UNO and Mega. As a newbie for QNX, I wonder whether there is a QNX BSP for Arduino. Because Arduino is much cheap and easy to set up example experiments with I/O PINs. Sat, 23 Feb 2013 06:14:44 GMT http://community.qnx.com/sf/go/post99490 Allen Chen 2013-02-23T06:14:44Z http://community.qnx.com/sf/go/post99417 the BSP at http://community.qnx.com/sf/frs/do/listReleases/projects.bsp/frs.intel_crown_bay has devc-serpci source. Others might as well On 02/21/2013 07:57 AM, Javier I. Acosta M. wrote: > I have the same problem, any idea where can I find the driver code? > > Thank you, > Javier > > > > _______________________________________________ > > QNX BSPs > http://community.qnx.com/sf/go/post99416 > To cancel your subscription to this discussion, please e-mail general-bsp-unsubscribe@community.qnx.com Thu, 21 Feb 2013 13:13:07 GMT http://community.qnx.com/sf/go/post99417 Michael Kisel 2013-02-21T13:13:07Z http://community.qnx.com/sf/go/post99416 I have the same problem, any idea where can I find the driver code? Thank you, Javier Thu, 21 Feb 2013 12:57:32 GMT http://community.qnx.com/sf/go/post99416 Javier I. Acosta M. 2013-02-21T12:57:32Z