03/09/2009 11:00 PM
NAND flash support for 5 addr cycles?
Looking at nand.c, it is not obvious that 5 address cycles are supported. I
did not find the code for the low-level functions such as nandio_init1,
nandio_reset, nandio_idread, etc. Am I missing something? Is there a good
sample for building a complete resource manager using a large-block NAND
flash. Our mfr. code is 0xEC, and type 0xAA. Added a section to nand_init:
case 0xaa: // 128 Mbyte
ncp->numblks = 2048;
ncp->addrcycles = 5;
ncp->pagemapbits = 18;
ncp->totspares = 40;
The controller (NXP LPC3180-01) has two NAND controllers to select from, a
single-level and multi-level. I can use raw C code (no OS) to do basic
operations on these 2 controllers (get id, read, erase, write). Just am a
bit confused how to use nand.c properly.