Sesh
09/06/2013 7:22 PM
post104909
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Hello,
I am looking for RMII driver for i.MX6 on QNX.
I've modified existing RGMII driver with the following updates, but the MAC cannot detect RMII PHY
********** Software changes to support RMII on I.MX6 to handshake with PHY add on module
IOMUX changes [ mx6q_gpio.c/Added new function that is invoked in place of mx6q_init_enet ]
void mx6q_init_enet_RMII(void)
{
// RMII MDIO - transfers control info between MAC and PHY
pinmux_set_swmux(SWMUX_ENET_MDIO, MUX_CTL_MUX_MODE_ALT1);
pinmux_set_input(SWINPUT_ENET_IPP_IND_MAC0_MDIO,0);
// RMII MDC - output from MAC to PHY, provides clock reference for MDIO
pinmux_set_swmux(SWMUX_ENET_MDC, MUX_CTL_MUX_MODE_ALT1);
//RMII ENET_CRS_DV
pinmux_set_swmux(SWMUX_ENET_CRS_DV, MUX_CTL_MUX_MODE_ALT1);
pinmux_set_padcfg(SWPAD_ENET_CRS_DV, MX6X_PAD_SETTINGS_ENET);
pinmux_set_input(SWINPUT_ENET_IPP_IND_MAC0_RXEN,1); //ENET_CRS_DV for mode ALT1
//RMII ENET_RX_ER
pinmux_set_swmux(SWMUX_ENET_RX_ER, MUX_CTL_MUX_MODE_ALT1);
pinmux_set_padcfg(SWPAD_ENET_RX_ER, MX6X_PAD_SETTINGS_ENET);
//RMII ENET_TX_EN
pinmux_set_swmux(SWMUX_ENET_TX_EN, MUX_CTL_MUX_MODE_ALT1);
pinmux_set_padcfg(SWPAD_ENET_TX_EN, MX6X_PAD_SETTINGS_ENET);
//RMII ENET_RXD0
pinmux_set_swmux(SWMUX_ENET_RXD0, MUX_CTL_MUX_MODE_ALT1);
pinmux_set_padcfg(SWPAD_ENET_RXD0, MX6X_PAD_SETTINGS_ENET);
pinmux_set_input(SWINPUT_ENET_IPP_IND_MAC_RXDATA_0,1); //ENET_RXD0 for Mode ALT1
//RMII ENET_RXD1
pinmux_set_swmux(SWMUX_ENET_RXD1, MUX_CTL_MUX_MODE_ALT1);
pinmux_set_padcfg(SWPAD_ENET_RXD1, MX6X_PAD_SETTINGS_ENET);
pinmux_set_input(SWINPUT_ENET_IPP_IND_MAC_RXDATA_1,1); //ENET_RXD1 for Mode ALT1
//RMII ENET_TXD0
pinmux_set_swmux(SWMUX_ENET_TXD0, MUX_CTL_MUX_MODE_ALT1);
pinmux_set_padcfg(SWPAD_ENET_TXD0, MX6X_PAD_SETTINGS_ENET);
//RMII ENET_TXD1
pinmux_set_swmux(SWMUX_ENET_TXD1, MUX_CTL_MUX_MODE_ALT1);
pinmux_set_padcfg(SWPAD_ENET_TXD1, MX6X_PAD_SETTINGS_ENET);
//RMII GPIO 16 provides 50 Mhz reference clock to PHY
pinmux_set_swmux(SWMUX_GPIO_16, MUX_CTL_MUX_MODE_ALT2 | MUX_CTL_SION);
pinmux_set_padcfg(SWPAD_GPIO_16, MX6X_PAD_SETTINGS_ENET);
pinmux_set_input(SWINPUT_ENET_IPG_CLK_RMII, 1);
//Enable ANATOP PLL ( Automatically handled in /* SATA */
//mx6x_init_sata(ANATOP_PLL8_ENET_REF_ENET_50M);)
// invoke mx6q_init_enet_RMII after init_sata function
//Obtain ENET Tx reference clock from ANATOP(loopback through pad)
//and send out to the external PHY
out32(MX6X_IOMUXC_BASE + MX6X_IOMUX_GPR1, in32(MX6X_IOMUXC_BASE + MX6X_IOMUX_GPR1) | (1 << 21));
}
*********************************************************************
In function detect.c/mx6q_init
*(base + MX6Q_R_CNTRL) |= RCNTRL_RMII_MODE;
Thanks,
Sesh
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