There seems to be a race/timing condition where the TDAR (Transmit Descriptor Active Register) bit can be reset by the 
hardware after it is set in mcimx28_send, but before the packet is sent.
It means the packet has to wait until the next Tx before it is sent.

One way to resolve this is to reset the bit every time a Tx interrupt occurs in mcimx28_process_interrupt().
Adding the out32 line below (and the braces) removes the issue:

		if (eir & (MX28_HW_ENET_MAC_EIR_TXB | MX28_HW_ENET_MAC_EIR_BABT | MX28_HW_ENET_MAC_EIR_UN))
		{
			mcimx28_transmit_complete (ext, eir);
			out32 (ext->iobase + MX28_HW_ENET_MAC_TDAR, MX28_HW_ENET_MAC_TDAR_TDAR);
		}