Malte Mundt wrote:
> A potential customer is seeing 8us interrupt latency, using 6.3. 

Are you talking about ISR or IST latency?

> What ways are there to improve interrupt latency?
> 
> 1) is 6.4 expected to significantly improve interrupt latency (e.g. because of large page? does large page exist on 
ARM9 anyway) ?

> 2) is it possibly to "bypass" the kernel for 1 certain interrupt source by hacking around in the callouts (startup 
code)?

That's getting pretty extreme...

-- 
cburgess@qnx.com

I would guess the only improvement to interrupt latency you'd get in 6.4 are related
to the improved kernel code performance because of the 1MB code and data mappings set
up by the 6.4 libstartup code. The ARM926 has quite poor TLB performance and pre-6.4
we always used 4K pages which cause a lot of micro-TLB misses that significantly lower
the performance.

I don't know how the interrupt controller on that chip works, but there could well be
some relatively expensive operations being performed in the id callout.

	Sunil.

Malte Mundt wrote:
> A potential customer is seeing 8us interrupt latency, using 6.3. 
> 
> What ways are there to improve interrupt latency?
> 
> 1) is 6.4 expected to significantly improve interrupt latency (e.g. because of large page? does large page exist on 
ARM9 anyway) ?
> 
> 2) is it possibly to "bypass" the kernel for 1 certain interrupt source by hacking around in the callouts (startup 
code)?
> 
> 
> - Malte
> 
> 
> _______________________________________________
> OSTech
> http://community.qnx.com/sf/go/post29272
>