Sorry for the delayed response.
I have verified the PINMUX and clock paths. Everything looks in order. Furthermore, I ported Linux on the custom board 
and the SATA port is recognized as expected. 

Since the same u-boot is used to load QNX, the above-mentioned step proves that Pinmux in U-Boot and the hardware is 
good. 

Moreover, I had a brief look into the errata of AM572x and found that section i818, 
************************************************************************************************************************
***
i818 SATA PHY Reset Required Following SATA PLL Unlock
DESCRIPTION If SATA controller is in slumber or partial low-power mode, SATA PHY is in low-power
mode, and SATA 1.5 GHz PLL is relocked for any reason, the PHY receiver looses lock.
In result the receiver / de-serializer is unable to produce parallel data from a correct
serial source, and will not detect the attached SATA drive.

WORKAROUND Workaround is to disable and re-enable both analog LDO of the transceiver, using the
corresponding SW programmable bits of power control MMR: The
CTRL_CORE_PHY_POWER_SATA[21:14] SATA_PWRCTL_CLK_CMD must be set to
0x0 to power down the SATA PHY TX and RX modules.
The rest of the workaround sequence is the same as upon initial SATA PHY power-up,
and includes setting above bits back to 0x2.

 ***********************************************************************************************************************
***

In init_sata.c::50  init_sata_phy(), I see that this function was implemented as per TRM, what  I don't see is that the 
i818 workaround implemented. Maybe this is the issue!?

Abilash