Hi!

I have an Intel haswell 8-core board and I need to do a lot of core-specific operations is kernel mode(in Ring0).
I created a simple interrupt handler and add my code there. So this method works, but only for core 0.

I was really dissapointed when found an information that in QNX all interrupts are handler only on CPU0.
So I have next bunch of questions:

1. What QNX architectural limitations cause this scheme?
2. What about Interprocessor Interrupts - how they are handled with the first point? because of preemption is working..
3. In a Linux system we have IDT on each interrupt. On QNX I found IDT index only on cpu0 and the question is - can I 
create IDT table on another cpu? How can i do it? because as I can copy IDT table to some memory space - I can't put IDT
 table ID into MSR register of a CPU what I want. Or can I? 

As I Understand, startup program works in ring 0 - can I for example create custom IDT on this moment? UserDocs says 
that IDT and GDT are filled automatically by startup library - but I want to do it by hand.

I additionally found that TraceEvent handlers can work on any CPU. 
I attach my handler to _NTO_TRACE_THREAD->_NTO_TRACE_THRUNNING and see that handler is performed on the same cpu as a 
thread which becomes to RUNNING state. 

Is it true or I just lucky and got 1000 of equal iterations?