We're battling an issue where some of our time critical threads just "run slow". We have kernel traces where a group of 
threads run at one rate and then the next iteration, they run roughly twice as long (the threads are not being preempted
, the run time is longer). Our thoughts turn to cache coherency. If some intervening threads run and cause a cache 
change, that would explain the longer run time if there are cache misses and system memory reads were required in the 
slow iterations. We're running on an x86 machine with the "Harpertown" CPU (E5440) that looks to be a dual-die dual-core
 part. Each core has a dedicated 32K L1 cache and two 6 MB L2 caches. Each L2 cache is shared by two of the cores but 
the question is which two? Unix has the cpuinfo command to show the cache sharing (see http://software.intel.com/en-us/
forums/topic/291067). How can we determine the CPU number, from a QNX perspective, to L2 cache association in QNX? In 
Linux, core 0/1 do not share an L2 cache, the sharing is 0/2 and 1/3.

Our goal is to do CPU affinity assignments that increases the likelihood of cache coherency in our time critical threads
. Is there a way to limit which core the procnto threads, actually procnto-smp-instr, run on? When we see cache 
coherency issues, we see some of the higher number procnto threads (i.e. 14) running on cores that we'd like to reserve 
for our time critical use.

Thanks.