Dear QNX forum,

I am trying to understand these call outs implementation,


1.       Is this code is for L1 cache or L2 cache ? if L2 , does L2 also has separate data and instruction cache areas?

2.       cache_mp11_i  and  cache_mp11_d  , what are they representing ? data cahne and instruction cahce?

3.       How much cache memory is available in this file. Is it   32*64*1024/8 = 256 KB ? or it is implementation for a 
512KB cache?

4.       If I want to change it to 1MB cache , what are the changes required ?

5.       Where can I find help for the CP15 instructions used here ? any link ?

6.       Where else we will tell to the QNX OS about the

7.       If this code is not for L2 cache. Pleas provide information / location where I have to see for L2 cache code.


Thanks,
Ravinder Are


#
# Copyright 2007, 2008, QNX Software Systems.
#
# Licensed under the Apache License, Version 2.0 (the "License"). You
# may not reproduce, modify or distribute this software except in
# compliance with the License. You may obtain a copy of the License
# at: http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" basis,
# WITHOUT WARRANTIES OF ANY KIND, either express or implied.
#
# This file may contain contributions from others, either as
# contributors under the License or as licensors under other terms.
# Please review this entire file for other proprietary rights or license
# notices, as well as the QNX Development Suite License Guide at
# http://licensing.qnx.com/license-guide/ for other information.
#
/*
* ARM11 MPcore specific cache operations
*
* unsigned control(paddr32_t base,
*                                                                            unsigned num_lines,
*                                                                            int flags,
*                                                                            struct cacheattr_entry *cache,
*                                                                            volatile struct syspage_entry * )
*/

#include "callout.ah"

#define                MAX_LINES        32
#define                LINE_SIZE            32

CALLOUT_START(cache_mp11_i, 0, 0)
                /*
                * Trim the address to a cache line boundary, and stop at 32 lines
                * to avoid having to re-issue the whole flush if we get preempted
                */
                bic                          r3, r0, #0x1f
                cmp                       r1, #MAX_LINES
                movhi   r1, #MAX_LINES
                mov                       r0, r1

                /*
                * Invalidate lines by address
                */
0:            mcr                        p15, 0, r3, c7, c5, 1
                add                        r3, r3, #LINE_SIZE
                subs       r1, r1, #1
                bne                        0b
                mov                       pc, lr
CALLOUT_END(cache_mp11_i)

CALLOUT_START(cache_mp11_d, 0, 0)
                /*
                * Trim the address to a cache line boundary, and stop at 32 lines
                * to avoid having to re-issue the whole flush if we get preempted
                */
                bic                          r3, r0, #0x1f
                cmp                       r1, #MAX_LINES
                movhi   r1, #MAX_LINES
                mov                       r0, r1

                tst                           r2, #MS_INVALIDATE
                bne                        1f

                /*
                * Clean lines by address
                */
0:            mcr                        p15, 0, r3, c7, c10, 1
                add                        r3, r3, #LINE_SIZE
                subs       r1, r1, #1
                bne                        0b
     ...