I have a system where I'm trying to process data driven by interrupts generated by a PCIe card. I'm using a industrial 
PC mainboard based on Intel's Q35 chipset and a Quadcore processor.

I've disabled every emulation feature I found in the BIOS, disabled serial ports, ACPI, processor SpeedStep, etc..   but
 still I get what appear to be SMI's from time to time (irrgularly).

So I read up on methods to disable the SMI by setting the GBL_SMI_EN register on the LPC bridge. I found the location of
 this register in the Intel ICH9 Datasheet.

Using the pci_read_config32() and pci_write_config32() functions, I attempted to do it in the following order:

* Check whether SMI_LOCK is set  (in GENPMCON_1 register)i
* Read the PMBASE register  (Base Address Register)
* Extract Base Address from this register (bits 7-15)
* [Read the SMI_EN (SMI control and enable) register]
* Unset the GBL_SMI_EN bit in the SMI_EN register.

I get no errors from the pci read/write functions, but I get 0x20 as Base Address -- the contents at which are 0. 
When I try to write to a pci config register, I get no error from the write function, but when it read again, my bits 
were not set!

I'm sure someone here with more experience with either pci configuration space accesses or disabling the SMI and can 
help me out.

User Art Hays had some similar issues he posted back around April '08..  Art, I was wondering if you ever found a 
solution to your SMI problems?

Any help is much appreciated.

~Lorenz